arch/arm/mach-davinci/dm355.c

   1 /*
   2  * TI DaVinci DM355 chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/gpio.h>
  17
  18 #include <linux/spi/spi.h>
  19
  20 #include <asm/mach/map.h>
  21
  22 #include <mach/dm355.h>
  23 #include <mach/clock.h>
  24 #include <mach/cputype.h>
  25 #include <mach/edma.h>
  26 #include <mach/psc.h>
  27 #include <mach/mux.h>
  28 #include <mach/irqs.h>
  29 #include <mach/time.h>
  30 #include <mach/common.h>
  31
  32 #include "clock.h"
  33 #include "mux.h"
  34
  35 /*
  36  * Device specific clocks
  37  */
  38 #define DM355_REF_FREQ          24000000        /* 24 or 36 MHz */
  39
  40 static struct pll_data pll1_data = {
  41         .num       = 1,
  42         .phys_base = DAVINCI_PLL1_BASE,
  43         .flags     = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
  44 };
  45
  46 static struct pll_data pll2_data = {
  47         .num       = 2,
  48         .phys_base = DAVINCI_PLL2_BASE,
  49         .flags     = PLL_HAS_PREDIV,
  50 };
  51
  52 static struct clk ref_clk = {
  53         .name = "ref_clk",
  54         /* FIXME -- crystal rate is board-specific */
  55         .rate = DM355_REF_FREQ,
  56 };
  57
  58 static struct clk pll1_clk = {
  59         .name = "pll1",
  60         .parent = &ref_clk,
  61         .flags = CLK_PLL,
  62         .pll_data = &pll1_data,
  63 };
  64
  65 static struct clk pll1_aux_clk = {
  66         .name = "pll1_aux_clk",
  67         .parent = &pll1_clk,
  68         .flags = CLK_PLL | PRE_PLL,
  69 };
  70
  71 static struct clk pll1_sysclk1 = {
  72         .name = "pll1_sysclk1",
  73         .parent = &pll1_clk,
  74         .flags = CLK_PLL,
  75         .div_reg = PLLDIV1,
  76 };
  77
  78 static struct clk pll1_sysclk2 = {
  79         .name = "pll1_sysclk2",
  80         .parent = &pll1_clk,
  81         .flags = CLK_PLL,
  82         .div_reg = PLLDIV2,
  83 };
  84
  85 static struct clk pll1_sysclk3 = {
  86         .name = "pll1_sysclk3",
  87         .parent = &pll1_clk,
  88         .flags = CLK_PLL,
  89         .div_reg = PLLDIV3,
  90 };
  91
  92 static struct clk pll1_sysclk4 = {
  93         .name = "pll1_sysclk4",
  94         .parent = &pll1_clk,
  95         .flags = CLK_PLL,
  96         .div_reg = PLLDIV4,
  97 };
  98
  99 static struct clk pll1_sysclkbp = {
 100         .name = "pll1_sysclkbp",
 101         .parent = &pll1_clk,
 102         .flags = CLK_PLL | PRE_PLL,
 103         .div_reg = BPDIV
 104 };
 105
 106 static struct clk vpss_dac_clk = {
 107         .name = "vpss_dac",
 108         .parent = &pll1_sysclk3,
 109         .lpsc = DM355_LPSC_VPSS_DAC,
 110 };
 111
 112 static struct clk vpss_master_clk = {
 113         .name = "vpss_master",
 114         .parent = &pll1_sysclk4,
 115         .lpsc = DAVINCI_LPSC_VPSSMSTR,
 116         .flags = CLK_PSC,
 117 };
 118
 119 static struct clk vpss_slave_clk = {
 120         .name = "vpss_slave",
 121         .parent = &pll1_sysclk4,
 122         .lpsc = DAVINCI_LPSC_VPSSSLV,
 123 };
 124
 125
 126 static struct clk clkout1_clk = {
 127         .name = "clkout1",
 128         .parent = &pll1_aux_clk,
 129         /* NOTE:  clkout1 can be externally gated by muxing GPIO-18 */
 130 };
 131
 132 static struct clk clkout2_clk = {
 133         .name = "clkout2",
 134         .parent = &pll1_sysclkbp,
 135 };
 136
 137 static struct clk pll2_clk = {
 138         .name = "pll2",
 139         .parent = &ref_clk,
 140         .flags = CLK_PLL,
 141         .pll_data = &pll2_data,
 142 };
 143
 144 static struct clk pll2_sysclk1 = {
 145         .name = "pll2_sysclk1",
 146         .parent = &pll2_clk,
 147         .flags = CLK_PLL,
 148         .div_reg = PLLDIV1,
 149 };
 150
 151 static struct clk pll2_sysclkbp = {
 152         .name = "pll2_sysclkbp",
 153         .parent = &pll2_clk,
 154         .flags = CLK_PLL | PRE_PLL,
 155         .div_reg = BPDIV
 156 };
 157
 158 static struct clk clkout3_clk = {
 159         .name = "clkout3",
 160         .parent = &pll2_sysclkbp,
 161         /* NOTE:  clkout3 can be externally gated by muxing GPIO-16 */
 162 };
 163
 164 static struct clk arm_clk = {
 165         .name = "arm_clk",
 166         .parent = &pll1_sysclk1,
 167         .lpsc = DAVINCI_LPSC_ARM,
 168         .flags = ALWAYS_ENABLED,
 169 };
 170
 171 /*
 172  * NOT LISTED below, and not touched by Linux
 173  *   - in SyncReset state by default
 174  *      .lpsc = DAVINCI_LPSC_TPCC,
 175  *      .lpsc = DAVINCI_LPSC_TPTC0,
 176  *      .lpsc = DAVINCI_LPSC_TPTC1,
 177  *      .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
 178  *      .lpsc = DAVINCI_LPSC_MEMSTICK,
 179  *   - in Enabled state by default
 180  *      .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
 181  *      .lpsc = DAVINCI_LPSC_SCR2,      // "bus"
 182  *      .lpsc = DAVINCI_LPSC_SCR3,      // "bus"
 183  *      .lpsc = DAVINCI_LPSC_SCR4,      // "bus"
 184  *      .lpsc = DAVINCI_LPSC_CROSSBAR,  // "emulation"
 185  *      .lpsc = DAVINCI_LPSC_CFG27,     // "test"
 186  *      .lpsc = DAVINCI_LPSC_CFG3,      // "test"
 187  *      .lpsc = DAVINCI_LPSC_CFG5,      // "test"
 188  */
 189
 190 static struct clk mjcp_clk = {
 191         .name = "mjcp",
 192         .parent = &pll1_sysclk1,
 193         .lpsc = DAVINCI_LPSC_IMCOP,
 194 };
 195
 196 static struct clk uart0_clk = {
 197         .name = "uart0",
 198         .parent = &pll1_aux_clk,
 199         .lpsc = DAVINCI_LPSC_UART0,
 200 };
 201
 202 static struct clk uart1_clk = {
 203         .name = "uart1",
 204         .parent = &pll1_aux_clk,
 205         .lpsc = DAVINCI_LPSC_UART1,
 206 };
 207
 208 static struct clk uart2_clk = {
 209         .name = "uart2",
 210         .parent = &pll1_sysclk2,
 211         .lpsc = DAVINCI_LPSC_UART2,
 212 };
 213
 214 static struct clk i2c_clk = {
 215         .name = "i2c",
 216         .parent = &pll1_aux_clk,
 217         .lpsc = DAVINCI_LPSC_I2C,
 218 };
 219
 220 static struct clk asp0_clk = {
 221         .name = "asp0",
 222         .parent = &pll1_sysclk2,
 223         .lpsc = DAVINCI_LPSC_McBSP,
 224 };
 225
 226 static struct clk asp1_clk = {
 227         .name = "asp1",
 228         .parent = &pll1_sysclk2,
 229         .lpsc = DM355_LPSC_McBSP1,
 230 };
 231
 232 static struct clk mmcsd0_clk = {
 233         .name = "mmcsd0",
 234         .parent = &pll1_sysclk2,
 235         .lpsc = DAVINCI_LPSC_MMC_SD,
 236 };
 237
 238 static struct clk mmcsd1_clk = {
 239         .name = "mmcsd1",
 240         .parent = &pll1_sysclk2,
 241         .lpsc = DM355_LPSC_MMC_SD1,
 242 };
 243
 244 static struct clk spi0_clk = {
 245         .name = "spi0",
 246         .parent = &pll1_sysclk2,
 247         .lpsc = DAVINCI_LPSC_SPI,
 248 };
 249
 250 static struct clk spi1_clk = {
 251         .name = "spi1",
 252         .parent = &pll1_sysclk2,
 253         .lpsc = DM355_LPSC_SPI1,
 254 };
 255
 256 static struct clk spi2_clk = {
 257         .name = "spi2",
 258         .parent = &pll1_sysclk2,
 259         .lpsc = DM355_LPSC_SPI2,
 260 };
 261
 262 static struct clk gpio_clk = {
 263         .name = "gpio",
 264         .parent = &pll1_sysclk2,
 265         .lpsc = DAVINCI_LPSC_GPIO,
 266 };
 267
 268 static struct clk aemif_clk = {
 269         .name = "aemif",
 270         .parent = &pll1_sysclk2,
 271         .lpsc = DAVINCI_LPSC_AEMIF,
 272 };
 273
 274 static struct clk pwm0_clk = {
 275         .name = "pwm0",
 276         .parent = &pll1_aux_clk,
 277         .lpsc = DAVINCI_LPSC_PWM0,
 278 };
 279
 280 static struct clk pwm1_clk = {
 281         .name = "pwm1",
 282         .parent = &pll1_aux_clk,
 283         .lpsc = DAVINCI_LPSC_PWM1,
 284 };
 285
 286 static struct clk pwm2_clk = {
 287         .name = "pwm2",
 288         .parent = &pll1_aux_clk,
 289         .lpsc = DAVINCI_LPSC_PWM2,
 290 };
 291
 292 static struct clk pwm3_clk = {
 293         .name = "pwm3",
 294         .parent = &pll1_aux_clk,
 295         .lpsc = DM355_LPSC_PWM3,
 296 };
 297
 298 static struct clk timer0_clk = {
 299         .name = "timer0",
 300         .parent = &pll1_aux_clk,
 301         .lpsc = DAVINCI_LPSC_TIMER0,
 302 };
 303
 304 static struct clk timer1_clk = {
 305         .name = "timer1",
 306         .parent = &pll1_aux_clk,
 307         .lpsc = DAVINCI_LPSC_TIMER1,
 308 };
 309
 310 static struct clk timer2_clk = {
 311         .name = "timer2",
 312         .parent = &pll1_aux_clk,
 313         .lpsc = DAVINCI_LPSC_TIMER2,
 314         .usecount = 1,              /* REVISIT: why cant' this be disabled? */
 315 };
 316
 317 static struct clk timer3_clk = {
 318         .name = "timer3",
 319         .parent = &pll1_aux_clk,
 320         .lpsc = DM355_LPSC_TIMER3,
 321 };
 322
 323 static struct clk rto_clk = {
 324         .name = "rto",
 325         .parent = &pll1_aux_clk,
 326         .lpsc = DM355_LPSC_RTO,
 327 };
 328
 329 static struct clk usb_clk = {
 330         .name = "usb",
 331         .parent = &pll1_sysclk2,
 332         .lpsc = DAVINCI_LPSC_USB,
 333 };
 334
 335 static struct davinci_clk dm355_clks[] = {
 336         CLK(NULL, "ref", &ref_clk),
 337         CLK(NULL, "pll1", &pll1_clk),
 338         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 339         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 340         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 341         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
 342         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 343         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 344         CLK(NULL, "vpss_dac", &vpss_dac_clk),
 345         CLK(NULL, "vpss_master", &vpss_master_clk),
 346         CLK(NULL, "vpss_slave", &vpss_slave_clk),
 347         CLK(NULL, "clkout1", &clkout1_clk),
 348         CLK(NULL, "clkout2", &clkout2_clk),
 349         CLK(NULL, "pll2", &pll2_clk),
 350         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 351         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
 352         CLK(NULL, "clkout3", &clkout3_clk),
 353         CLK(NULL, "arm", &arm_clk),
 354         CLK(NULL, "mjcp", &mjcp_clk),
 355         CLK(NULL, "uart0", &uart0_clk),
 356         CLK(NULL, "uart1", &uart1_clk),
 357         CLK(NULL, "uart2", &uart2_clk),
 358         CLK("i2c_davinci.1", NULL, &i2c_clk),
 359         CLK("soc-audio.0", NULL, &asp0_clk),
 360         CLK("soc-audio.1", NULL, &asp1_clk),
 361         CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
 362         CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
 363         CLK(NULL, "spi0", &spi0_clk),
 364         CLK(NULL, "spi1", &spi1_clk),
 365         CLK(NULL, "spi2", &spi2_clk),
 366         CLK(NULL, "gpio", &gpio_clk),
 367         CLK(NULL, "aemif", &aemif_clk),
 368         CLK(NULL, "pwm0", &pwm0_clk),
 369         CLK(NULL, "pwm1", &pwm1_clk),
 370         CLK(NULL, "pwm2", &pwm2_clk),
 371         CLK(NULL, "pwm3", &pwm3_clk),
 372         CLK(NULL, "timer0", &timer0_clk),
 373         CLK(NULL, "timer1", &timer1_clk),
 374         CLK("watchdog", NULL, &timer2_clk),
 375         CLK(NULL, "timer3", &timer3_clk),
 376         CLK(NULL, "rto", &rto_clk),
 377         CLK(NULL, "usb", &usb_clk),
 378         CLK(NULL, NULL, NULL),
 379 };
 380
 381 /*----------------------------------------------------------------------*/
 382
 383 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
 384
 385 static struct resource dm355_spi0_resources[] = {
 386         {
 387                 .start = 0x01c66000,
 388                 .end   = 0x01c667ff,
 389                 .flags = IORESOURCE_MEM,
 390         },
 391         {
 392                 .start = IRQ_DM355_SPINT0_1,
 393                 .flags = IORESOURCE_IRQ,
 394         },
 395         /* Not yet used, so not included:
 396          * IORESOURCE_IRQ:
 397          *  - IRQ_DM355_SPINT0_0
 398          * IORESOURCE_DMA:
 399          *  - DAVINCI_DMA_SPI_SPIX
 400          *  - DAVINCI_DMA_SPI_SPIR
 401          */
 402 };
 403
 404 static struct platform_device dm355_spi0_device = {
 405         .name = "spi_davinci",
 406         .id = 0,
 407         .dev = {
 408                 .dma_mask = &dm355_spi0_dma_mask,
 409                 .coherent_dma_mask = DMA_BIT_MASK(32),
 410         },
 411         .num_resources = ARRAY_SIZE(dm355_spi0_resources),
 412         .resource = dm355_spi0_resources,
 413 };
 414
 415 void __init dm355_init_spi0(unsigned chipselect_mask,
 416                 struct spi_board_info *info, unsigned len)
 417 {
 418         /* for now, assume we need MISO */
 419         davinci_cfg_reg(DM355_SPI0_SDI);
 420
 421         /* not all slaves will be wired up */
 422         if (chipselect_mask & BIT(0))
 423                 davinci_cfg_reg(DM355_SPI0_SDENA0);
 424         if (chipselect_mask & BIT(1))
 425                 davinci_cfg_reg(DM355_SPI0_SDENA1);
 426
 427         spi_register_board_info(info, len);
 428
 429         platform_device_register(&dm355_spi0_device);
 430 }
 431
 432 /*----------------------------------------------------------------------*/
 433
 434 /*
 435  * Device specific mux setup
 436  *
 437  *      soc     description     mux  mode   mode  mux    dbg
 438  *                              reg  offset mask  mode
 439  */
 440 static const struct mux_config dm355_pins[] = {
 441 #ifdef CONFIG_DAVINCI_MUX
 442 MUX_CFG(DM355,  MMCSD0,         4,   2,     1,    0,     false)
 443
 444 MUX_CFG(DM355,  SD1_CLK,        3,   6,     1,    1,     false)
 445 MUX_CFG(DM355,  SD1_CMD,        3,   7,     1,    1,     false)
 446 MUX_CFG(DM355,  SD1_DATA3,      3,   8,     3,    1,     false)
 447 MUX_CFG(DM355,  SD1_DATA2,      3,   10,    3,    1,     false)
 448 MUX_CFG(DM355,  SD1_DATA1,      3,   12,    3,    1,     false)
 449 MUX_CFG(DM355,  SD1_DATA0,      3,   14,    3,    1,     false)
 450
 451 MUX_CFG(DM355,  I2C_SDA,        3,   19,    1,    1,     false)
 452 MUX_CFG(DM355,  I2C_SCL,        3,   20,    1,    1,     false)
 453
 454 MUX_CFG(DM355,  MCBSP0_BDX,     3,   0,     1,    1,     false)
 455 MUX_CFG(DM355,  MCBSP0_X,       3,   1,     1,    1,     false)
 456 MUX_CFG(DM355,  MCBSP0_BFSX,    3,   2,     1,    1,     false)
 457 MUX_CFG(DM355,  MCBSP0_BDR,     3,   3,     1,    1,     false)
 458 MUX_CFG(DM355,  MCBSP0_R,       3,   4,     1,    1,     false)
 459 MUX_CFG(DM355,  MCBSP0_BFSR,    3,   5,     1,    1,     false)
 460
 461 MUX_CFG(DM355,  SPI0_SDI,       4,   1,     1,    0,     false)
 462 MUX_CFG(DM355,  SPI0_SDENA0,    4,   0,     1,    0,     false)
 463 MUX_CFG(DM355,  SPI0_SDENA1,    3,   28,    1,    1,     false)
 464
 465 INT_CFG(DM355,  INT_EDMA_CC,          2,    1,    1,     false)
 466 INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
 467 INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
 468
 469 EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
 470 EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
 471 EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
 472 #endif
 473 };
 474
 475 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 476         [IRQ_DM355_CCDC_VDINT0]         = 2,
 477         [IRQ_DM355_CCDC_VDINT1]         = 6,
 478         [IRQ_DM355_CCDC_VDINT2]         = 6,
 479         [IRQ_DM355_IPIPE_HST]           = 6,
 480         [IRQ_DM355_H3AINT]              = 6,
 481         [IRQ_DM355_IPIPE_SDR]           = 6,
 482         [IRQ_DM355_IPIPEIFINT]          = 6,
 483         [IRQ_DM355_OSDINT]              = 7,
 484         [IRQ_DM355_VENCINT]             = 6,
 485         [IRQ_ASQINT]                    = 6,
 486         [IRQ_IMXINT]                    = 6,
 487         [IRQ_USBINT]                    = 4,
 488         [IRQ_DM355_RTOINT]              = 4,
 489         [IRQ_DM355_UARTINT2]            = 7,
 490         [IRQ_DM355_TINT6]               = 7,
 491         [IRQ_CCINT0]                    = 5,    /* dma */
 492         [IRQ_CCERRINT]                  = 5,    /* dma */
 493         [IRQ_TCERRINT0]                 = 5,    /* dma */
 494         [IRQ_TCERRINT]                  = 5,    /* dma */
 495         [IRQ_DM355_SPINT2_1]            = 7,
 496         [IRQ_DM355_TINT7]               = 4,
 497         [IRQ_DM355_SDIOINT0]            = 7,
 498         [IRQ_MBXINT]                    = 7,
 499         [IRQ_MBRINT]                    = 7,
 500         [IRQ_MMCINT]                    = 7,
 501         [IRQ_DM355_MMCINT1]             = 7,
 502         [IRQ_DM355_PWMINT3]             = 7,
 503         [IRQ_DDRINT]                    = 7,
 504         [IRQ_AEMIFINT]                  = 7,
 505         [IRQ_DM355_SDIOINT1]            = 4,
 506         [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
 507         [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
 508         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 509         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 510         [IRQ_PWMINT0]                   = 7,
 511         [IRQ_PWMINT1]                   = 7,
 512         [IRQ_PWMINT2]                   = 7,
 513         [IRQ_I2C]                       = 3,
 514         [IRQ_UARTINT0]                  = 3,
 515         [IRQ_UARTINT1]                  = 3,
 516         [IRQ_DM355_SPINT0_0]            = 3,
 517         [IRQ_DM355_SPINT0_1]            = 3,
 518         [IRQ_DM355_GPIO0]               = 3,
 519         [IRQ_DM355_GPIO1]               = 7,
 520         [IRQ_DM355_GPIO2]               = 4,
 521         [IRQ_DM355_GPIO3]               = 4,
 522         [IRQ_DM355_GPIO4]               = 7,
 523         [IRQ_DM355_GPIO5]               = 7,
 524         [IRQ_DM355_GPIO6]               = 7,
 525         [IRQ_DM355_GPIO7]               = 7,
 526         [IRQ_DM355_GPIO8]               = 7,
 527         [IRQ_DM355_GPIO9]               = 7,
 528         [IRQ_DM355_GPIOBNK0]            = 7,
 529         [IRQ_DM355_GPIOBNK1]            = 7,
 530         [IRQ_DM355_GPIOBNK2]            = 7,
 531         [IRQ_DM355_GPIOBNK3]            = 7,
 532         [IRQ_DM355_GPIOBNK4]            = 7,
 533         [IRQ_DM355_GPIOBNK5]            = 7,
 534         [IRQ_DM355_GPIOBNK6]            = 7,
 535         [IRQ_COMMTX]                    = 7,
 536         [IRQ_COMMRX]                    = 7,
 537         [IRQ_EMUINT]                    = 7,
 538 };
 539
 540 /*----------------------------------------------------------------------*/
 541
 542 static const s8 dma_chan_dm355_no_event[] = {
 543         12, 13, 24, 56, 57,
 544         58, 59, 60, 61, 62,
 545         63,
 546         -1
 547 };
 548
 549 static struct edma_soc_info dm355_edma_info = {
 550         .n_channel      = 64,
 551         .n_region       = 4,
 552         .n_slot         = 128,
 553         .n_tc           = 2,
 554         .noevent        = dma_chan_dm355_no_event,
 555 };
 556
 557 static struct resource edma_resources[] = {
 558         {
 559                 .name   = "edma_cc",
 560                 .start  = 0x01c00000,
 561                 .end    = 0x01c00000 + SZ_64K - 1,
 562                 .flags  = IORESOURCE_MEM,
 563         },
 564         {
 565                 .name   = "edma_tc0",
 566                 .start  = 0x01c10000,
 567                 .end    = 0x01c10000 + SZ_1K - 1,
 568                 .flags  = IORESOURCE_MEM,
 569         },
 570         {
 571                 .name   = "edma_tc1",
 572                 .start  = 0x01c10400,
 573                 .end    = 0x01c10400 + SZ_1K - 1,
 574                 .flags  = IORESOURCE_MEM,
 575         },
 576         {
 577                 .start  = IRQ_CCINT0,
 578                 .flags  = IORESOURCE_IRQ,
 579         },
 580         {
 581                 .start  = IRQ_CCERRINT,
 582                 .flags  = IORESOURCE_IRQ,
 583         },
 584         /* not using (or muxing) TC*_ERR */
 585 };
 586
 587 static struct platform_device dm355_edma_device = {
 588         .name                   = "edma",
 589         .id                     = -1,
 590         .dev.platform_data      = &dm355_edma_info,
 591         .num_resources          = ARRAY_SIZE(edma_resources),
 592         .resource               = edma_resources,
 593 };
 594
 595 /*----------------------------------------------------------------------*/
 596
 597 static struct map_desc dm355_io_desc[] = {
 598         {
 599                 .virtual        = IO_VIRT,
 600                 .pfn            = __phys_to_pfn(IO_PHYS),
 601                 .length         = IO_SIZE,
 602                 .type           = MT_DEVICE
 603         },
 604 };
 605
 606 /* Contents of JTAG ID register used to identify exact cpu type */
 607 static struct davinci_id dm355_ids[] = {
 608         {
 609                 .variant        = 0x0,
 610                 .part_no        = 0xb73b,
 611                 .manufacturer   = 0x00f,
 612                 .cpu_id         = DAVINCI_CPU_ID_DM355,
 613                 .name           = "dm355",
 614         },
 615 };
 616
 617 static void __iomem *dm355_psc_bases[] = {
 618         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 619 };
 620
 621 /*
 622  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 623  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 624  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 625  * T1_TOP: Timer 1, top   :  <unused>
 626  */
 627 struct davinci_timer_info dm355_timer_info = {
 628         .timers         = davinci_timer_instance,
 629         .clockevent_id  = T0_BOT,
 630         .clocksource_id = T0_TOP,
 631 };
 632
 633 static struct davinci_soc_info davinci_soc_info_dm355 = {
 634         .io_desc                = dm355_io_desc,
 635         .io_desc_num            = ARRAY_SIZE(dm355_io_desc),
 636         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 637         .ids                    = dm355_ids,
 638         .ids_num                = ARRAY_SIZE(dm355_ids),
 639         .cpu_clks               = dm355_clks,
 640         .psc_bases              = dm355_psc_bases,
 641         .psc_bases_num          = ARRAY_SIZE(dm355_psc_bases),
 642         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 643         .pinmux_pins            = dm355_pins,
 644         .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
 645         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
 646         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 647         .intc_irq_prios         = dm355_default_priorities,
 648         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 649         .timer_info             = &dm355_timer_info,
 650         .wdt_base               = IO_ADDRESS(DAVINCI_WDOG_BASE),
 651         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
 652         .gpio_num               = 104,
 653         .gpio_irq               = IRQ_DM355_GPIOBNK0,
 654 };
 655
 656 void __init dm355_init(void)
 657 {
 658         davinci_common_init(&davinci_soc_info_dm355);
 659 }
 660
 661 static int __init dm355_init_devices(void)
 662 {
 663         if (!cpu_is_davinci_dm355())
 664                 return 0;
 665
 666         davinci_cfg_reg(DM355_INT_EDMA_CC);
 667         platform_device_register(&dm355_edma_device);
 668         return 0;
 669 }
 670 postcore_initcall(dm355_init_devices);