arch/arm/mach-davinci/dm644x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/platform_device.h>
  15
  16 #include <asm/mach/map.h>
  17
  18 #include <mach/dm644x.h>
  19 #include <mach/clock.h>
  20 #include <mach/cputype.h>
  21 #include <mach/edma.h>
  22 #include <mach/irqs.h>
  23 #include <mach/psc.h>
  24 #include <mach/mux.h>
  25 #include <mach/common.h>
  26
  27 #include "clock.h"
  28 #include "mux.h"
  29
  30 /*
  31  * Device specific clocks
  32  */
  33 #define DM644X_REF_FREQ         27000000
  34
  35 static struct pll_data pll1_data = {
  36         .num       = 1,
  37         .phys_base = DAVINCI_PLL1_BASE,
  38 };
  39
  40 static struct pll_data pll2_data = {
  41         .num       = 2,
  42         .phys_base = DAVINCI_PLL2_BASE,
  43 };
  44
  45 static struct clk ref_clk = {
  46         .name = "ref_clk",
  47         .rate = DM644X_REF_FREQ,
  48 };
  49
  50 static struct clk pll1_clk = {
  51         .name = "pll1",
  52         .parent = &ref_clk,
  53         .pll_data = &pll1_data,
  54         .flags = CLK_PLL,
  55 };
  56
  57 static struct clk pll1_sysclk1 = {
  58         .name = "pll1_sysclk1",
  59         .parent = &pll1_clk,
  60         .flags = CLK_PLL,
  61         .div_reg = PLLDIV1,
  62 };
  63
  64 static struct clk pll1_sysclk2 = {
  65         .name = "pll1_sysclk2",
  66         .parent = &pll1_clk,
  67         .flags = CLK_PLL,
  68         .div_reg = PLLDIV2,
  69 };
  70
  71 static struct clk pll1_sysclk3 = {
  72         .name = "pll1_sysclk3",
  73         .parent = &pll1_clk,
  74         .flags = CLK_PLL,
  75         .div_reg = PLLDIV3,
  76 };
  77
  78 static struct clk pll1_sysclk5 = {
  79         .name = "pll1_sysclk5",
  80         .parent = &pll1_clk,
  81         .flags = CLK_PLL,
  82         .div_reg = PLLDIV5,
  83 };
  84
  85 static struct clk pll1_aux_clk = {
  86         .name = "pll1_aux_clk",
  87         .parent = &pll1_clk,
  88         .flags = CLK_PLL | PRE_PLL,
  89 };
  90
  91 static struct clk pll1_sysclkbp = {
  92         .name = "pll1_sysclkbp",
  93         .parent = &pll1_clk,
  94         .flags = CLK_PLL | PRE_PLL,
  95         .div_reg = BPDIV
  96 };
  97
  98 static struct clk pll2_clk = {
  99         .name = "pll2",
 100         .parent = &ref_clk,
 101         .pll_data = &pll2_data,
 102         .flags = CLK_PLL,
 103 };
 104
 105 static struct clk pll2_sysclk1 = {
 106         .name = "pll2_sysclk1",
 107         .parent = &pll2_clk,
 108         .flags = CLK_PLL,
 109         .div_reg = PLLDIV1,
 110 };
 111
 112 static struct clk pll2_sysclk2 = {
 113         .name = "pll2_sysclk2",
 114         .parent = &pll2_clk,
 115         .flags = CLK_PLL,
 116         .div_reg = PLLDIV2,
 117 };
 118
 119 static struct clk pll2_sysclkbp = {
 120         .name = "pll2_sysclkbp",
 121         .parent = &pll2_clk,
 122         .flags = CLK_PLL | PRE_PLL,
 123         .div_reg = BPDIV
 124 };
 125
 126 static struct clk dsp_clk = {
 127         .name = "dsp",
 128         .parent = &pll1_sysclk1,
 129         .lpsc = DAVINCI_LPSC_GEM,
 130         .flags = PSC_DSP,
 131         .usecount = 1,                  /* REVISIT how to disable? */
 132 };
 133
 134 static struct clk arm_clk = {
 135         .name = "arm",
 136         .parent = &pll1_sysclk2,
 137         .lpsc = DAVINCI_LPSC_ARM,
 138         .flags = ALWAYS_ENABLED,
 139 };
 140
 141 static struct clk vicp_clk = {
 142         .name = "vicp",
 143         .parent = &pll1_sysclk2,
 144         .lpsc = DAVINCI_LPSC_IMCOP,
 145         .flags = PSC_DSP,
 146         .usecount = 1,                  /* REVISIT how to disable? */
 147 };
 148
 149 static struct clk vpss_master_clk = {
 150         .name = "vpss_master",
 151         .parent = &pll1_sysclk3,
 152         .lpsc = DAVINCI_LPSC_VPSSMSTR,
 153         .flags = CLK_PSC,
 154 };
 155
 156 static struct clk vpss_slave_clk = {
 157         .name = "vpss_slave",
 158         .parent = &pll1_sysclk3,
 159         .lpsc = DAVINCI_LPSC_VPSSSLV,
 160 };
 161
 162 static struct clk uart0_clk = {
 163         .name = "uart0",
 164         .parent = &pll1_aux_clk,
 165         .lpsc = DAVINCI_LPSC_UART0,
 166 };
 167
 168 static struct clk uart1_clk = {
 169         .name = "uart1",
 170         .parent = &pll1_aux_clk,
 171         .lpsc = DAVINCI_LPSC_UART1,
 172 };
 173
 174 static struct clk uart2_clk = {
 175         .name = "uart2",
 176         .parent = &pll1_aux_clk,
 177         .lpsc = DAVINCI_LPSC_UART2,
 178 };
 179
 180 static struct clk emac_clk = {
 181         .name = "emac",
 182         .parent = &pll1_sysclk5,
 183         .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
 184 };
 185
 186 static struct clk i2c_clk = {
 187         .name = "i2c",
 188         .parent = &pll1_aux_clk,
 189         .lpsc = DAVINCI_LPSC_I2C,
 190 };
 191
 192 static struct clk ide_clk = {
 193         .name = "ide",
 194         .parent = &pll1_sysclk5,
 195         .lpsc = DAVINCI_LPSC_ATA,
 196 };
 197
 198 static struct clk asp_clk = {
 199         .name = "asp0",
 200         .parent = &pll1_sysclk5,
 201         .lpsc = DAVINCI_LPSC_McBSP,
 202 };
 203
 204 static struct clk mmcsd_clk = {
 205         .name = "mmcsd",
 206         .parent = &pll1_sysclk5,
 207         .lpsc = DAVINCI_LPSC_MMC_SD,
 208 };
 209
 210 static struct clk spi_clk = {
 211         .name = "spi",
 212         .parent = &pll1_sysclk5,
 213         .lpsc = DAVINCI_LPSC_SPI,
 214 };
 215
 216 static struct clk gpio_clk = {
 217         .name = "gpio",
 218         .parent = &pll1_sysclk5,
 219         .lpsc = DAVINCI_LPSC_GPIO,
 220 };
 221
 222 static struct clk usb_clk = {
 223         .name = "usb",
 224         .parent = &pll1_sysclk5,
 225         .lpsc = DAVINCI_LPSC_USB,
 226 };
 227
 228 static struct clk vlynq_clk = {
 229         .name = "vlynq",
 230         .parent = &pll1_sysclk5,
 231         .lpsc = DAVINCI_LPSC_VLYNQ,
 232 };
 233
 234 static struct clk aemif_clk = {
 235         .name = "aemif",
 236         .parent = &pll1_sysclk5,
 237         .lpsc = DAVINCI_LPSC_AEMIF,
 238 };
 239
 240 static struct clk pwm0_clk = {
 241         .name = "pwm0",
 242         .parent = &pll1_aux_clk,
 243         .lpsc = DAVINCI_LPSC_PWM0,
 244 };
 245
 246 static struct clk pwm1_clk = {
 247         .name = "pwm1",
 248         .parent = &pll1_aux_clk,
 249         .lpsc = DAVINCI_LPSC_PWM1,
 250 };
 251
 252 static struct clk pwm2_clk = {
 253         .name = "pwm2",
 254         .parent = &pll1_aux_clk,
 255         .lpsc = DAVINCI_LPSC_PWM2,
 256 };
 257
 258 static struct clk timer0_clk = {
 259         .name = "timer0",
 260         .parent = &pll1_aux_clk,
 261         .lpsc = DAVINCI_LPSC_TIMER0,
 262 };
 263
 264 static struct clk timer1_clk = {
 265         .name = "timer1",
 266         .parent = &pll1_aux_clk,
 267         .lpsc = DAVINCI_LPSC_TIMER1,
 268 };
 269
 270 static struct clk timer2_clk = {
 271         .name = "timer2",
 272         .parent = &pll1_aux_clk,
 273         .lpsc = DAVINCI_LPSC_TIMER2,
 274         .usecount = 1,              /* REVISIT: why cant' this be disabled? */
 275 };
 276
 277 struct davinci_clk dm644x_clks[] = {
 278         CLK(NULL, "ref", &ref_clk),
 279         CLK(NULL, "pll1", &pll1_clk),
 280         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 281         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 282         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 283         CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
 284         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 285         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 286         CLK(NULL, "pll2", &pll2_clk),
 287         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 288         CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
 289         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
 290         CLK(NULL, "dsp", &dsp_clk),
 291         CLK(NULL, "arm", &arm_clk),
 292         CLK(NULL, "vicp", &vicp_clk),
 293         CLK(NULL, "vpss_master", &vpss_master_clk),
 294         CLK(NULL, "vpss_slave", &vpss_slave_clk),
 295         CLK(NULL, "arm", &arm_clk),
 296         CLK(NULL, "uart0", &uart0_clk),
 297         CLK(NULL, "uart1", &uart1_clk),
 298         CLK(NULL, "uart2", &uart2_clk),
 299         CLK("davinci_emac.1", NULL, &emac_clk),
 300         CLK("i2c_davinci.1", NULL, &i2c_clk),
 301         CLK("palm_bk3710", NULL, &ide_clk),
 302         CLK("soc-audio.0", NULL, &asp_clk),
 303         CLK("davinci_mmc.0", NULL, &mmcsd_clk),
 304         CLK(NULL, "spi", &spi_clk),
 305         CLK(NULL, "gpio", &gpio_clk),
 306         CLK(NULL, "usb", &usb_clk),
 307         CLK(NULL, "vlynq", &vlynq_clk),
 308         CLK(NULL, "aemif", &aemif_clk),
 309         CLK(NULL, "pwm0", &pwm0_clk),
 310         CLK(NULL, "pwm1", &pwm1_clk),
 311         CLK(NULL, "pwm2", &pwm2_clk),
 312         CLK(NULL, "timer0", &timer0_clk),
 313         CLK(NULL, "timer1", &timer1_clk),
 314         CLK("watchdog", NULL, &timer2_clk),
 315         CLK(NULL, NULL, NULL),
 316 };
 317
 318 #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
 319
 320 static struct resource dm644x_emac_resources[] = {
 321         {
 322                 .start  = DM644X_EMAC_BASE,
 323                 .end    = DM644X_EMAC_BASE + 0x47ff,
 324                 .flags  = IORESOURCE_MEM,
 325         },
 326         {
 327                 .start = IRQ_EMACINT,
 328                 .end   = IRQ_EMACINT,
 329                 .flags = IORESOURCE_IRQ,
 330         },
 331 };
 332
 333 static struct platform_device dm644x_emac_device = {
 334        .name            = "davinci_emac",
 335        .id              = 1,
 336        .num_resources   = ARRAY_SIZE(dm644x_emac_resources),
 337        .resource        = dm644x_emac_resources,
 338 };
 339
 340 #endif
 341
 342 /*
 343  * Device specific mux setup
 344  *
 345  *      soc     description     mux  mode   mode  mux    dbg
 346  *                              reg  offset mask  mode
 347  */
 348 static const struct mux_config dm644x_pins[] = {
 349 #ifdef CONFIG_DAVINCI_MUX
 350 MUX_CFG(DM644X, HDIREN,         0,   16,    1,    1,     true)
 351 MUX_CFG(DM644X, ATAEN,          0,   17,    1,    1,     true)
 352 MUX_CFG(DM644X, ATAEN_DISABLE,  0,   17,    1,    0,     true)
 353
 354 MUX_CFG(DM644X, HPIEN_DISABLE,  0,   29,    1,    0,     true)
 355
 356 MUX_CFG(DM644X, AEAW,           0,   0,     31,   31,    true)
 357
 358 MUX_CFG(DM644X, MSTK,           1,   9,     1,    0,     false)
 359
 360 MUX_CFG(DM644X, I2C,            1,   7,     1,    1,     false)
 361
 362 MUX_CFG(DM644X, MCBSP,          1,   10,    1,    1,     false)
 363
 364 MUX_CFG(DM644X, UART1,          1,   1,     1,    1,     true)
 365 MUX_CFG(DM644X, UART2,          1,   2,     1,    1,     true)
 366
 367 MUX_CFG(DM644X, PWM0,           1,   4,     1,    1,     false)
 368
 369 MUX_CFG(DM644X, PWM1,           1,   5,     1,    1,     false)
 370
 371 MUX_CFG(DM644X, PWM2,           1,   6,     1,    1,     false)
 372
 373 MUX_CFG(DM644X, VLYNQEN,        0,   15,    1,    1,     false)
 374 MUX_CFG(DM644X, VLSCREN,        0,   14,    1,    1,     false)
 375 MUX_CFG(DM644X, VLYNQWD,        0,   12,    3,    3,     false)
 376
 377 MUX_CFG(DM644X, EMACEN,         0,   31,    1,    1,     true)
 378
 379 MUX_CFG(DM644X, GPIO3V,         0,   31,    1,    0,     true)
 380
 381 MUX_CFG(DM644X, GPIO0,          0,   24,    1,    0,     true)
 382 MUX_CFG(DM644X, GPIO3,          0,   25,    1,    0,     false)
 383 MUX_CFG(DM644X, GPIO43_44,      1,   7,     1,    0,     false)
 384 MUX_CFG(DM644X, GPIO46_47,      0,   22,    1,    0,     true)
 385
 386 MUX_CFG(DM644X, RGB666,         0,   22,    1,    1,     true)
 387
 388 MUX_CFG(DM644X, LOEEN,          0,   24,    1,    1,     true)
 389 MUX_CFG(DM644X, LFLDEN,         0,   25,    1,    1,     false)
 390 #endif
 391 };
 392
 393 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 394 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 395         [IRQ_VDINT0]            = 2,
 396         [IRQ_VDINT1]            = 6,
 397         [IRQ_VDINT2]            = 6,
 398         [IRQ_HISTINT]           = 6,
 399         [IRQ_H3AINT]            = 6,
 400         [IRQ_PRVUINT]           = 6,
 401         [IRQ_RSZINT]            = 6,
 402         [7]                     = 7,
 403         [IRQ_VENCINT]           = 6,
 404         [IRQ_ASQINT]            = 6,
 405         [IRQ_IMXINT]            = 6,
 406         [IRQ_VLCDINT]           = 6,
 407         [IRQ_USBINT]            = 4,
 408         [IRQ_EMACINT]           = 4,
 409         [14]                    = 7,
 410         [15]                    = 7,
 411         [IRQ_CCINT0]            = 5,    /* dma */
 412         [IRQ_CCERRINT]          = 5,    /* dma */
 413         [IRQ_TCERRINT0]         = 5,    /* dma */
 414         [IRQ_TCERRINT]          = 5,    /* dma */
 415         [IRQ_PSCIN]             = 7,
 416         [21]                    = 7,
 417         [IRQ_IDE]               = 4,
 418         [23]                    = 7,
 419         [IRQ_MBXINT]            = 7,
 420         [IRQ_MBRINT]            = 7,
 421         [IRQ_MMCINT]            = 7,
 422         [IRQ_SDIOINT]           = 7,
 423         [28]                    = 7,
 424         [IRQ_DDRINT]            = 7,
 425         [IRQ_AEMIFINT]          = 7,
 426         [IRQ_VLQINT]            = 4,
 427         [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
 428         [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
 429         [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
 430         [IRQ_TINT1_TINT34]      = 7,    /* system tick */
 431         [IRQ_PWMINT0]           = 7,
 432         [IRQ_PWMINT1]           = 7,
 433         [IRQ_PWMINT2]           = 7,
 434         [IRQ_I2C]               = 3,
 435         [IRQ_UARTINT0]          = 3,
 436         [IRQ_UARTINT1]          = 3,
 437         [IRQ_UARTINT2]          = 3,
 438         [IRQ_SPINT0]            = 3,
 439         [IRQ_SPINT1]            = 3,
 440         [45]                    = 7,
 441         [IRQ_DSP2ARM0]          = 4,
 442         [IRQ_DSP2ARM1]          = 4,
 443         [IRQ_GPIO0]             = 7,
 444         [IRQ_GPIO1]             = 7,
 445         [IRQ_GPIO2]             = 7,
 446         [IRQ_GPIO3]             = 7,
 447         [IRQ_GPIO4]             = 7,
 448         [IRQ_GPIO5]             = 7,
 449         [IRQ_GPIO6]             = 7,
 450         [IRQ_GPIO7]             = 7,
 451         [IRQ_GPIOBNK0]          = 7,
 452         [IRQ_GPIOBNK1]          = 7,
 453         [IRQ_GPIOBNK2]          = 7,
 454         [IRQ_GPIOBNK3]          = 7,
 455         [IRQ_GPIOBNK4]          = 7,
 456         [IRQ_COMMTX]            = 7,
 457         [IRQ_COMMRX]            = 7,
 458         [IRQ_EMUINT]            = 7,
 459 };
 460
 461 /*----------------------------------------------------------------------*/
 462
 463 static const s8 dma_chan_dm644x_no_event[] = {
 464          0,  1, 12, 13, 14,
 465         15, 25, 30, 31, 45,
 466         46, 47, 55, 56, 57,
 467         58, 59, 60, 61, 62,
 468         63,
 469         -1
 470 };
 471
 472 static struct edma_soc_info dm644x_edma_info = {
 473         .n_channel      = 64,
 474         .n_region       = 4,
 475         .n_slot         = 128,
 476         .n_tc           = 2,
 477         .noevent        = dma_chan_dm644x_no_event,
 478 };
 479
 480 static struct resource edma_resources[] = {
 481         {
 482                 .name   = "edma_cc",
 483                 .start  = 0x01c00000,
 484                 .end    = 0x01c00000 + SZ_64K - 1,
 485                 .flags  = IORESOURCE_MEM,
 486         },
 487         {
 488                 .name   = "edma_tc0",
 489                 .start  = 0x01c10000,
 490                 .end    = 0x01c10000 + SZ_1K - 1,
 491                 .flags  = IORESOURCE_MEM,
 492         },
 493         {
 494                 .name   = "edma_tc1",
 495                 .start  = 0x01c10400,
 496                 .end    = 0x01c10400 + SZ_1K - 1,
 497                 .flags  = IORESOURCE_MEM,
 498         },
 499         {
 500                 .start  = IRQ_CCINT0,
 501                 .flags  = IORESOURCE_IRQ,
 502         },
 503         {
 504                 .start  = IRQ_CCERRINT,
 505                 .flags  = IORESOURCE_IRQ,
 506         },
 507         /* not using TC*_ERR */
 508 };
 509
 510 static struct platform_device dm644x_edma_device = {
 511         .name                   = "edma",
 512         .id                     = -1,
 513         .dev.platform_data      = &dm644x_edma_info,
 514         .num_resources          = ARRAY_SIZE(edma_resources),
 515         .resource               = edma_resources,
 516 };
 517
 518 /*----------------------------------------------------------------------*/
 519 #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
 520
 521 void dm644x_init_emac(struct emac_platform_data *pdata)
 522 {
 523         pdata->ctrl_reg_offset          = DM644X_EMAC_CNTRL_OFFSET;
 524         pdata->ctrl_mod_reg_offset      = DM644X_EMAC_CNTRL_MOD_OFFSET;
 525         pdata->ctrl_ram_offset          = DM644X_EMAC_CNTRL_RAM_OFFSET;
 526         pdata->mdio_reg_offset          = DM644X_EMAC_MDIO_OFFSET;
 527         pdata->ctrl_ram_size            = DM644X_EMAC_CNTRL_RAM_SIZE;
 528         pdata->version                  = EMAC_VERSION_1;
 529         dm644x_emac_device.dev.platform_data = pdata;
 530         platform_device_register(&dm644x_emac_device);
 531 }
 532 #else
 533
 534 void dm644x_init_emac(struct emac_platform_data *unused) {}
 535
 536 #endif
 537
 538 static struct map_desc dm644x_io_desc[] = {
 539         {
 540                 .virtual        = IO_VIRT,
 541                 .pfn            = __phys_to_pfn(IO_PHYS),
 542                 .length         = IO_SIZE,
 543                 .type           = MT_DEVICE
 544         },
 545 };
 546
 547 /* Contents of JTAG ID register used to identify exact cpu type */
 548 static struct davinci_id dm644x_ids[] = {
 549         {
 550                 .variant        = 0x0,
 551                 .part_no        = 0xb700,
 552                 .manufacturer   = 0x017,
 553                 .cpu_id         = DAVINCI_CPU_ID_DM6446,
 554                 .name           = "dm6446",
 555         },
 556 };
 557
 558 static void __iomem *dm644x_psc_bases[] = {
 559         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 560 };
 561
 562 static struct davinci_soc_info davinci_soc_info_dm644x = {
 563         .io_desc                = dm644x_io_desc,
 564         .io_desc_num            = ARRAY_SIZE(dm644x_io_desc),
 565         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 566         .ids                    = dm644x_ids,
 567         .ids_num                = ARRAY_SIZE(dm644x_ids),
 568         .cpu_clks               = dm644x_clks,
 569         .psc_bases              = dm644x_psc_bases,
 570         .psc_bases_num          = ARRAY_SIZE(dm644x_psc_bases),
 571         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 572         .pinmux_pins            = dm644x_pins,
 573         .pinmux_pins_num        = ARRAY_SIZE(dm644x_pins),
 574         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
 575         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 576         .intc_irq_prios         = dm644x_default_priorities,
 577         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 578 };
 579
 580 void __init dm644x_init(void)
 581 {
 582         davinci_common_init(&davinci_soc_info_dm644x);
 583 }
 584
 585 static int __init dm644x_init_devices(void)
 586 {
 587         if (!cpu_is_davinci_dm644x())
 588                 return 0;
 589
 590         platform_device_register(&dm644x_edma_device);
 591         return 0;
 592 }
 593 postcore_initcall(dm644x_init_devices);