arch/arm/mach-davinci/dm644x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/platform_device.h>
  15
  16 #include <asm/mach/map.h>
  17
  18 #include <mach/dm644x.h>
  19 #include <mach/clock.h>
  20 #include <mach/cputype.h>
  21 #include <mach/edma.h>
  22 #include <mach/irqs.h>
  23 #include <mach/psc.h>
  24 #include <mach/mux.h>
  25 #include <mach/time.h>
  26 #include <mach/common.h>
  27
  28 #include "clock.h"
  29 #include "mux.h"
  30
  31 /*
  32  * Device specific clocks
  33  */
  34 #define DM644X_REF_FREQ         27000000
  35
  36 static struct pll_data pll1_data = {
  37         .num       = 1,
  38         .phys_base = DAVINCI_PLL1_BASE,
  39 };
  40
  41 static struct pll_data pll2_data = {
  42         .num       = 2,
  43         .phys_base = DAVINCI_PLL2_BASE,
  44 };
  45
  46 static struct clk ref_clk = {
  47         .name = "ref_clk",
  48         .rate = DM644X_REF_FREQ,
  49 };
  50
  51 static struct clk pll1_clk = {
  52         .name = "pll1",
  53         .parent = &ref_clk,
  54         .pll_data = &pll1_data,
  55         .flags = CLK_PLL,
  56 };
  57
  58 static struct clk pll1_sysclk1 = {
  59         .name = "pll1_sysclk1",
  60         .parent = &pll1_clk,
  61         .flags = CLK_PLL,
  62         .div_reg = PLLDIV1,
  63 };
  64
  65 static struct clk pll1_sysclk2 = {
  66         .name = "pll1_sysclk2",
  67         .parent = &pll1_clk,
  68         .flags = CLK_PLL,
  69         .div_reg = PLLDIV2,
  70 };
  71
  72 static struct clk pll1_sysclk3 = {
  73         .name = "pll1_sysclk3",
  74         .parent = &pll1_clk,
  75         .flags = CLK_PLL,
  76         .div_reg = PLLDIV3,
  77 };
  78
  79 static struct clk pll1_sysclk5 = {
  80         .name = "pll1_sysclk5",
  81         .parent = &pll1_clk,
  82         .flags = CLK_PLL,
  83         .div_reg = PLLDIV5,
  84 };
  85
  86 static struct clk pll1_aux_clk = {
  87         .name = "pll1_aux_clk",
  88         .parent = &pll1_clk,
  89         .flags = CLK_PLL | PRE_PLL,
  90 };
  91
  92 static struct clk pll1_sysclkbp = {
  93         .name = "pll1_sysclkbp",
  94         .parent = &pll1_clk,
  95         .flags = CLK_PLL | PRE_PLL,
  96         .div_reg = BPDIV
  97 };
  98
  99 static struct clk pll2_clk = {
 100         .name = "pll2",
 101         .parent = &ref_clk,
 102         .pll_data = &pll2_data,
 103         .flags = CLK_PLL,
 104 };
 105
 106 static struct clk pll2_sysclk1 = {
 107         .name = "pll2_sysclk1",
 108         .parent = &pll2_clk,
 109         .flags = CLK_PLL,
 110         .div_reg = PLLDIV1,
 111 };
 112
 113 static struct clk pll2_sysclk2 = {
 114         .name = "pll2_sysclk2",
 115         .parent = &pll2_clk,
 116         .flags = CLK_PLL,
 117         .div_reg = PLLDIV2,
 118 };
 119
 120 static struct clk pll2_sysclkbp = {
 121         .name = "pll2_sysclkbp",
 122         .parent = &pll2_clk,
 123         .flags = CLK_PLL | PRE_PLL,
 124         .div_reg = BPDIV
 125 };
 126
 127 static struct clk dsp_clk = {
 128         .name = "dsp",
 129         .parent = &pll1_sysclk1,
 130         .lpsc = DAVINCI_LPSC_GEM,
 131         .flags = PSC_DSP,
 132         .usecount = 1,                  /* REVISIT how to disable? */
 133 };
 134
 135 static struct clk arm_clk = {
 136         .name = "arm",
 137         .parent = &pll1_sysclk2,
 138         .lpsc = DAVINCI_LPSC_ARM,
 139         .flags = ALWAYS_ENABLED,
 140 };
 141
 142 static struct clk vicp_clk = {
 143         .name = "vicp",
 144         .parent = &pll1_sysclk2,
 145         .lpsc = DAVINCI_LPSC_IMCOP,
 146         .flags = PSC_DSP,
 147         .usecount = 1,                  /* REVISIT how to disable? */
 148 };
 149
 150 static struct clk vpss_master_clk = {
 151         .name = "vpss_master",
 152         .parent = &pll1_sysclk3,
 153         .lpsc = DAVINCI_LPSC_VPSSMSTR,
 154         .flags = CLK_PSC,
 155 };
 156
 157 static struct clk vpss_slave_clk = {
 158         .name = "vpss_slave",
 159         .parent = &pll1_sysclk3,
 160         .lpsc = DAVINCI_LPSC_VPSSSLV,
 161 };
 162
 163 static struct clk uart0_clk = {
 164         .name = "uart0",
 165         .parent = &pll1_aux_clk,
 166         .lpsc = DAVINCI_LPSC_UART0,
 167 };
 168
 169 static struct clk uart1_clk = {
 170         .name = "uart1",
 171         .parent = &pll1_aux_clk,
 172         .lpsc = DAVINCI_LPSC_UART1,
 173 };
 174
 175 static struct clk uart2_clk = {
 176         .name = "uart2",
 177         .parent = &pll1_aux_clk,
 178         .lpsc = DAVINCI_LPSC_UART2,
 179 };
 180
 181 static struct clk emac_clk = {
 182         .name = "emac",
 183         .parent = &pll1_sysclk5,
 184         .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
 185 };
 186
 187 static struct clk i2c_clk = {
 188         .name = "i2c",
 189         .parent = &pll1_aux_clk,
 190         .lpsc = DAVINCI_LPSC_I2C,
 191 };
 192
 193 static struct clk ide_clk = {
 194         .name = "ide",
 195         .parent = &pll1_sysclk5,
 196         .lpsc = DAVINCI_LPSC_ATA,
 197 };
 198
 199 static struct clk asp_clk = {
 200         .name = "asp0",
 201         .parent = &pll1_sysclk5,
 202         .lpsc = DAVINCI_LPSC_McBSP,
 203 };
 204
 205 static struct clk mmcsd_clk = {
 206         .name = "mmcsd",
 207         .parent = &pll1_sysclk5,
 208         .lpsc = DAVINCI_LPSC_MMC_SD,
 209 };
 210
 211 static struct clk spi_clk = {
 212         .name = "spi",
 213         .parent = &pll1_sysclk5,
 214         .lpsc = DAVINCI_LPSC_SPI,
 215 };
 216
 217 static struct clk gpio_clk = {
 218         .name = "gpio",
 219         .parent = &pll1_sysclk5,
 220         .lpsc = DAVINCI_LPSC_GPIO,
 221 };
 222
 223 static struct clk usb_clk = {
 224         .name = "usb",
 225         .parent = &pll1_sysclk5,
 226         .lpsc = DAVINCI_LPSC_USB,
 227 };
 228
 229 static struct clk vlynq_clk = {
 230         .name = "vlynq",
 231         .parent = &pll1_sysclk5,
 232         .lpsc = DAVINCI_LPSC_VLYNQ,
 233 };
 234
 235 static struct clk aemif_clk = {
 236         .name = "aemif",
 237         .parent = &pll1_sysclk5,
 238         .lpsc = DAVINCI_LPSC_AEMIF,
 239 };
 240
 241 static struct clk pwm0_clk = {
 242         .name = "pwm0",
 243         .parent = &pll1_aux_clk,
 244         .lpsc = DAVINCI_LPSC_PWM0,
 245 };
 246
 247 static struct clk pwm1_clk = {
 248         .name = "pwm1",
 249         .parent = &pll1_aux_clk,
 250         .lpsc = DAVINCI_LPSC_PWM1,
 251 };
 252
 253 static struct clk pwm2_clk = {
 254         .name = "pwm2",
 255         .parent = &pll1_aux_clk,
 256         .lpsc = DAVINCI_LPSC_PWM2,
 257 };
 258
 259 static struct clk timer0_clk = {
 260         .name = "timer0",
 261         .parent = &pll1_aux_clk,
 262         .lpsc = DAVINCI_LPSC_TIMER0,
 263 };
 264
 265 static struct clk timer1_clk = {
 266         .name = "timer1",
 267         .parent = &pll1_aux_clk,
 268         .lpsc = DAVINCI_LPSC_TIMER1,
 269 };
 270
 271 static struct clk timer2_clk = {
 272         .name = "timer2",
 273         .parent = &pll1_aux_clk,
 274         .lpsc = DAVINCI_LPSC_TIMER2,
 275         .usecount = 1,              /* REVISIT: why cant' this be disabled? */
 276 };
 277
 278 struct davinci_clk dm644x_clks[] = {
 279         CLK(NULL, "ref", &ref_clk),
 280         CLK(NULL, "pll1", &pll1_clk),
 281         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 282         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 283         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 284         CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
 285         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 286         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 287         CLK(NULL, "pll2", &pll2_clk),
 288         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 289         CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
 290         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
 291         CLK(NULL, "dsp", &dsp_clk),
 292         CLK(NULL, "arm", &arm_clk),
 293         CLK(NULL, "vicp", &vicp_clk),
 294         CLK(NULL, "vpss_master", &vpss_master_clk),
 295         CLK(NULL, "vpss_slave", &vpss_slave_clk),
 296         CLK(NULL, "arm", &arm_clk),
 297         CLK(NULL, "uart0", &uart0_clk),
 298         CLK(NULL, "uart1", &uart1_clk),
 299         CLK(NULL, "uart2", &uart2_clk),
 300         CLK("davinci_emac.1", NULL, &emac_clk),
 301         CLK("i2c_davinci.1", NULL, &i2c_clk),
 302         CLK("palm_bk3710", NULL, &ide_clk),
 303         CLK("soc-audio.0", NULL, &asp_clk),
 304         CLK("davinci_mmc.0", NULL, &mmcsd_clk),
 305         CLK(NULL, "spi", &spi_clk),
 306         CLK(NULL, "gpio", &gpio_clk),
 307         CLK(NULL, "usb", &usb_clk),
 308         CLK(NULL, "vlynq", &vlynq_clk),
 309         CLK(NULL, "aemif", &aemif_clk),
 310         CLK(NULL, "pwm0", &pwm0_clk),
 311         CLK(NULL, "pwm1", &pwm1_clk),
 312         CLK(NULL, "pwm2", &pwm2_clk),
 313         CLK(NULL, "timer0", &timer0_clk),
 314         CLK(NULL, "timer1", &timer1_clk),
 315         CLK("watchdog", NULL, &timer2_clk),
 316         CLK(NULL, NULL, NULL),
 317 };
 318
 319 #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
 320
 321 static struct resource dm644x_emac_resources[] = {
 322         {
 323                 .start  = DM644X_EMAC_BASE,
 324                 .end    = DM644X_EMAC_BASE + 0x47ff,
 325                 .flags  = IORESOURCE_MEM,
 326         },
 327         {
 328                 .start = IRQ_EMACINT,
 329                 .end   = IRQ_EMACINT,
 330                 .flags = IORESOURCE_IRQ,
 331         },
 332 };
 333
 334 static struct platform_device dm644x_emac_device = {
 335        .name            = "davinci_emac",
 336        .id              = 1,
 337        .num_resources   = ARRAY_SIZE(dm644x_emac_resources),
 338        .resource        = dm644x_emac_resources,
 339 };
 340
 341 #endif
 342
 343 /*
 344  * Device specific mux setup
 345  *
 346  *      soc     description     mux  mode   mode  mux    dbg
 347  *                              reg  offset mask  mode
 348  */
 349 static const struct mux_config dm644x_pins[] = {
 350 #ifdef CONFIG_DAVINCI_MUX
 351 MUX_CFG(DM644X, HDIREN,         0,   16,    1,    1,     true)
 352 MUX_CFG(DM644X, ATAEN,          0,   17,    1,    1,     true)
 353 MUX_CFG(DM644X, ATAEN_DISABLE,  0,   17,    1,    0,     true)
 354
 355 MUX_CFG(DM644X, HPIEN_DISABLE,  0,   29,    1,    0,     true)
 356
 357 MUX_CFG(DM644X, AEAW,           0,   0,     31,   31,    true)
 358
 359 MUX_CFG(DM644X, MSTK,           1,   9,     1,    0,     false)
 360
 361 MUX_CFG(DM644X, I2C,            1,   7,     1,    1,     false)
 362
 363 MUX_CFG(DM644X, MCBSP,          1,   10,    1,    1,     false)
 364
 365 MUX_CFG(DM644X, UART1,          1,   1,     1,    1,     true)
 366 MUX_CFG(DM644X, UART2,          1,   2,     1,    1,     true)
 367
 368 MUX_CFG(DM644X, PWM0,           1,   4,     1,    1,     false)
 369
 370 MUX_CFG(DM644X, PWM1,           1,   5,     1,    1,     false)
 371
 372 MUX_CFG(DM644X, PWM2,           1,   6,     1,    1,     false)
 373
 374 MUX_CFG(DM644X, VLYNQEN,        0,   15,    1,    1,     false)
 375 MUX_CFG(DM644X, VLSCREN,        0,   14,    1,    1,     false)
 376 MUX_CFG(DM644X, VLYNQWD,        0,   12,    3,    3,     false)
 377
 378 MUX_CFG(DM644X, EMACEN,         0,   31,    1,    1,     true)
 379
 380 MUX_CFG(DM644X, GPIO3V,         0,   31,    1,    0,     true)
 381
 382 MUX_CFG(DM644X, GPIO0,          0,   24,    1,    0,     true)
 383 MUX_CFG(DM644X, GPIO3,          0,   25,    1,    0,     false)
 384 MUX_CFG(DM644X, GPIO43_44,      1,   7,     1,    0,     false)
 385 MUX_CFG(DM644X, GPIO46_47,      0,   22,    1,    0,     true)
 386
 387 MUX_CFG(DM644X, RGB666,         0,   22,    1,    1,     true)
 388
 389 MUX_CFG(DM644X, LOEEN,          0,   24,    1,    1,     true)
 390 MUX_CFG(DM644X, LFLDEN,         0,   25,    1,    1,     false)
 391 #endif
 392 };
 393
 394 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 395 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 396         [IRQ_VDINT0]            = 2,
 397         [IRQ_VDINT1]            = 6,
 398         [IRQ_VDINT2]            = 6,
 399         [IRQ_HISTINT]           = 6,
 400         [IRQ_H3AINT]            = 6,
 401         [IRQ_PRVUINT]           = 6,
 402         [IRQ_RSZINT]            = 6,
 403         [7]                     = 7,
 404         [IRQ_VENCINT]           = 6,
 405         [IRQ_ASQINT]            = 6,
 406         [IRQ_IMXINT]            = 6,
 407         [IRQ_VLCDINT]           = 6,
 408         [IRQ_USBINT]            = 4,
 409         [IRQ_EMACINT]           = 4,
 410         [14]                    = 7,
 411         [15]                    = 7,
 412         [IRQ_CCINT0]            = 5,    /* dma */
 413         [IRQ_CCERRINT]          = 5,    /* dma */
 414         [IRQ_TCERRINT0]         = 5,    /* dma */
 415         [IRQ_TCERRINT]          = 5,    /* dma */
 416         [IRQ_PSCIN]             = 7,
 417         [21]                    = 7,
 418         [IRQ_IDE]               = 4,
 419         [23]                    = 7,
 420         [IRQ_MBXINT]            = 7,
 421         [IRQ_MBRINT]            = 7,
 422         [IRQ_MMCINT]            = 7,
 423         [IRQ_SDIOINT]           = 7,
 424         [28]                    = 7,
 425         [IRQ_DDRINT]            = 7,
 426         [IRQ_AEMIFINT]          = 7,
 427         [IRQ_VLQINT]            = 4,
 428         [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
 429         [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
 430         [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
 431         [IRQ_TINT1_TINT34]      = 7,    /* system tick */
 432         [IRQ_PWMINT0]           = 7,
 433         [IRQ_PWMINT1]           = 7,
 434         [IRQ_PWMINT2]           = 7,
 435         [IRQ_I2C]               = 3,
 436         [IRQ_UARTINT0]          = 3,
 437         [IRQ_UARTINT1]          = 3,
 438         [IRQ_UARTINT2]          = 3,
 439         [IRQ_SPINT0]            = 3,
 440         [IRQ_SPINT1]            = 3,
 441         [45]                    = 7,
 442         [IRQ_DSP2ARM0]          = 4,
 443         [IRQ_DSP2ARM1]          = 4,
 444         [IRQ_GPIO0]             = 7,
 445         [IRQ_GPIO1]             = 7,
 446         [IRQ_GPIO2]             = 7,
 447         [IRQ_GPIO3]             = 7,
 448         [IRQ_GPIO4]             = 7,
 449         [IRQ_GPIO5]             = 7,
 450         [IRQ_GPIO6]             = 7,
 451         [IRQ_GPIO7]             = 7,
 452         [IRQ_GPIOBNK0]          = 7,
 453         [IRQ_GPIOBNK1]          = 7,
 454         [IRQ_GPIOBNK2]          = 7,
 455         [IRQ_GPIOBNK3]          = 7,
 456         [IRQ_GPIOBNK4]          = 7,
 457         [IRQ_COMMTX]            = 7,
 458         [IRQ_COMMRX]            = 7,
 459         [IRQ_EMUINT]            = 7,
 460 };
 461
 462 /*----------------------------------------------------------------------*/
 463
 464 static const s8 dma_chan_dm644x_no_event[] = {
 465          0,  1, 12, 13, 14,
 466         15, 25, 30, 31, 45,
 467         46, 47, 55, 56, 57,
 468         58, 59, 60, 61, 62,
 469         63,
 470         -1
 471 };
 472
 473 static struct edma_soc_info dm644x_edma_info = {
 474         .n_channel      = 64,
 475         .n_region       = 4,
 476         .n_slot         = 128,
 477         .n_tc           = 2,
 478         .noevent        = dma_chan_dm644x_no_event,
 479 };
 480
 481 static struct resource edma_resources[] = {
 482         {
 483                 .name   = "edma_cc",
 484                 .start  = 0x01c00000,
 485                 .end    = 0x01c00000 + SZ_64K - 1,
 486                 .flags  = IORESOURCE_MEM,
 487         },
 488         {
 489                 .name   = "edma_tc0",
 490                 .start  = 0x01c10000,
 491                 .end    = 0x01c10000 + SZ_1K - 1,
 492                 .flags  = IORESOURCE_MEM,
 493         },
 494         {
 495                 .name   = "edma_tc1",
 496                 .start  = 0x01c10400,
 497                 .end    = 0x01c10400 + SZ_1K - 1,
 498                 .flags  = IORESOURCE_MEM,
 499         },
 500         {
 501                 .start  = IRQ_CCINT0,
 502                 .flags  = IORESOURCE_IRQ,
 503         },
 504         {
 505                 .start  = IRQ_CCERRINT,
 506                 .flags  = IORESOURCE_IRQ,
 507         },
 508         /* not using TC*_ERR */
 509 };
 510
 511 static struct platform_device dm644x_edma_device = {
 512         .name                   = "edma",
 513         .id                     = -1,
 514         .dev.platform_data      = &dm644x_edma_info,
 515         .num_resources          = ARRAY_SIZE(edma_resources),
 516         .resource               = edma_resources,
 517 };
 518
 519 /*----------------------------------------------------------------------*/
 520 #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
 521
 522 void dm644x_init_emac(struct emac_platform_data *pdata)
 523 {
 524         pdata->ctrl_reg_offset          = DM644X_EMAC_CNTRL_OFFSET;
 525         pdata->ctrl_mod_reg_offset      = DM644X_EMAC_CNTRL_MOD_OFFSET;
 526         pdata->ctrl_ram_offset          = DM644X_EMAC_CNTRL_RAM_OFFSET;
 527         pdata->mdio_reg_offset          = DM644X_EMAC_MDIO_OFFSET;
 528         pdata->ctrl_ram_size            = DM644X_EMAC_CNTRL_RAM_SIZE;
 529         pdata->version                  = EMAC_VERSION_1;
 530         dm644x_emac_device.dev.platform_data = pdata;
 531         platform_device_register(&dm644x_emac_device);
 532 }
 533 #else
 534
 535 void dm644x_init_emac(struct emac_platform_data *unused) {}
 536
 537 #endif
 538
 539 static struct map_desc dm644x_io_desc[] = {
 540         {
 541                 .virtual        = IO_VIRT,
 542                 .pfn            = __phys_to_pfn(IO_PHYS),
 543                 .length         = IO_SIZE,
 544                 .type           = MT_DEVICE
 545         },
 546 };
 547
 548 /* Contents of JTAG ID register used to identify exact cpu type */
 549 static struct davinci_id dm644x_ids[] = {
 550         {
 551                 .variant        = 0x0,
 552                 .part_no        = 0xb700,
 553                 .manufacturer   = 0x017,
 554                 .cpu_id         = DAVINCI_CPU_ID_DM6446,
 555                 .name           = "dm6446",
 556         },
 557 };
 558
 559 static void __iomem *dm644x_psc_bases[] = {
 560         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 561 };
 562
 563 /*
 564  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 565  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 566  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 567  * T1_TOP: Timer 1, top   :  <unused>
 568  */
 569 struct davinci_timer_info dm644x_timer_info = {
 570         .timers         = davinci_timer_instance,
 571         .clockevent_id  = T0_BOT,
 572         .clocksource_id = T0_TOP,
 573 };
 574
 575 static struct davinci_soc_info davinci_soc_info_dm644x = {
 576         .io_desc                = dm644x_io_desc,
 577         .io_desc_num            = ARRAY_SIZE(dm644x_io_desc),
 578         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 579         .ids                    = dm644x_ids,
 580         .ids_num                = ARRAY_SIZE(dm644x_ids),
 581         .cpu_clks               = dm644x_clks,
 582         .psc_bases              = dm644x_psc_bases,
 583         .psc_bases_num          = ARRAY_SIZE(dm644x_psc_bases),
 584         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 585         .pinmux_pins            = dm644x_pins,
 586         .pinmux_pins_num        = ARRAY_SIZE(dm644x_pins),
 587         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
 588         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 589         .intc_irq_prios         = dm644x_default_priorities,
 590         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 591         .timer_info             = &dm644x_timer_info,
 592         .wdt_base               = IO_ADDRESS(DAVINCI_WDOG_BASE),
 593 };
 594
 595 void __init dm644x_init(void)
 596 {
 597         davinci_common_init(&davinci_soc_info_dm644x);
 598 }
 599
 600 static int __init dm644x_init_devices(void)
 601 {
 602         if (!cpu_is_davinci_dm644x())
 603                 return 0;
 604
 605         platform_device_register(&dm644x_edma_device);
 606         return 0;
 607 }
 608 postcore_initcall(dm644x_init_devices);