2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/platform_device.h>
16 #include <mach/dm646x.h>
17 #include <mach/clock.h>
18 #include <mach/cputype.h>
19 #include <mach/edma.h>
20 #include <mach/irqs.h>
28 * Device specific clocks
30 #define DM646X_REF_FREQ 27000000
31 #define DM646X_AUX_FREQ 24000000
33 static struct pll_data pll1_data = {
35 .phys_base = DAVINCI_PLL1_BASE,
38 static struct pll_data pll2_data = {
40 .phys_base = DAVINCI_PLL2_BASE,
43 static struct clk ref_clk = {
45 .rate = DM646X_REF_FREQ,
48 static struct clk aux_clkin = {
50 .rate = DM646X_AUX_FREQ,
53 static struct clk pll1_clk = {
56 .pll_data = &pll1_data,
60 static struct clk pll1_sysclk1 = {
61 .name = "pll1_sysclk1",
67 static struct clk pll1_sysclk2 = {
68 .name = "pll1_sysclk2",
74 static struct clk pll1_sysclk3 = {
75 .name = "pll1_sysclk3",
81 static struct clk pll1_sysclk4 = {
82 .name = "pll1_sysclk4",
88 static struct clk pll1_sysclk5 = {
89 .name = "pll1_sysclk5",
95 static struct clk pll1_sysclk6 = {
96 .name = "pll1_sysclk6",
102 static struct clk pll1_sysclk8 = {
103 .name = "pll1_sysclk8",
109 static struct clk pll1_sysclk9 = {
110 .name = "pll1_sysclk9",
116 static struct clk pll1_sysclkbp = {
117 .name = "pll1_sysclkbp",
119 .flags = CLK_PLL | PRE_PLL,
123 static struct clk pll1_aux_clk = {
124 .name = "pll1_aux_clk",
126 .flags = CLK_PLL | PRE_PLL,
129 static struct clk pll2_clk = {
132 .pll_data = &pll2_data,
136 static struct clk pll2_sysclk1 = {
137 .name = "pll2_sysclk1",
143 static struct clk dsp_clk = {
145 .parent = &pll1_sysclk1,
146 .lpsc = DM646X_LPSC_C64X_CPU,
148 .usecount = 1, /* REVISIT how to disable? */
151 static struct clk arm_clk = {
153 .parent = &pll1_sysclk2,
154 .lpsc = DM646X_LPSC_ARM,
155 .flags = ALWAYS_ENABLED,
158 static struct clk uart0_clk = {
160 .parent = &aux_clkin,
161 .lpsc = DM646X_LPSC_UART0,
164 static struct clk uart1_clk = {
166 .parent = &aux_clkin,
167 .lpsc = DM646X_LPSC_UART1,
170 static struct clk uart2_clk = {
172 .parent = &aux_clkin,
173 .lpsc = DM646X_LPSC_UART2,
176 static struct clk i2c_clk = {
178 .parent = &pll1_sysclk3,
179 .lpsc = DM646X_LPSC_I2C,
182 static struct clk gpio_clk = {
184 .parent = &pll1_sysclk3,
185 .lpsc = DM646X_LPSC_GPIO,
188 static struct clk aemif_clk = {
190 .parent = &pll1_sysclk3,
191 .lpsc = DM646X_LPSC_AEMIF,
192 .flags = ALWAYS_ENABLED,
195 static struct clk emac_clk = {
197 .parent = &pll1_sysclk3,
198 .lpsc = DM646X_LPSC_EMAC,
201 static struct clk pwm0_clk = {
203 .parent = &pll1_sysclk3,
204 .lpsc = DM646X_LPSC_PWM0,
205 .usecount = 1, /* REVIST: disabling hangs system */
208 static struct clk pwm1_clk = {
210 .parent = &pll1_sysclk3,
211 .lpsc = DM646X_LPSC_PWM1,
212 .usecount = 1, /* REVIST: disabling hangs system */
215 static struct clk timer0_clk = {
217 .parent = &pll1_sysclk3,
218 .lpsc = DM646X_LPSC_TIMER0,
221 static struct clk timer1_clk = {
223 .parent = &pll1_sysclk3,
224 .lpsc = DM646X_LPSC_TIMER1,
227 static struct clk timer2_clk = {
229 .parent = &pll1_sysclk3,
230 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
233 static struct clk vpif0_clk = {
236 .lpsc = DM646X_LPSC_VPSSMSTR,
237 .flags = ALWAYS_ENABLED,
240 static struct clk vpif1_clk = {
243 .lpsc = DM646X_LPSC_VPSSSLV,
244 .flags = ALWAYS_ENABLED,
247 struct davinci_clk dm646x_clks[] = {
248 CLK(NULL, "ref", &ref_clk),
249 CLK(NULL, "aux", &aux_clkin),
250 CLK(NULL, "pll1", &pll1_clk),
251 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
252 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
253 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
254 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
255 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
256 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
257 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
258 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
259 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
260 CLK(NULL, "pll1_aux", &pll1_aux_clk),
261 CLK(NULL, "pll2", &pll2_clk),
262 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
263 CLK(NULL, "dsp", &dsp_clk),
264 CLK(NULL, "arm", &arm_clk),
265 CLK(NULL, "uart0", &uart0_clk),
266 CLK(NULL, "uart1", &uart1_clk),
267 CLK(NULL, "uart2", &uart2_clk),
268 CLK("i2c_davinci.1", NULL, &i2c_clk),
269 CLK(NULL, "gpio", &gpio_clk),
270 CLK(NULL, "aemif", &aemif_clk),
271 CLK("davinci_emac.1", NULL, &emac_clk),
272 CLK(NULL, "pwm0", &pwm0_clk),
273 CLK(NULL, "pwm1", &pwm1_clk),
274 CLK(NULL, "timer0", &timer0_clk),
275 CLK(NULL, "timer1", &timer1_clk),
276 CLK("watchdog", NULL, &timer2_clk),
277 CLK(NULL, "vpif0", &vpif0_clk),
278 CLK(NULL, "vpif1", &vpif1_clk),
279 CLK(NULL, NULL, NULL),
282 #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
283 static struct resource dm646x_emac_resources[] = {
285 .start = DM646X_EMAC_BASE,
286 .end = DM646X_EMAC_BASE + 0x47ff,
287 .flags = IORESOURCE_MEM,
290 .start = IRQ_DM646X_EMACRXTHINT,
291 .end = IRQ_DM646X_EMACRXTHINT,
292 .flags = IORESOURCE_IRQ,
295 .start = IRQ_DM646X_EMACRXINT,
296 .end = IRQ_DM646X_EMACRXINT,
297 .flags = IORESOURCE_IRQ,
300 .start = IRQ_DM646X_EMACTXINT,
301 .end = IRQ_DM646X_EMACTXINT,
302 .flags = IORESOURCE_IRQ,
305 .start = IRQ_DM646X_EMACMISCINT,
306 .end = IRQ_DM646X_EMACMISCINT,
307 .flags = IORESOURCE_IRQ,
311 static struct platform_device dm646x_emac_device = {
312 .name = "davinci_emac",
314 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
315 .resource = dm646x_emac_resources,
321 * Device specific mux setup
323 * soc description mux mode mode mux dbg
324 * reg offset mask mode
326 static const struct mux_config dm646x_pins[] = {
327 MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true)
329 MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
331 MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
333 MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
335 MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
337 MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
339 MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
341 MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
343 MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
345 MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
347 MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
349 MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
351 MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
353 MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
356 /*----------------------------------------------------------------------*/
358 static const s8 dma_chan_dm646x_no_event[] = {
366 static struct edma_soc_info dm646x_edma_info = {
368 .n_region = 6, /* 0-1, 4-7 */
371 .noevent = dma_chan_dm646x_no_event,
374 static struct resource edma_resources[] = {
378 .end = 0x01c00000 + SZ_64K - 1,
379 .flags = IORESOURCE_MEM,
384 .end = 0x01c10000 + SZ_1K - 1,
385 .flags = IORESOURCE_MEM,
390 .end = 0x01c10400 + SZ_1K - 1,
391 .flags = IORESOURCE_MEM,
396 .end = 0x01c10800 + SZ_1K - 1,
397 .flags = IORESOURCE_MEM,
402 .end = 0x01c10c00 + SZ_1K - 1,
403 .flags = IORESOURCE_MEM,
407 .flags = IORESOURCE_IRQ,
410 .start = IRQ_CCERRINT,
411 .flags = IORESOURCE_IRQ,
413 /* not using TC*_ERR */
416 static struct platform_device dm646x_edma_device = {
419 .dev.platform_data = &dm646x_edma_info,
420 .num_resources = ARRAY_SIZE(edma_resources),
421 .resource = edma_resources,
424 /*----------------------------------------------------------------------*/
426 #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
428 void dm646x_init_emac(struct emac_platform_data *pdata)
430 pdata->ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET;
431 pdata->ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET;
432 pdata->ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET;
433 pdata->mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET;
434 pdata->ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE;
435 pdata->version = EMAC_VERSION_2;
436 dm646x_emac_device.dev.platform_data = pdata;
437 platform_device_register(&dm646x_emac_device);
441 void dm646x_init_emac(struct emac_platform_data *unused) {}
445 void __init dm646x_init(void)
447 davinci_clk_init(dm646x_clks);
448 davinci_mux_register(dm646x_pins, ARRAY_SIZE(dm646x_pins));
451 static int __init dm646x_init_devices(void)
453 if (!cpu_is_davinci_dm646x())
456 platform_device_register(&dm646x_edma_device);
459 postcore_initcall(dm646x_init_devices);