2 * DaVinci timer subsystem
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/clocksource.h>
16 #include <linux/clockchips.h>
17 #include <linux/spinlock.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/device.h>
22 #include <linux/platform_device.h>
24 #include <mach/hardware.h>
25 #include <asm/system.h>
27 #include <asm/mach/irq.h>
28 #include <asm/mach/time.h>
29 #include <asm/errno.h>
31 #include <mach/cputype.h>
32 #include <mach/time.h>
35 static struct clock_event_device clockevent_davinci;
36 static unsigned int davinci_clock_tick_rate;
38 #define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
41 * This driver configures the 2 64-bit count-up timers as 4 independent
42 * 32-bit count-up timers used as follows:
50 /* Timer register offsets */
60 /* Timer register bitfields */
61 #define TCR_ENAMODE_DISABLE 0x0
62 #define TCR_ENAMODE_ONESHOT 0x1
63 #define TCR_ENAMODE_PERIODIC 0x2
64 #define TCR_ENAMODE_MASK 0x3
66 #define TGCR_TIMMODE_SHIFT 2
67 #define TGCR_TIMMODE_64BIT_GP 0x0
68 #define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
69 #define TGCR_TIMMODE_64BIT_WDOG 0x2
70 #define TGCR_TIMMODE_32BIT_CHAINED 0x3
72 #define TGCR_TIM12RS_SHIFT 0
73 #define TGCR_TIM34RS_SHIFT 1
74 #define TGCR_RESET 0x0
75 #define TGCR_UNRESET 0x1
76 #define TGCR_RESET_MASK 0x3
78 #define WDTCR_WDEN_SHIFT 14
79 #define WDTCR_WDEN_DISABLE 0x0
80 #define WDTCR_WDEN_ENABLE 0x1
81 #define WDTCR_WDKEY_SHIFT 16
82 #define WDTCR_WDKEY_SEQ0 0xa5c6
83 #define WDTCR_WDKEY_SEQ1 0xda7e
91 unsigned long tim_off;
92 unsigned long prd_off;
93 unsigned long enamode_shift;
94 struct irqaction irqaction;
96 static struct timer_s timers[];
98 /* values for 'opts' field of struct timer_s */
99 #define TIMER_OPTS_DISABLED 0x00
100 #define TIMER_OPTS_ONESHOT 0x01
101 #define TIMER_OPTS_PERIODIC 0x02
103 static char *id_to_name[] = {
104 [T0_BOT] = "timer0_0",
105 [T0_TOP] = "timer0_1",
106 [T1_BOT] = "timer1_0",
107 [T1_TOP] = "timer1_1",
110 static int timer32_config(struct timer_s *t)
112 u32 tcr = __raw_readl(t->base + TCR);
115 tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
116 __raw_writel(tcr, t->base + TCR);
118 /* reset counter to zero, set new period */
119 __raw_writel(0, t->base + t->tim_off);
120 __raw_writel(t->period, t->base + t->prd_off);
122 /* Set enable mode */
123 if (t->opts & TIMER_OPTS_ONESHOT) {
124 tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
125 } else if (t->opts & TIMER_OPTS_PERIODIC) {
126 tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
129 __raw_writel(tcr, t->base + TCR);
133 static inline u32 timer32_read(struct timer_s *t)
135 return __raw_readl(t->base + t->tim_off);
138 static irqreturn_t timer_interrupt(int irq, void *dev_id)
140 struct clock_event_device *evt = &clockevent_davinci;
142 evt->event_handler(evt);
146 /* called when 32-bit counter wraps */
147 static irqreturn_t freerun_interrupt(int irq, void *dev_id)
152 static struct timer_s timers[] = {
154 .name = "clockevent",
155 .opts = TIMER_OPTS_DISABLED,
157 .flags = IRQF_DISABLED | IRQF_TIMER,
158 .handler = timer_interrupt,
161 [TID_CLOCKSOURCE] = {
162 .name = "free-run counter",
164 .opts = TIMER_OPTS_PERIODIC,
166 .flags = IRQF_DISABLED | IRQF_TIMER,
167 .handler = freerun_interrupt,
172 static void __init timer_init(void)
174 struct davinci_soc_info *soc_info = &davinci_soc_info;
175 struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
178 /* Global init of each 64-bit timer as a whole */
181 void __iomem *base = dtip[i].base;
183 /* Disabled, Internal clock source */
184 __raw_writel(0, base + TCR);
186 /* reset both timers, no pre-scaler for timer34 */
188 __raw_writel(tgcr, base + TGCR);
190 /* Set both timers to unchained 32-bit */
191 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
192 __raw_writel(tgcr, base + TGCR);
195 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
196 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
197 __raw_writel(tgcr, base + TGCR);
199 /* Init both counters to zero */
200 __raw_writel(0, base + TIM12);
201 __raw_writel(0, base + TIM34);
204 /* Init of each timer as a 32-bit timer */
205 for (i=0; i< ARRAY_SIZE(timers); i++) {
206 struct timer_s *t = &timers[i];
207 int timer = ID_TO_TIMER(t->id);
210 t->base = dtip[timer].base;
212 if (IS_TIMER_BOT(t->id)) {
213 t->enamode_shift = 6;
216 irq = dtip[timer].bottom_irq;
218 t->enamode_shift = 22;
221 irq = dtip[timer].top_irq;
224 /* Register interrupt */
225 t->irqaction.name = t->name;
226 t->irqaction.dev_id = (void *)t;
227 if (t->irqaction.handler != NULL)
228 setup_irq(irq, &t->irqaction);
230 timer32_config(&timers[i]);
237 static cycle_t read_cycles(struct clocksource *cs)
239 struct timer_s *t = &timers[TID_CLOCKSOURCE];
241 return (cycles_t)timer32_read(t);
244 static struct clocksource clocksource_davinci = {
247 .mask = CLOCKSOURCE_MASK(32),
249 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
255 static int davinci_set_next_event(unsigned long cycles,
256 struct clock_event_device *evt)
258 struct timer_s *t = &timers[TID_CLOCKEVENT];
265 static void davinci_set_mode(enum clock_event_mode mode,
266 struct clock_event_device *evt)
268 struct timer_s *t = &timers[TID_CLOCKEVENT];
271 case CLOCK_EVT_MODE_PERIODIC:
272 t->period = davinci_clock_tick_rate / (HZ);
273 t->opts = TIMER_OPTS_PERIODIC;
276 case CLOCK_EVT_MODE_ONESHOT:
277 t->opts = TIMER_OPTS_ONESHOT;
279 case CLOCK_EVT_MODE_UNUSED:
280 case CLOCK_EVT_MODE_SHUTDOWN:
281 t->opts = TIMER_OPTS_DISABLED;
283 case CLOCK_EVT_MODE_RESUME:
288 static struct clock_event_device clockevent_davinci = {
289 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
291 .set_next_event = davinci_set_next_event,
292 .set_mode = davinci_set_mode,
296 static void __init davinci_timer_init(void)
298 struct clk *timer_clk;
299 struct davinci_soc_info *soc_info = &davinci_soc_info;
301 static char err[] __initdata = KERN_ERR
302 "%s: can't register clocksource!\n";
304 timers[TID_CLOCKEVENT].id = soc_info->timer_info->clockevent_id;
305 timers[TID_CLOCKSOURCE].id = soc_info->timer_info->clocksource_id;
310 timer_clk = clk_get(NULL, "timer0");
311 BUG_ON(IS_ERR(timer_clk));
312 clk_enable(timer_clk);
314 davinci_clock_tick_rate = clk_get_rate(timer_clk);
316 /* setup clocksource */
317 clocksource_davinci.name = id_to_name[timers[TID_CLOCKSOURCE].id];
318 clocksource_davinci.mult =
319 clocksource_khz2mult(davinci_clock_tick_rate/1000,
320 clocksource_davinci.shift);
321 if (clocksource_register(&clocksource_davinci))
322 printk(err, clocksource_davinci.name);
324 /* setup clockevent */
325 clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id];
326 clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
327 clockevent_davinci.shift);
328 clockevent_davinci.max_delta_ns =
329 clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
330 clockevent_davinci.min_delta_ns =
331 clockevent_delta2ns(1, &clockevent_davinci);
333 clockevent_davinci.cpumask = cpumask_of(0);
334 clockevents_register_device(&clockevent_davinci);
337 struct sys_timer davinci_timer = {
338 .init = davinci_timer_init,
342 /* reset board using watchdog timer */
343 void davinci_watchdog_reset(void)
346 void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE);
349 wd_clk = clk_get(&davinci_wdt_device.dev, NULL);
350 if (WARN_ON(IS_ERR(wd_clk)))
354 /* disable, internal clock source */
355 __raw_writel(0, base + TCR);
357 /* reset timer, set mode to 64-bit watchdog, and unreset */
359 __raw_writel(tgcr, base + TCR);
360 tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
361 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
362 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
363 __raw_writel(tgcr, base + TCR);
365 /* clear counter and period regs */
366 __raw_writel(0, base + TIM12);
367 __raw_writel(0, base + TIM34);
368 __raw_writel(0, base + PRD12);
369 __raw_writel(0, base + PRD34);
372 wdtcr = __raw_readl(base + WDTCR);
373 wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT;
374 __raw_writel(wdtcr, base + WDTCR);
376 /* put watchdog in pre-active state */
377 wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
378 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
379 __raw_writel(wdtcr, base + WDTCR);
381 /* put watchdog in active state */
382 wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
383 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
384 __raw_writel(wdtcr, base + WDTCR);
386 /* write an invalid value to the WDKEY field to trigger
387 * a watchdog reset */
389 __raw_writel(wdtcr, base + WDTCR);