arch/arm/mach-exynos/clock-exynos5.c

   1 /*
   2  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Clock support for EXYNOS5 SoCs
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/syscore_ops.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23 #include <plat/pm.h>
  24
  25 #include <mach/map.h>
  26 #include <mach/regs-clock.h>
  27 #include <mach/sysmmu.h>
  28
  29 #include "common.h"
  30
  31 #ifdef CONFIG_PM_SLEEP
  32 static struct sleep_save exynos5_clock_save[] = {
  33         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
  34         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
  35         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
  36         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
  37         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
  38         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
  39         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
  40         SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
  41         SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
  42         SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
  43         SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
  44         SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
  45         SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
  46         SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
  47         SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
  48         SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
  49         SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
  50         SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
  51         SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
  52         SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
  53         SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
  54         SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
  55         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
  56         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
  57         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
  58         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
  59         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
  60         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
  61         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
  62         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
  63         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
  64         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
  65         SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
  66         SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
  67         SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
  68         SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
  69         SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
  70         SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
  71         SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
  72         SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
  73         SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
  74         SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
  75         SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
  76         SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
  77         SAVE_ITEM(EXYNOS5_EPLL_CON0),
  78         SAVE_ITEM(EXYNOS5_EPLL_CON1),
  79         SAVE_ITEM(EXYNOS5_EPLL_CON2),
  80         SAVE_ITEM(EXYNOS5_VPLL_CON0),
  81         SAVE_ITEM(EXYNOS5_VPLL_CON1),
  82         SAVE_ITEM(EXYNOS5_VPLL_CON2),
  83 };
  84 #endif
  85
  86 static struct clk exynos5_clk_sclk_dptxphy = {
  87         .name           = "sclk_dptx",
  88 };
  89
  90 static struct clk exynos5_clk_sclk_hdmi24m = {
  91         .name           = "sclk_hdmi24m",
  92         .rate           = 24000000,
  93 };
  94
  95 static struct clk exynos5_clk_sclk_hdmi27m = {
  96         .name           = "sclk_hdmi27m",
  97         .rate           = 27000000,
  98 };
  99
 100 static struct clk exynos5_clk_sclk_hdmiphy = {
 101         .name           = "sclk_hdmiphy",
 102 };
 103
 104 static struct clk exynos5_clk_sclk_usbphy = {
 105         .name           = "sclk_usbphy",
 106         .rate           = 48000000,
 107 };
 108
 109 static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 110 {
 111         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
 112 }
 113
 114 static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
 115 {
 116         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
 117 }
 118
 119 static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 120 {
 121         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
 122 }
 123
 124 static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
 125 {
 126         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
 127 }
 128
 129 static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
 130 {
 131         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
 132 }
 133
 134 static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
 135 {
 136         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
 137 }
 138
 139 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
 140 {
 141         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
 142 }
 143
 144 static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
 145 {
 146         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
 147 }
 148
 149 static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 150 {
 151         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
 152 }
 153
 154 static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
 155 {
 156         return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
 157 }
 158
 159 static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
 160 {
 161         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
 162 }
 163
 164 static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
 165 {
 166         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
 167 }
 168
 169 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 170 {
 171         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
 172 }
 173
 174 static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
 175 {
 176         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
 177 }
 178
 179 static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
 180 {
 181         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
 182 }
 183
 184 static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
 185 {
 186         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
 187 }
 188
 189 static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
 190 {
 191         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
 192 }
 193
 194 static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
 195 {
 196         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
 197 }
 198
 199 /* Core list of CMU_CPU side */
 200
 201 static struct clksrc_clk exynos5_clk_mout_apll = {
 202         .clk    = {
 203                 .name           = "mout_apll",
 204         },
 205         .sources = &clk_src_apll,
 206         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
 207 };
 208
 209 static struct clksrc_clk exynos5_clk_sclk_apll = {
 210         .clk    = {
 211                 .name           = "sclk_apll",
 212                 .parent         = &exynos5_clk_mout_apll.clk,
 213         },
 214         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 215 };
 216
 217 static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
 218         .clk    = {
 219                 .name           = "mout_bpll_fout",
 220         },
 221         .sources = &clk_src_bpll_fout,
 222         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
 223 };
 224
 225 static struct clk *exynos5_clk_src_bpll_list[] = {
 226         [0] = &clk_fin_bpll,
 227         [1] = &exynos5_clk_mout_bpll_fout.clk,
 228 };
 229
 230 static struct clksrc_sources exynos5_clk_src_bpll = {
 231         .sources        = exynos5_clk_src_bpll_list,
 232         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
 233 };
 234
 235 static struct clksrc_clk exynos5_clk_mout_bpll = {
 236         .clk    = {
 237                 .name           = "mout_bpll",
 238         },
 239         .sources = &exynos5_clk_src_bpll,
 240         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
 241 };
 242
 243 static struct clk *exynos5_clk_src_bpll_user_list[] = {
 244         [0] = &clk_fin_mpll,
 245         [1] = &exynos5_clk_mout_bpll.clk,
 246 };
 247
 248 static struct clksrc_sources exynos5_clk_src_bpll_user = {
 249         .sources        = exynos5_clk_src_bpll_user_list,
 250         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
 251 };
 252
 253 static struct clksrc_clk exynos5_clk_mout_bpll_user = {
 254         .clk    = {
 255                 .name           = "mout_bpll_user",
 256         },
 257         .sources = &exynos5_clk_src_bpll_user,
 258         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
 259 };
 260
 261 static struct clksrc_clk exynos5_clk_mout_cpll = {
 262         .clk    = {
 263                 .name           = "mout_cpll",
 264         },
 265         .sources = &clk_src_cpll,
 266         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
 267 };
 268
 269 static struct clksrc_clk exynos5_clk_mout_epll = {
 270         .clk    = {
 271                 .name           = "mout_epll",
 272         },
 273         .sources = &clk_src_epll,
 274         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 275 };
 276
 277 static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
 278         .clk    = {
 279                 .name           = "mout_mpll_fout",
 280         },
 281         .sources = &clk_src_mpll_fout,
 282         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
 283 };
 284
 285 static struct clk *exynos5_clk_src_mpll_list[] = {
 286         [0] = &clk_fin_mpll,
 287         [1] = &exynos5_clk_mout_mpll_fout.clk,
 288 };
 289
 290 static struct clksrc_sources exynos5_clk_src_mpll = {
 291         .sources        = exynos5_clk_src_mpll_list,
 292         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
 293 };
 294
 295 struct clksrc_clk exynos5_clk_mout_mpll = {
 296         .clk = {
 297                 .name           = "mout_mpll",
 298         },
 299         .sources = &exynos5_clk_src_mpll,
 300         .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 301 };
 302
 303 static struct clk *exynos_clkset_vpllsrc_list[] = {
 304         [0] = &clk_fin_vpll,
 305         [1] = &exynos5_clk_sclk_hdmi27m,
 306 };
 307
 308 static struct clksrc_sources exynos5_clkset_vpllsrc = {
 309         .sources        = exynos_clkset_vpllsrc_list,
 310         .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
 311 };
 312
 313 static struct clksrc_clk exynos5_clk_vpllsrc = {
 314         .clk    = {
 315                 .name           = "vpll_src",
 316                 .enable         = exynos5_clksrc_mask_top_ctrl,
 317                 .ctrlbit        = (1 << 0),
 318         },
 319         .sources = &exynos5_clkset_vpllsrc,
 320         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
 321 };
 322
 323 static struct clk *exynos5_clkset_sclk_vpll_list[] = {
 324         [0] = &exynos5_clk_vpllsrc.clk,
 325         [1] = &clk_fout_vpll,
 326 };
 327
 328 static struct clksrc_sources exynos5_clkset_sclk_vpll = {
 329         .sources        = exynos5_clkset_sclk_vpll_list,
 330         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
 331 };
 332
 333 static struct clksrc_clk exynos5_clk_sclk_vpll = {
 334         .clk    = {
 335                 .name           = "sclk_vpll",
 336         },
 337         .sources = &exynos5_clkset_sclk_vpll,
 338         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
 339 };
 340
 341 static struct clksrc_clk exynos5_clk_sclk_pixel = {
 342         .clk    = {
 343                 .name           = "sclk_pixel",
 344                 .parent         = &exynos5_clk_sclk_vpll.clk,
 345         },
 346         .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
 347 };
 348
 349 static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
 350         [0] = &exynos5_clk_sclk_pixel.clk,
 351         [1] = &exynos5_clk_sclk_hdmiphy,
 352 };
 353
 354 static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
 355         .sources        = exynos5_clkset_sclk_hdmi_list,
 356         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
 357 };
 358
 359 static struct clksrc_clk exynos5_clk_sclk_hdmi = {
 360         .clk    = {
 361                 .name           = "sclk_hdmi",
 362                 .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
 363                 .ctrlbit        = (1 << 20),
 364         },
 365         .sources = &exynos5_clkset_sclk_hdmi,
 366         .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
 367 };
 368
 369 static struct clksrc_clk *exynos5_sclk_tv[] = {
 370         &exynos5_clk_sclk_pixel,
 371         &exynos5_clk_sclk_hdmi,
 372 };
 373
 374 static struct clk *exynos5_clk_src_mpll_user_list[] = {
 375         [0] = &clk_fin_mpll,
 376         [1] = &exynos5_clk_mout_mpll.clk,
 377 };
 378
 379 static struct clksrc_sources exynos5_clk_src_mpll_user = {
 380         .sources        = exynos5_clk_src_mpll_user_list,
 381         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
 382 };
 383
 384 static struct clksrc_clk exynos5_clk_mout_mpll_user = {
 385         .clk    = {
 386                 .name           = "mout_mpll_user",
 387         },
 388         .sources = &exynos5_clk_src_mpll_user,
 389         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
 390 };
 391
 392 static struct clk *exynos5_clkset_mout_cpu_list[] = {
 393         [0] = &exynos5_clk_mout_apll.clk,
 394         [1] = &exynos5_clk_mout_mpll.clk,
 395 };
 396
 397 static struct clksrc_sources exynos5_clkset_mout_cpu = {
 398         .sources        = exynos5_clkset_mout_cpu_list,
 399         .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
 400 };
 401
 402 static struct clksrc_clk exynos5_clk_mout_cpu = {
 403         .clk    = {
 404                 .name           = "mout_cpu",
 405         },
 406         .sources = &exynos5_clkset_mout_cpu,
 407         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
 408 };
 409
 410 static struct clksrc_clk exynos5_clk_dout_armclk = {
 411         .clk    = {
 412                 .name           = "dout_armclk",
 413                 .parent         = &exynos5_clk_mout_cpu.clk,
 414         },
 415         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
 416 };
 417
 418 static struct clksrc_clk exynos5_clk_dout_arm2clk = {
 419         .clk    = {
 420                 .name           = "dout_arm2clk",
 421                 .parent         = &exynos5_clk_dout_armclk.clk,
 422         },
 423         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
 424 };
 425
 426 static struct clk exynos5_clk_armclk = {
 427         .name           = "armclk",
 428         .parent         = &exynos5_clk_dout_arm2clk.clk,
 429 };
 430
 431 /* Core list of CMU_CDREX side */
 432
 433 static struct clk *exynos5_clkset_cdrex_list[] = {
 434         [0] = &exynos5_clk_mout_mpll.clk,
 435         [1] = &exynos5_clk_mout_bpll.clk,
 436 };
 437
 438 static struct clksrc_sources exynos5_clkset_cdrex = {
 439         .sources        = exynos5_clkset_cdrex_list,
 440         .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
 441 };
 442
 443 static struct clksrc_clk exynos5_clk_cdrex = {
 444         .clk    = {
 445                 .name           = "clk_cdrex",
 446         },
 447         .sources = &exynos5_clkset_cdrex,
 448         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
 449         .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
 450 };
 451
 452 static struct clksrc_clk exynos5_clk_aclk_acp = {
 453         .clk    = {
 454                 .name           = "aclk_acp",
 455                 .parent         = &exynos5_clk_mout_mpll.clk,
 456         },
 457         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
 458 };
 459
 460 static struct clksrc_clk exynos5_clk_pclk_acp = {
 461         .clk    = {
 462                 .name           = "pclk_acp",
 463                 .parent         = &exynos5_clk_aclk_acp.clk,
 464         },
 465         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
 466 };
 467
 468 /* Core list of CMU_TOP side */
 469
 470 struct clk *exynos5_clkset_aclk_top_list[] = {
 471         [0] = &exynos5_clk_mout_mpll_user.clk,
 472         [1] = &exynos5_clk_mout_bpll_user.clk,
 473 };
 474
 475 struct clksrc_sources exynos5_clkset_aclk = {
 476         .sources        = exynos5_clkset_aclk_top_list,
 477         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
 478 };
 479
 480 static struct clksrc_clk exynos5_clk_aclk_400 = {
 481         .clk    = {
 482                 .name           = "aclk_400",
 483         },
 484         .sources = &exynos5_clkset_aclk,
 485         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
 486         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
 487 };
 488
 489 struct clk *exynos5_clkset_aclk_333_166_list[] = {
 490         [0] = &exynos5_clk_mout_cpll.clk,
 491         [1] = &exynos5_clk_mout_mpll_user.clk,
 492 };
 493
 494 struct clksrc_sources exynos5_clkset_aclk_333_166 = {
 495         .sources        = exynos5_clkset_aclk_333_166_list,
 496         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
 497 };
 498
 499 static struct clksrc_clk exynos5_clk_aclk_333 = {
 500         .clk    = {
 501                 .name           = "aclk_333",
 502         },
 503         .sources = &exynos5_clkset_aclk_333_166,
 504         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
 505         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
 506 };
 507
 508 static struct clksrc_clk exynos5_clk_aclk_166 = {
 509         .clk    = {
 510                 .name           = "aclk_166",
 511         },
 512         .sources = &exynos5_clkset_aclk_333_166,
 513         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
 514         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
 515 };
 516
 517 static struct clksrc_clk exynos5_clk_aclk_266 = {
 518         .clk    = {
 519                 .name           = "aclk_266",
 520                 .parent         = &exynos5_clk_mout_mpll_user.clk,
 521         },
 522         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
 523 };
 524
 525 static struct clksrc_clk exynos5_clk_aclk_200 = {
 526         .clk    = {
 527                 .name           = "aclk_200",
 528         },
 529         .sources = &exynos5_clkset_aclk,
 530         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
 531         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
 532 };
 533
 534 static struct clksrc_clk exynos5_clk_aclk_66_pre = {
 535         .clk    = {
 536                 .name           = "aclk_66_pre",
 537                 .parent         = &exynos5_clk_mout_mpll_user.clk,
 538         },
 539         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
 540 };
 541
 542 static struct clksrc_clk exynos5_clk_aclk_66 = {
 543         .clk    = {
 544                 .name           = "aclk_66",
 545                 .parent         = &exynos5_clk_aclk_66_pre.clk,
 546         },
 547         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
 548 };
 549
 550 static struct clk exynos5_init_clocks_off[] = {
 551         {
 552                 .name           = "timers",
 553                 .parent         = &exynos5_clk_aclk_66.clk,
 554                 .enable         = exynos5_clk_ip_peric_ctrl,
 555                 .ctrlbit        = (1 << 24),
 556         }, {
 557                 .name           = "rtc",
 558                 .parent         = &exynos5_clk_aclk_66.clk,
 559                 .enable         = exynos5_clk_ip_peris_ctrl,
 560                 .ctrlbit        = (1 << 20),
 561         }, {
 562                 .name           = "watchdog",
 563                 .parent         = &exynos5_clk_aclk_66.clk,
 564                 .enable         = exynos5_clk_ip_peris_ctrl,
 565                 .ctrlbit        = (1 << 19),
 566         }, {
 567                 .name           = "hsmmc",
 568                 .devname        = "exynos4-sdhci.0",
 569                 .parent         = &exynos5_clk_aclk_200.clk,
 570                 .enable         = exynos5_clk_ip_fsys_ctrl,
 571                 .ctrlbit        = (1 << 12),
 572         }, {
 573                 .name           = "hsmmc",
 574                 .devname        = "exynos4-sdhci.1",
 575                 .parent         = &exynos5_clk_aclk_200.clk,
 576                 .enable         = exynos5_clk_ip_fsys_ctrl,
 577                 .ctrlbit        = (1 << 13),
 578         }, {
 579                 .name           = "hsmmc",
 580                 .devname        = "exynos4-sdhci.2",
 581                 .parent         = &exynos5_clk_aclk_200.clk,
 582                 .enable         = exynos5_clk_ip_fsys_ctrl,
 583                 .ctrlbit        = (1 << 14),
 584         }, {
 585                 .name           = "hsmmc",
 586                 .devname        = "exynos4-sdhci.3",
 587                 .parent         = &exynos5_clk_aclk_200.clk,
 588                 .enable         = exynos5_clk_ip_fsys_ctrl,
 589                 .ctrlbit        = (1 << 15),
 590         }, {
 591                 .name           = "dwmci",
 592                 .parent         = &exynos5_clk_aclk_200.clk,
 593                 .enable         = exynos5_clk_ip_fsys_ctrl,
 594                 .ctrlbit        = (1 << 16),
 595         }, {
 596                 .name           = "sata",
 597                 .devname        = "ahci",
 598                 .enable         = exynos5_clk_ip_fsys_ctrl,
 599                 .ctrlbit        = (1 << 6),
 600         }, {
 601                 .name           = "sata_phy",
 602                 .enable         = exynos5_clk_ip_fsys_ctrl,
 603                 .ctrlbit        = (1 << 24),
 604         }, {
 605                 .name           = "sata_phy_i2c",
 606                 .enable         = exynos5_clk_ip_fsys_ctrl,
 607                 .ctrlbit        = (1 << 25),
 608         }, {
 609                 .name           = "mfc",
 610                 .devname        = "s5p-mfc",
 611                 .enable         = exynos5_clk_ip_mfc_ctrl,
 612                 .ctrlbit        = (1 << 0),
 613         }, {
 614                 .name           = "hdmi",
 615                 .devname        = "exynos4-hdmi",
 616                 .enable         = exynos5_clk_ip_disp1_ctrl,
 617                 .ctrlbit        = (1 << 6),
 618         }, {
 619                 .name           = "mixer",
 620                 .devname        = "s5p-mixer",
 621                 .enable         = exynos5_clk_ip_disp1_ctrl,
 622                 .ctrlbit        = (1 << 5),
 623         }, {
 624                 .name           = "jpeg",
 625                 .enable         = exynos5_clk_ip_gen_ctrl,
 626                 .ctrlbit        = (1 << 2),
 627         }, {
 628                 .name           = "dsim0",
 629                 .enable         = exynos5_clk_ip_disp1_ctrl,
 630                 .ctrlbit        = (1 << 3),
 631         }, {
 632                 .name           = "iis",
 633                 .devname        = "samsung-i2s.1",
 634                 .enable         = exynos5_clk_ip_peric_ctrl,
 635                 .ctrlbit        = (1 << 20),
 636         }, {
 637                 .name           = "iis",
 638                 .devname        = "samsung-i2s.2",
 639                 .enable         = exynos5_clk_ip_peric_ctrl,
 640                 .ctrlbit        = (1 << 21),
 641         }, {
 642                 .name           = "pcm",
 643                 .devname        = "samsung-pcm.1",
 644                 .enable         = exynos5_clk_ip_peric_ctrl,
 645                 .ctrlbit        = (1 << 22),
 646         }, {
 647                 .name           = "pcm",
 648                 .devname        = "samsung-pcm.2",
 649                 .enable         = exynos5_clk_ip_peric_ctrl,
 650                 .ctrlbit        = (1 << 23),
 651         }, {
 652                 .name           = "spdif",
 653                 .devname        = "samsung-spdif",
 654                 .enable         = exynos5_clk_ip_peric_ctrl,
 655                 .ctrlbit        = (1 << 26),
 656         }, {
 657                 .name           = "ac97",
 658                 .devname        = "samsung-ac97",
 659                 .enable         = exynos5_clk_ip_peric_ctrl,
 660                 .ctrlbit        = (1 << 27),
 661         }, {
 662                 .name           = "usbhost",
 663                 .enable         = exynos5_clk_ip_fsys_ctrl ,
 664                 .ctrlbit        = (1 << 18),
 665         }, {
 666                 .name           = "usbotg",
 667                 .enable         = exynos5_clk_ip_fsys_ctrl,
 668                 .ctrlbit        = (1 << 7),
 669         }, {
 670                 .name           = "gps",
 671                 .enable         = exynos5_clk_ip_gps_ctrl,
 672                 .ctrlbit        = ((1 << 3) | (1 << 2) | (1 << 0)),
 673         }, {
 674                 .name           = "nfcon",
 675                 .enable         = exynos5_clk_ip_fsys_ctrl,
 676                 .ctrlbit        = (1 << 22),
 677         }, {
 678                 .name           = "iop",
 679                 .enable         = exynos5_clk_ip_fsys_ctrl,
 680                 .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
 681         }, {
 682                 .name           = "core_iop",
 683                 .enable         = exynos5_clk_ip_core_ctrl,
 684                 .ctrlbit        = ((1 << 21) | (1 << 3)),
 685         }, {
 686                 .name           = "mcu_iop",
 687                 .enable         = exynos5_clk_ip_fsys_ctrl,
 688                 .ctrlbit        = (1 << 0),
 689         }, {
 690                 .name           = "i2c",
 691                 .devname        = "s3c2440-i2c.0",
 692                 .parent         = &exynos5_clk_aclk_66.clk,
 693                 .enable         = exynos5_clk_ip_peric_ctrl,
 694                 .ctrlbit        = (1 << 6),
 695         }, {
 696                 .name           = "i2c",
 697                 .devname        = "s3c2440-i2c.1",
 698                 .parent         = &exynos5_clk_aclk_66.clk,
 699                 .enable         = exynos5_clk_ip_peric_ctrl,
 700                 .ctrlbit        = (1 << 7),
 701         }, {
 702                 .name           = "i2c",
 703                 .devname        = "s3c2440-i2c.2",
 704                 .parent         = &exynos5_clk_aclk_66.clk,
 705                 .enable         = exynos5_clk_ip_peric_ctrl,
 706                 .ctrlbit        = (1 << 8),
 707         }, {
 708                 .name           = "i2c",
 709                 .devname        = "s3c2440-i2c.3",
 710                 .parent         = &exynos5_clk_aclk_66.clk,
 711                 .enable         = exynos5_clk_ip_peric_ctrl,
 712                 .ctrlbit        = (1 << 9),
 713         }, {
 714                 .name           = "i2c",
 715                 .devname        = "s3c2440-i2c.4",
 716                 .parent         = &exynos5_clk_aclk_66.clk,
 717                 .enable         = exynos5_clk_ip_peric_ctrl,
 718                 .ctrlbit        = (1 << 10),
 719         }, {
 720                 .name           = "i2c",
 721                 .devname        = "s3c2440-i2c.5",
 722                 .parent         = &exynos5_clk_aclk_66.clk,
 723                 .enable         = exynos5_clk_ip_peric_ctrl,
 724                 .ctrlbit        = (1 << 11),
 725         }, {
 726                 .name           = "i2c",
 727                 .devname        = "s3c2440-i2c.6",
 728                 .parent         = &exynos5_clk_aclk_66.clk,
 729                 .enable         = exynos5_clk_ip_peric_ctrl,
 730                 .ctrlbit        = (1 << 12),
 731         }, {
 732                 .name           = "i2c",
 733                 .devname        = "s3c2440-i2c.7",
 734                 .parent         = &exynos5_clk_aclk_66.clk,
 735                 .enable         = exynos5_clk_ip_peric_ctrl,
 736                 .ctrlbit        = (1 << 13),
 737         }, {
 738                 .name           = "i2c",
 739                 .devname        = "s3c2440-hdmiphy-i2c",
 740                 .parent         = &exynos5_clk_aclk_66.clk,
 741                 .enable         = exynos5_clk_ip_peric_ctrl,
 742                 .ctrlbit        = (1 << 14),
 743         }, {
 744                 .name           = SYSMMU_CLOCK_NAME,
 745                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
 746                 .enable         = &exynos5_clk_ip_mfc_ctrl,
 747                 .ctrlbit        = (1 << 1),
 748         }, {
 749                 .name           = SYSMMU_CLOCK_NAME,
 750                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
 751                 .enable         = &exynos5_clk_ip_mfc_ctrl,
 752                 .ctrlbit        = (1 << 2),
 753         }, {
 754                 .name           = SYSMMU_CLOCK_NAME,
 755                 .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
 756                 .enable         = &exynos5_clk_ip_disp1_ctrl,
 757                 .ctrlbit        = (1 << 9)
 758         }, {
 759                 .name           = SYSMMU_CLOCK_NAME,
 760                 .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
 761                 .enable         = &exynos5_clk_ip_gen_ctrl,
 762                 .ctrlbit        = (1 << 7),
 763         }, {
 764                 .name           = SYSMMU_CLOCK_NAME,
 765                 .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
 766                 .enable         = &exynos5_clk_ip_gen_ctrl,
 767                 .ctrlbit        = (1 << 6)
 768         }, {
 769                 .name           = SYSMMU_CLOCK_NAME,
 770                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
 771                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 772                 .ctrlbit        = (1 << 7),
 773         }, {
 774                 .name           = SYSMMU_CLOCK_NAME,
 775                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
 776                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 777                 .ctrlbit        = (1 << 8),
 778         }, {
 779                 .name           = SYSMMU_CLOCK_NAME,
 780                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
 781                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 782                 .ctrlbit        = (1 << 9),
 783         }, {
 784                 .name           = SYSMMU_CLOCK_NAME,
 785                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
 786                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 787                 .ctrlbit        = (1 << 10),
 788         }, {
 789                 .name           = SYSMMU_CLOCK_NAME,
 790                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 791                 .enable         = &exynos5_clk_ip_isp0_ctrl,
 792                 .ctrlbit        = (0x3F << 8),
 793         }, {
 794                 .name           = SYSMMU_CLOCK_NAME2,
 795                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 796                 .enable         = &exynos5_clk_ip_isp1_ctrl,
 797                 .ctrlbit        = (0xF << 4),
 798         }, {
 799                 .name           = SYSMMU_CLOCK_NAME,
 800                 .devname        = SYSMMU_CLOCK_DEVNAME(camif0, 12),
 801                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 802                 .ctrlbit        = (1 << 11),
 803         }, {
 804                 .name           = SYSMMU_CLOCK_NAME,
 805                 .devname        = SYSMMU_CLOCK_DEVNAME(camif1, 13),
 806                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 807                 .ctrlbit        = (1 << 12),
 808         }, {
 809                 .name           = SYSMMU_CLOCK_NAME,
 810                 .devname        = SYSMMU_CLOCK_DEVNAME(2d, 14),
 811                 .enable         = &exynos5_clk_ip_acp_ctrl,
 812                 .ctrlbit        = (1 << 7)
 813         }
 814 };
 815
 816 static struct clk exynos5_init_clocks_on[] = {
 817         {
 818                 .name           = "uart",
 819                 .devname        = "s5pv210-uart.0",
 820                 .enable         = exynos5_clk_ip_peric_ctrl,
 821                 .ctrlbit        = (1 << 0),
 822         }, {
 823                 .name           = "uart",
 824                 .devname        = "s5pv210-uart.1",
 825                 .enable         = exynos5_clk_ip_peric_ctrl,
 826                 .ctrlbit        = (1 << 1),
 827         }, {
 828                 .name           = "uart",
 829                 .devname        = "s5pv210-uart.2",
 830                 .enable         = exynos5_clk_ip_peric_ctrl,
 831                 .ctrlbit        = (1 << 2),
 832         }, {
 833                 .name           = "uart",
 834                 .devname        = "s5pv210-uart.3",
 835                 .enable         = exynos5_clk_ip_peric_ctrl,
 836                 .ctrlbit        = (1 << 3),
 837         }, {
 838                 .name           = "uart",
 839                 .devname        = "s5pv210-uart.4",
 840                 .enable         = exynos5_clk_ip_peric_ctrl,
 841                 .ctrlbit        = (1 << 4),
 842         }, {
 843                 .name           = "uart",
 844                 .devname        = "s5pv210-uart.5",
 845                 .enable         = exynos5_clk_ip_peric_ctrl,
 846                 .ctrlbit        = (1 << 5),
 847         }
 848 };
 849
 850 static struct clk exynos5_clk_pdma0 = {
 851         .name           = "dma",
 852         .devname        = "dma-pl330.0",
 853         .enable         = exynos5_clk_ip_fsys_ctrl,
 854         .ctrlbit        = (1 << 1),
 855 };
 856
 857 static struct clk exynos5_clk_pdma1 = {
 858         .name           = "dma",
 859         .devname        = "dma-pl330.1",
 860         .enable         = exynos5_clk_ip_fsys_ctrl,
 861         .ctrlbit        = (1 << 2),
 862 };
 863
 864 static struct clk exynos5_clk_mdma1 = {
 865         .name           = "dma",
 866         .devname        = "dma-pl330.2",
 867         .enable         = exynos5_clk_ip_gen_ctrl,
 868         .ctrlbit        = (1 << 4),
 869 };
 870
 871 struct clk *exynos5_clkset_group_list[] = {
 872         [0] = &clk_ext_xtal_mux,
 873         [1] = NULL,
 874         [2] = &exynos5_clk_sclk_hdmi24m,
 875         [3] = &exynos5_clk_sclk_dptxphy,
 876         [4] = &exynos5_clk_sclk_usbphy,
 877         [5] = &exynos5_clk_sclk_hdmiphy,
 878         [6] = &exynos5_clk_mout_mpll_user.clk,
 879         [7] = &exynos5_clk_mout_epll.clk,
 880         [8] = &exynos5_clk_sclk_vpll.clk,
 881         [9] = &exynos5_clk_mout_cpll.clk,
 882 };
 883
 884 struct clksrc_sources exynos5_clkset_group = {
 885         .sources        = exynos5_clkset_group_list,
 886         .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
 887 };
 888
 889 /* Possible clock sources for aclk_266_gscl_sub Mux */
 890 static struct clk *clk_src_gscl_266_list[] = {
 891         [0] = &clk_ext_xtal_mux,
 892         [1] = &exynos5_clk_aclk_266.clk,
 893 };
 894
 895 static struct clksrc_sources clk_src_gscl_266 = {
 896         .sources        = clk_src_gscl_266_list,
 897         .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
 898 };
 899
 900 static struct clksrc_clk exynos5_clk_dout_mmc0 = {
 901         .clk            = {
 902                 .name           = "dout_mmc0",
 903         },
 904         .sources = &exynos5_clkset_group,
 905         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
 906         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 907 };
 908
 909 static struct clksrc_clk exynos5_clk_dout_mmc1 = {
 910         .clk            = {
 911                 .name           = "dout_mmc1",
 912         },
 913         .sources = &exynos5_clkset_group,
 914         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
 915         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 916 };
 917
 918 static struct clksrc_clk exynos5_clk_dout_mmc2 = {
 919         .clk            = {
 920                 .name           = "dout_mmc2",
 921         },
 922         .sources = &exynos5_clkset_group,
 923         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
 924         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
 925 };
 926
 927 static struct clksrc_clk exynos5_clk_dout_mmc3 = {
 928         .clk            = {
 929                 .name           = "dout_mmc3",
 930         },
 931         .sources = &exynos5_clkset_group,
 932         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
 933         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
 934 };
 935
 936 static struct clksrc_clk exynos5_clk_dout_mmc4 = {
 937         .clk            = {
 938                 .name           = "dout_mmc4",
 939         },
 940         .sources = &exynos5_clkset_group,
 941         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
 942         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
 943 };
 944
 945 static struct clksrc_clk exynos5_clk_sclk_uart0 = {
 946         .clk    = {
 947                 .name           = "uclk1",
 948                 .devname        = "exynos4210-uart.0",
 949                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 950                 .ctrlbit        = (1 << 0),
 951         },
 952         .sources = &exynos5_clkset_group,
 953         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
 954         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
 955 };
 956
 957 static struct clksrc_clk exynos5_clk_sclk_uart1 = {
 958         .clk    = {
 959                 .name           = "uclk1",
 960                 .devname        = "exynos4210-uart.1",
 961                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 962                 .ctrlbit        = (1 << 4),
 963         },
 964         .sources = &exynos5_clkset_group,
 965         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
 966         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
 967 };
 968
 969 static struct clksrc_clk exynos5_clk_sclk_uart2 = {
 970         .clk    = {
 971                 .name           = "uclk1",
 972                 .devname        = "exynos4210-uart.2",
 973                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 974                 .ctrlbit        = (1 << 8),
 975         },
 976         .sources = &exynos5_clkset_group,
 977         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
 978         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
 979 };
 980
 981 static struct clksrc_clk exynos5_clk_sclk_uart3 = {
 982         .clk    = {
 983                 .name           = "uclk1",
 984                 .devname        = "exynos4210-uart.3",
 985                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 986                 .ctrlbit        = (1 << 12),
 987         },
 988         .sources = &exynos5_clkset_group,
 989         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
 990         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
 991 };
 992
 993 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 994         .clk    = {
 995                 .name           = "sclk_mmc",
 996                 .devname        = "exynos4-sdhci.0",
 997                 .parent         = &exynos5_clk_dout_mmc0.clk,
 998                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
 999                 .ctrlbit        = (1 << 0),
1000         },
1001         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1002 };
1003
1004 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
1005         .clk    = {
1006                 .name           = "sclk_mmc",
1007                 .devname        = "exynos4-sdhci.1",
1008                 .parent         = &exynos5_clk_dout_mmc1.clk,
1009                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1010                 .ctrlbit        = (1 << 4),
1011         },
1012         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1013 };
1014
1015 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
1016         .clk    = {
1017                 .name           = "sclk_mmc",
1018                 .devname        = "exynos4-sdhci.2",
1019                 .parent         = &exynos5_clk_dout_mmc2.clk,
1020                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1021                 .ctrlbit        = (1 << 8),
1022         },
1023         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1024 };
1025
1026 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1027         .clk    = {
1028                 .name           = "sclk_mmc",
1029                 .devname        = "exynos4-sdhci.3",
1030                 .parent         = &exynos5_clk_dout_mmc3.clk,
1031                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1032                 .ctrlbit        = (1 << 12),
1033         },
1034         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1035 };
1036
1037 static struct clksrc_clk exynos5_clksrcs[] = {
1038         {
1039                 .clk    = {
1040                         .name           = "sclk_dwmci",
1041                         .parent         = &exynos5_clk_dout_mmc4.clk,
1042                         .enable         = exynos5_clksrc_mask_fsys_ctrl,
1043                         .ctrlbit        = (1 << 16),
1044                 },
1045                 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1046         }, {
1047                 .clk    = {
1048                         .name           = "sclk_fimd",
1049                         .devname        = "s3cfb.1",
1050                         .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
1051                         .ctrlbit        = (1 << 0),
1052                 },
1053                 .sources = &exynos5_clkset_group,
1054                 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1055                 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1056         }, {
1057                 .clk    = {
1058                         .name           = "aclk_266_gscl",
1059                 },
1060                 .sources = &clk_src_gscl_266,
1061                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1062         }, {
1063                 .clk    = {
1064                         .name           = "sclk_g3d",
1065                         .devname        = "mali-t604.0",
1066                         .enable         = exynos5_clk_block_ctrl,
1067                         .ctrlbit        = (1 << 1),
1068                 },
1069                 .sources = &exynos5_clkset_aclk,
1070                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1071                 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1072         }, {
1073                 .clk    = {
1074                         .name           = "sclk_gscl_wrap",
1075                         .devname        = "s5p-mipi-csis.0",
1076                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1077                         .ctrlbit        = (1 << 24),
1078                 },
1079                 .sources = &exynos5_clkset_group,
1080                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1081                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1082         }, {
1083                 .clk    = {
1084                         .name           = "sclk_gscl_wrap",
1085                         .devname        = "s5p-mipi-csis.1",
1086                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1087                         .ctrlbit        = (1 << 28),
1088                 },
1089                 .sources = &exynos5_clkset_group,
1090                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1091                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1092         }, {
1093                 .clk    = {
1094                         .name           = "sclk_cam0",
1095                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1096                         .ctrlbit        = (1 << 16),
1097                 },
1098                 .sources = &exynos5_clkset_group,
1099                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1100                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1101         }, {
1102                 .clk    = {
1103                         .name           = "sclk_cam1",
1104                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1105                         .ctrlbit        = (1 << 20),
1106                 },
1107                 .sources = &exynos5_clkset_group,
1108                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1109                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1110         }, {
1111                 .clk    = {
1112                         .name           = "sclk_jpeg",
1113                         .parent         = &exynos5_clk_mout_cpll.clk,
1114                 },
1115                 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1116         },
1117 };
1118
1119 /* Clock initialization code */
1120 static struct clksrc_clk *exynos5_sysclks[] = {
1121         &exynos5_clk_mout_apll,
1122         &exynos5_clk_sclk_apll,
1123         &exynos5_clk_mout_bpll,
1124         &exynos5_clk_mout_bpll_fout,
1125         &exynos5_clk_mout_bpll_user,
1126         &exynos5_clk_mout_cpll,
1127         &exynos5_clk_mout_epll,
1128         &exynos5_clk_mout_mpll,
1129         &exynos5_clk_mout_mpll_fout,
1130         &exynos5_clk_mout_mpll_user,
1131         &exynos5_clk_vpllsrc,
1132         &exynos5_clk_sclk_vpll,
1133         &exynos5_clk_mout_cpu,
1134         &exynos5_clk_dout_armclk,
1135         &exynos5_clk_dout_arm2clk,
1136         &exynos5_clk_cdrex,
1137         &exynos5_clk_aclk_400,
1138         &exynos5_clk_aclk_333,
1139         &exynos5_clk_aclk_266,
1140         &exynos5_clk_aclk_200,
1141         &exynos5_clk_aclk_166,
1142         &exynos5_clk_aclk_66_pre,
1143         &exynos5_clk_aclk_66,
1144         &exynos5_clk_dout_mmc0,
1145         &exynos5_clk_dout_mmc1,
1146         &exynos5_clk_dout_mmc2,
1147         &exynos5_clk_dout_mmc3,
1148         &exynos5_clk_dout_mmc4,
1149         &exynos5_clk_aclk_acp,
1150         &exynos5_clk_pclk_acp,
1151 };
1152
1153 static struct clk *exynos5_clk_cdev[] = {
1154         &exynos5_clk_pdma0,
1155         &exynos5_clk_pdma1,
1156         &exynos5_clk_mdma1,
1157 };
1158
1159 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1160         &exynos5_clk_sclk_uart0,
1161         &exynos5_clk_sclk_uart1,
1162         &exynos5_clk_sclk_uart2,
1163         &exynos5_clk_sclk_uart3,
1164         &exynos5_clk_sclk_mmc0,
1165         &exynos5_clk_sclk_mmc1,
1166         &exynos5_clk_sclk_mmc2,
1167         &exynos5_clk_sclk_mmc3,
1168 };
1169
1170 static struct clk_lookup exynos5_clk_lookup[] = {
1171         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1172         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1173         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1174         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1175         CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1176         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1177         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1178         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1179         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1180         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1181         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1182 };
1183
1184 static unsigned long exynos5_epll_get_rate(struct clk *clk)
1185 {
1186         return clk->rate;
1187 }
1188
1189 static struct clk *exynos5_clks[] __initdata = {
1190         &exynos5_clk_sclk_hdmi27m,
1191         &exynos5_clk_sclk_hdmiphy,
1192         &clk_fout_bpll,
1193         &clk_fout_bpll_div2,
1194         &clk_fout_cpll,
1195         &clk_fout_mpll_div2,
1196         &exynos5_clk_armclk,
1197 };
1198
1199 static u32 epll_div[][6] = {
1200         { 192000000, 0, 48, 3, 1, 0 },
1201         { 180000000, 0, 45, 3, 1, 0 },
1202         {  73728000, 1, 73, 3, 3, 47710 },
1203         {  67737600, 1, 90, 4, 3, 20762 },
1204         {  49152000, 0, 49, 3, 3, 9961 },
1205         {  45158400, 0, 45, 3, 3, 10381 },
1206         { 180633600, 0, 45, 3, 1, 10381 },
1207 };
1208
1209 static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1210 {
1211         unsigned int epll_con, epll_con_k;
1212         unsigned int i;
1213         unsigned int tmp;
1214         unsigned int epll_rate;
1215         unsigned int locktime;
1216         unsigned int lockcnt;
1217
1218         /* Return if nothing changed */
1219         if (clk->rate == rate)
1220                 return 0;
1221
1222         if (clk->parent)
1223                 epll_rate = clk_get_rate(clk->parent);
1224         else
1225                 epll_rate = clk_ext_xtal_mux.rate;
1226
1227         if (epll_rate != 24000000) {
1228                 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1229                 return -EINVAL;
1230         }
1231
1232         epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1233         epll_con &= ~(0x1 << 27 | \
1234                         PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
1235                         PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1236                         PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1237
1238         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1239                 if (epll_div[i][0] == rate) {
1240                         epll_con_k = epll_div[i][5] << 0;
1241                         epll_con |= epll_div[i][1] << 27;
1242                         epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1243                         epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1244                         epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1245                         break;
1246                 }
1247         }
1248
1249         if (i == ARRAY_SIZE(epll_div)) {
1250                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1251                                 __func__);
1252                 return -EINVAL;
1253         }
1254
1255         epll_rate /= 1000000;
1256
1257         /* 3000 max_cycls : specification data */
1258         locktime = 3000 / epll_rate * epll_div[i][3];
1259         lockcnt = locktime * 10000 / (10000 / epll_rate);
1260
1261         __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1262
1263         __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1264         __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1265
1266         do {
1267                 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1268         } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1269
1270         clk->rate = rate;
1271
1272         return 0;
1273 }
1274
1275 static struct clk_ops exynos5_epll_ops = {
1276         .get_rate = exynos5_epll_get_rate,
1277         .set_rate = exynos5_epll_set_rate,
1278 };
1279
1280 static int xtal_rate;
1281
1282 static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1283 {
1284         return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1285 }
1286
1287 static struct clk_ops exynos5_fout_apll_ops = {
1288         .get_rate = exynos5_fout_apll_get_rate,
1289 };
1290
1291 #ifdef CONFIG_PM
1292 static int exynos5_clock_suspend(void)
1293 {
1294         s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1295
1296         return 0;
1297 }
1298
1299 static void exynos5_clock_resume(void)
1300 {
1301         s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1302 }
1303 #else
1304 #define exynos5_clock_suspend NULL
1305 #define exynos5_clock_resume NULL
1306 #endif
1307
1308 struct syscore_ops exynos5_clock_syscore_ops = {
1309         .suspend        = exynos5_clock_suspend,
1310         .resume         = exynos5_clock_resume,
1311 };
1312
1313 void __init_or_cpufreq exynos5_setup_clocks(void)
1314 {
1315         struct clk *xtal_clk;
1316         unsigned long apll;
1317         unsigned long bpll;
1318         unsigned long cpll;
1319         unsigned long mpll;
1320         unsigned long epll;
1321         unsigned long vpll;
1322         unsigned long vpllsrc;
1323         unsigned long xtal;
1324         unsigned long armclk;
1325         unsigned long mout_cdrex;
1326         unsigned long aclk_400;
1327         unsigned long aclk_333;
1328         unsigned long aclk_266;
1329         unsigned long aclk_200;
1330         unsigned long aclk_166;
1331         unsigned long aclk_66;
1332         unsigned int ptr;
1333
1334         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1335
1336         xtal_clk = clk_get(NULL, "xtal");
1337         BUG_ON(IS_ERR(xtal_clk));
1338
1339         xtal = clk_get_rate(xtal_clk);
1340
1341         xtal_rate = xtal;
1342
1343         clk_put(xtal_clk);
1344
1345         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1346
1347         apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1348         bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1349         cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1350         mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1351         epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1352                         __raw_readl(EXYNOS5_EPLL_CON1));
1353
1354         vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1355         vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1356                         __raw_readl(EXYNOS5_VPLL_CON1));
1357
1358         clk_fout_apll.ops = &exynos5_fout_apll_ops;
1359         clk_fout_bpll.rate = bpll;
1360         clk_fout_bpll_div2.rate = bpll >> 1;
1361         clk_fout_cpll.rate = cpll;
1362         clk_fout_mpll.rate = mpll;
1363         clk_fout_mpll_div2.rate = mpll >> 1;
1364         clk_fout_epll.rate = epll;
1365         clk_fout_vpll.rate = vpll;
1366
1367         printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1368                         "M=%ld, E=%ld V=%ld",
1369                         apll, bpll, cpll, mpll, epll, vpll);
1370
1371         armclk = clk_get_rate(&exynos5_clk_armclk);
1372         mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1373
1374         aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1375         aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1376         aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1377         aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1378         aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1379         aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1380
1381         printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1382                         "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1383                         "ACLK166=%ld, ACLK66=%ld\n",
1384                         armclk, mout_cdrex, aclk_400,
1385                         aclk_333, aclk_266, aclk_200,
1386                         aclk_166, aclk_66);
1387
1388
1389         clk_fout_epll.ops = &exynos5_epll_ops;
1390
1391         if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1392                 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1393                                 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1394
1395         clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1396         clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1397
1398         clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1399         clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1400
1401         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1402                 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1403 }
1404
1405 void __init exynos5_register_clocks(void)
1406 {
1407         int ptr;
1408
1409         s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1410
1411         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1412                 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1413
1414         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1415                 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1416
1417         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1418                 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1419
1420         s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1421         s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1422
1423         s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1424         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1425                 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1426
1427         s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1428         s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1429         clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1430
1431         register_syscore_ops(&exynos5_clock_syscore_ops);
1432         s3c_pwmclk_init();
1433 }