2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Clock support for EXYNOS5 SoCs
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/err.h>
15 #include <linux/syscore_ops.h>
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
26 #include <mach/regs-clock.h>
27 #include <mach/sysmmu.h>
31 #ifdef CONFIG_PM_SLEEP
32 static struct sleep_save exynos5_clock_save[] = {
33 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
34 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
35 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
36 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
37 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
38 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
39 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
40 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
41 SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
42 SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
43 SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
44 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
45 SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
46 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
47 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
48 SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
49 SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
50 SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
51 SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
52 SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
53 SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
54 SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
55 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
56 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
57 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
58 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
59 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
60 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
61 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
62 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
63 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
64 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
65 SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
66 SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
67 SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
68 SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
69 SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
70 SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
71 SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
72 SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
73 SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
74 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
75 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
76 SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
77 SAVE_ITEM(EXYNOS5_EPLL_CON0),
78 SAVE_ITEM(EXYNOS5_EPLL_CON1),
79 SAVE_ITEM(EXYNOS5_EPLL_CON2),
80 SAVE_ITEM(EXYNOS5_VPLL_CON0),
81 SAVE_ITEM(EXYNOS5_VPLL_CON1),
82 SAVE_ITEM(EXYNOS5_VPLL_CON2),
86 static struct clk exynos5_clk_sclk_dptxphy = {
90 static struct clk exynos5_clk_sclk_hdmi24m = {
91 .name = "sclk_hdmi24m",
95 static struct clk exynos5_clk_sclk_hdmi27m = {
96 .name = "sclk_hdmi27m",
100 static struct clk exynos5_clk_sclk_hdmiphy = {
101 .name = "sclk_hdmiphy",
104 static struct clk exynos5_clk_sclk_usbphy = {
105 .name = "sclk_usbphy",
109 static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
111 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
114 static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
116 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
119 static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
121 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
124 static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
126 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
129 static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
131 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
134 static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
136 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
139 static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
141 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
144 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
146 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
149 static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
151 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
154 static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
156 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
159 static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
161 return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
164 static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
166 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
169 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
171 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
174 static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
176 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
179 static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
181 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
184 static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
186 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
189 static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
191 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
194 static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
196 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
199 static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
201 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
204 /* Core list of CMU_CPU side */
206 static struct clksrc_clk exynos5_clk_mout_apll = {
210 .sources = &clk_src_apll,
211 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
214 static struct clksrc_clk exynos5_clk_sclk_apll = {
217 .parent = &exynos5_clk_mout_apll.clk,
219 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
222 static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
224 .name = "mout_bpll_fout",
226 .sources = &clk_src_bpll_fout,
227 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
230 static struct clk *exynos5_clk_src_bpll_list[] = {
232 [1] = &exynos5_clk_mout_bpll_fout.clk,
235 static struct clksrc_sources exynos5_clk_src_bpll = {
236 .sources = exynos5_clk_src_bpll_list,
237 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
240 static struct clksrc_clk exynos5_clk_mout_bpll = {
244 .sources = &exynos5_clk_src_bpll,
245 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
248 static struct clk *exynos5_clk_src_bpll_user_list[] = {
250 [1] = &exynos5_clk_mout_bpll.clk,
253 static struct clksrc_sources exynos5_clk_src_bpll_user = {
254 .sources = exynos5_clk_src_bpll_user_list,
255 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
258 static struct clksrc_clk exynos5_clk_mout_bpll_user = {
260 .name = "mout_bpll_user",
262 .sources = &exynos5_clk_src_bpll_user,
263 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
266 static struct clksrc_clk exynos5_clk_mout_cpll = {
270 .sources = &clk_src_cpll,
271 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
274 static struct clksrc_clk exynos5_clk_mout_epll = {
278 .sources = &clk_src_epll,
279 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
282 static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
284 .name = "mout_mpll_fout",
286 .sources = &clk_src_mpll_fout,
287 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
290 static struct clk *exynos5_clk_src_mpll_list[] = {
292 [1] = &exynos5_clk_mout_mpll_fout.clk,
295 static struct clksrc_sources exynos5_clk_src_mpll = {
296 .sources = exynos5_clk_src_mpll_list,
297 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
300 static struct clksrc_clk exynos5_clk_mout_mpll = {
304 .sources = &exynos5_clk_src_mpll,
305 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
308 static struct clk *exynos_clkset_vpllsrc_list[] = {
310 [1] = &exynos5_clk_sclk_hdmi27m,
313 static struct clksrc_sources exynos5_clkset_vpllsrc = {
314 .sources = exynos_clkset_vpllsrc_list,
315 .nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
318 static struct clksrc_clk exynos5_clk_vpllsrc = {
321 .enable = exynos5_clksrc_mask_top_ctrl,
324 .sources = &exynos5_clkset_vpllsrc,
325 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
328 static struct clk *exynos5_clkset_sclk_vpll_list[] = {
329 [0] = &exynos5_clk_vpllsrc.clk,
330 [1] = &clk_fout_vpll,
333 static struct clksrc_sources exynos5_clkset_sclk_vpll = {
334 .sources = exynos5_clkset_sclk_vpll_list,
335 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
338 static struct clksrc_clk exynos5_clk_sclk_vpll = {
342 .sources = &exynos5_clkset_sclk_vpll,
343 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
346 static struct clksrc_clk exynos5_clk_sclk_pixel = {
348 .name = "sclk_pixel",
349 .parent = &exynos5_clk_sclk_vpll.clk,
351 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
354 static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
355 [0] = &exynos5_clk_sclk_pixel.clk,
356 [1] = &exynos5_clk_sclk_hdmiphy,
359 static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
360 .sources = exynos5_clkset_sclk_hdmi_list,
361 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
364 static struct clksrc_clk exynos5_clk_sclk_hdmi = {
367 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
368 .ctrlbit = (1 << 20),
370 .sources = &exynos5_clkset_sclk_hdmi,
371 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
374 static struct clksrc_clk *exynos5_sclk_tv[] = {
375 &exynos5_clk_sclk_pixel,
376 &exynos5_clk_sclk_hdmi,
379 static struct clk *exynos5_clk_src_mpll_user_list[] = {
381 [1] = &exynos5_clk_mout_mpll.clk,
384 static struct clksrc_sources exynos5_clk_src_mpll_user = {
385 .sources = exynos5_clk_src_mpll_user_list,
386 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
389 static struct clksrc_clk exynos5_clk_mout_mpll_user = {
391 .name = "mout_mpll_user",
393 .sources = &exynos5_clk_src_mpll_user,
394 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
397 static struct clk *exynos5_clkset_mout_cpu_list[] = {
398 [0] = &exynos5_clk_mout_apll.clk,
399 [1] = &exynos5_clk_mout_mpll.clk,
402 static struct clksrc_sources exynos5_clkset_mout_cpu = {
403 .sources = exynos5_clkset_mout_cpu_list,
404 .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
407 static struct clksrc_clk exynos5_clk_mout_cpu = {
411 .sources = &exynos5_clkset_mout_cpu,
412 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
415 static struct clksrc_clk exynos5_clk_dout_armclk = {
417 .name = "dout_armclk",
418 .parent = &exynos5_clk_mout_cpu.clk,
420 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
423 static struct clksrc_clk exynos5_clk_dout_arm2clk = {
425 .name = "dout_arm2clk",
426 .parent = &exynos5_clk_dout_armclk.clk,
428 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
431 static struct clk exynos5_clk_armclk = {
433 .parent = &exynos5_clk_dout_arm2clk.clk,
436 /* Core list of CMU_CDREX side */
438 static struct clk *exynos5_clkset_cdrex_list[] = {
439 [0] = &exynos5_clk_mout_mpll.clk,
440 [1] = &exynos5_clk_mout_bpll.clk,
443 static struct clksrc_sources exynos5_clkset_cdrex = {
444 .sources = exynos5_clkset_cdrex_list,
445 .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list),
448 static struct clksrc_clk exynos5_clk_cdrex = {
452 .sources = &exynos5_clkset_cdrex,
453 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
454 .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
457 static struct clksrc_clk exynos5_clk_aclk_acp = {
460 .parent = &exynos5_clk_mout_mpll.clk,
462 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
465 static struct clksrc_clk exynos5_clk_pclk_acp = {
468 .parent = &exynos5_clk_aclk_acp.clk,
470 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
473 /* Core list of CMU_TOP side */
475 static struct clk *exynos5_clkset_aclk_top_list[] = {
476 [0] = &exynos5_clk_mout_mpll_user.clk,
477 [1] = &exynos5_clk_mout_bpll_user.clk,
480 static struct clksrc_sources exynos5_clkset_aclk = {
481 .sources = exynos5_clkset_aclk_top_list,
482 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
485 static struct clksrc_clk exynos5_clk_aclk_400 = {
489 .sources = &exynos5_clkset_aclk,
490 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
491 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
494 static struct clk *exynos5_clkset_aclk_333_166_list[] = {
495 [0] = &exynos5_clk_mout_cpll.clk,
496 [1] = &exynos5_clk_mout_mpll_user.clk,
499 static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
500 .sources = exynos5_clkset_aclk_333_166_list,
501 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
504 static struct clksrc_clk exynos5_clk_aclk_333 = {
508 .sources = &exynos5_clkset_aclk_333_166,
509 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
510 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
513 static struct clksrc_clk exynos5_clk_aclk_166 = {
517 .sources = &exynos5_clkset_aclk_333_166,
518 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
519 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
522 static struct clksrc_clk exynos5_clk_aclk_266 = {
525 .parent = &exynos5_clk_mout_mpll_user.clk,
527 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
530 static struct clksrc_clk exynos5_clk_aclk_200 = {
534 .sources = &exynos5_clkset_aclk,
535 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
536 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
539 static struct clksrc_clk exynos5_clk_aclk_66_pre = {
541 .name = "aclk_66_pre",
542 .parent = &exynos5_clk_mout_mpll_user.clk,
544 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
547 static struct clksrc_clk exynos5_clk_aclk_66 = {
550 .parent = &exynos5_clk_aclk_66_pre.clk,
552 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
555 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
557 .name = "mout_aclk_300_gscl_mid",
559 .sources = &exynos5_clkset_aclk,
560 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
563 static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
564 [0] = &exynos5_clk_sclk_vpll.clk,
565 [1] = &exynos5_clk_mout_cpll.clk,
568 static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
569 .sources = exynos5_clkset_aclk_300_mid1_list,
570 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
573 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
575 .name = "mout_aclk_300_gscl_mid1",
577 .sources = &exynos5_clkset_aclk_300_gscl_mid1,
578 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
581 static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
582 [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
583 [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
586 static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
587 .sources = exynos5_clkset_aclk_300_gscl_list,
588 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
591 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
593 .name = "mout_aclk_300_gscl",
595 .sources = &exynos5_clkset_aclk_300_gscl,
596 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
599 static struct clk *exynos5_clk_src_gscl_300_list[] = {
600 [0] = &clk_ext_xtal_mux,
601 [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
604 static struct clksrc_sources exynos5_clk_src_gscl_300 = {
605 .sources = exynos5_clk_src_gscl_300_list,
606 .nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
609 static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
611 .name = "aclk_300_gscl",
613 .sources = &exynos5_clk_src_gscl_300,
614 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
617 static struct clk exynos5_init_clocks_off[] = {
620 .parent = &exynos5_clk_aclk_66.clk,
621 .enable = exynos5_clk_ip_peric_ctrl,
622 .ctrlbit = (1 << 24),
625 .parent = &exynos5_clk_aclk_66.clk,
626 .enable = exynos5_clk_ip_peris_ctrl,
627 .ctrlbit = (1 << 21),
630 .parent = &exynos5_clk_aclk_66.clk,
631 .enable = exynos5_clk_ip_peris_ctrl,
632 .ctrlbit = (1 << 20),
635 .parent = &exynos5_clk_aclk_66.clk,
636 .enable = exynos5_clk_ip_peris_ctrl,
637 .ctrlbit = (1 << 19),
639 .name = "biu", /* bus interface unit clock */
640 .devname = "dw_mmc.0",
641 .parent = &exynos5_clk_aclk_200.clk,
642 .enable = exynos5_clk_ip_fsys_ctrl,
643 .ctrlbit = (1 << 12),
646 .devname = "dw_mmc.1",
647 .parent = &exynos5_clk_aclk_200.clk,
648 .enable = exynos5_clk_ip_fsys_ctrl,
649 .ctrlbit = (1 << 13),
652 .devname = "dw_mmc.2",
653 .parent = &exynos5_clk_aclk_200.clk,
654 .enable = exynos5_clk_ip_fsys_ctrl,
655 .ctrlbit = (1 << 14),
658 .devname = "dw_mmc.3",
659 .parent = &exynos5_clk_aclk_200.clk,
660 .enable = exynos5_clk_ip_fsys_ctrl,
661 .ctrlbit = (1 << 15),
665 .enable = exynos5_clk_ip_fsys_ctrl,
669 .enable = exynos5_clk_ip_fsys_ctrl,
670 .ctrlbit = (1 << 24),
672 .name = "sata_phy_i2c",
673 .enable = exynos5_clk_ip_fsys_ctrl,
674 .ctrlbit = (1 << 25),
677 .devname = "s5p-mfc-v6",
678 .enable = exynos5_clk_ip_mfc_ctrl,
682 .devname = "exynos5-hdmi",
683 .enable = exynos5_clk_ip_disp1_ctrl,
687 .devname = "exynos5-hdmi",
688 .enable = exynos5_clk_hdmiphy_ctrl,
692 .devname = "exynos5-mixer",
693 .enable = exynos5_clk_ip_disp1_ctrl,
697 .enable = exynos5_clk_ip_gen_ctrl,
701 .enable = exynos5_clk_ip_disp1_ctrl,
705 .devname = "samsung-i2s.1",
706 .enable = exynos5_clk_ip_peric_ctrl,
707 .ctrlbit = (1 << 20),
710 .devname = "samsung-i2s.2",
711 .enable = exynos5_clk_ip_peric_ctrl,
712 .ctrlbit = (1 << 21),
715 .devname = "samsung-pcm.1",
716 .enable = exynos5_clk_ip_peric_ctrl,
717 .ctrlbit = (1 << 22),
720 .devname = "samsung-pcm.2",
721 .enable = exynos5_clk_ip_peric_ctrl,
722 .ctrlbit = (1 << 23),
725 .devname = "samsung-spdif",
726 .enable = exynos5_clk_ip_peric_ctrl,
727 .ctrlbit = (1 << 26),
730 .devname = "samsung-ac97",
731 .enable = exynos5_clk_ip_peric_ctrl,
732 .ctrlbit = (1 << 27),
735 .enable = exynos5_clk_ip_fsys_ctrl ,
736 .ctrlbit = (1 << 18),
739 .enable = exynos5_clk_ip_fsys_ctrl,
743 .enable = exynos5_clk_ip_fsys_ctrl,
744 .ctrlbit = (1 << 22),
747 .enable = exynos5_clk_ip_fsys_ctrl,
748 .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)),
751 .enable = exynos5_clk_ip_core_ctrl,
752 .ctrlbit = ((1 << 21) | (1 << 3)),
755 .enable = exynos5_clk_ip_fsys_ctrl,
759 .devname = "s3c2440-i2c.0",
760 .parent = &exynos5_clk_aclk_66.clk,
761 .enable = exynos5_clk_ip_peric_ctrl,
765 .devname = "s3c2440-i2c.1",
766 .parent = &exynos5_clk_aclk_66.clk,
767 .enable = exynos5_clk_ip_peric_ctrl,
771 .devname = "s3c2440-i2c.2",
772 .parent = &exynos5_clk_aclk_66.clk,
773 .enable = exynos5_clk_ip_peric_ctrl,
777 .devname = "s3c2440-i2c.3",
778 .parent = &exynos5_clk_aclk_66.clk,
779 .enable = exynos5_clk_ip_peric_ctrl,
783 .devname = "s3c2440-i2c.4",
784 .parent = &exynos5_clk_aclk_66.clk,
785 .enable = exynos5_clk_ip_peric_ctrl,
786 .ctrlbit = (1 << 10),
789 .devname = "s3c2440-i2c.5",
790 .parent = &exynos5_clk_aclk_66.clk,
791 .enable = exynos5_clk_ip_peric_ctrl,
792 .ctrlbit = (1 << 11),
795 .devname = "s3c2440-i2c.6",
796 .parent = &exynos5_clk_aclk_66.clk,
797 .enable = exynos5_clk_ip_peric_ctrl,
798 .ctrlbit = (1 << 12),
801 .devname = "s3c2440-i2c.7",
802 .parent = &exynos5_clk_aclk_66.clk,
803 .enable = exynos5_clk_ip_peric_ctrl,
804 .ctrlbit = (1 << 13),
807 .devname = "s3c2440-hdmiphy-i2c",
808 .parent = &exynos5_clk_aclk_66.clk,
809 .enable = exynos5_clk_ip_peric_ctrl,
810 .ctrlbit = (1 << 14),
813 .devname = "exynos4210-spi.0",
814 .parent = &exynos5_clk_aclk_66.clk,
815 .enable = exynos5_clk_ip_peric_ctrl,
816 .ctrlbit = (1 << 16),
819 .devname = "exynos4210-spi.1",
820 .parent = &exynos5_clk_aclk_66.clk,
821 .enable = exynos5_clk_ip_peric_ctrl,
822 .ctrlbit = (1 << 17),
825 .devname = "exynos4210-spi.2",
826 .parent = &exynos5_clk_aclk_66.clk,
827 .enable = exynos5_clk_ip_peric_ctrl,
828 .ctrlbit = (1 << 18),
831 .devname = "exynos-gsc.0",
832 .enable = exynos5_clk_ip_gscl_ctrl,
836 .devname = "exynos-gsc.1",
837 .enable = exynos5_clk_ip_gscl_ctrl,
841 .devname = "exynos-gsc.2",
842 .enable = exynos5_clk_ip_gscl_ctrl,
846 .devname = "exynos-gsc.3",
847 .enable = exynos5_clk_ip_gscl_ctrl,
850 .name = SYSMMU_CLOCK_NAME,
851 .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
852 .enable = &exynos5_clk_ip_mfc_ctrl,
855 .name = SYSMMU_CLOCK_NAME,
856 .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
857 .enable = &exynos5_clk_ip_mfc_ctrl,
860 .name = SYSMMU_CLOCK_NAME,
861 .devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
862 .enable = &exynos5_clk_ip_disp1_ctrl,
865 .name = SYSMMU_CLOCK_NAME,
866 .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
867 .enable = &exynos5_clk_ip_gen_ctrl,
870 .name = SYSMMU_CLOCK_NAME,
871 .devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
872 .enable = &exynos5_clk_ip_gen_ctrl,
875 .name = SYSMMU_CLOCK_NAME,
876 .devname = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
877 .enable = &exynos5_clk_ip_gscl_ctrl,
880 .name = SYSMMU_CLOCK_NAME,
881 .devname = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
882 .enable = &exynos5_clk_ip_gscl_ctrl,
885 .name = SYSMMU_CLOCK_NAME,
886 .devname = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
887 .enable = &exynos5_clk_ip_gscl_ctrl,
890 .name = SYSMMU_CLOCK_NAME,
891 .devname = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
892 .enable = &exynos5_clk_ip_gscl_ctrl,
893 .ctrlbit = (1 << 10),
895 .name = SYSMMU_CLOCK_NAME,
896 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
897 .enable = &exynos5_clk_ip_isp0_ctrl,
898 .ctrlbit = (0x3F << 8),
900 .name = SYSMMU_CLOCK_NAME2,
901 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
902 .enable = &exynos5_clk_ip_isp1_ctrl,
903 .ctrlbit = (0xF << 4),
905 .name = SYSMMU_CLOCK_NAME,
906 .devname = SYSMMU_CLOCK_DEVNAME(camif0, 12),
907 .enable = &exynos5_clk_ip_gscl_ctrl,
908 .ctrlbit = (1 << 11),
910 .name = SYSMMU_CLOCK_NAME,
911 .devname = SYSMMU_CLOCK_DEVNAME(camif1, 13),
912 .enable = &exynos5_clk_ip_gscl_ctrl,
913 .ctrlbit = (1 << 12),
915 .name = SYSMMU_CLOCK_NAME,
916 .devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
917 .enable = &exynos5_clk_ip_acp_ctrl,
922 static struct clk exynos5_init_clocks_on[] = {
925 .devname = "s5pv210-uart.0",
926 .enable = exynos5_clk_ip_peric_ctrl,
930 .devname = "s5pv210-uart.1",
931 .enable = exynos5_clk_ip_peric_ctrl,
935 .devname = "s5pv210-uart.2",
936 .enable = exynos5_clk_ip_peric_ctrl,
940 .devname = "s5pv210-uart.3",
941 .enable = exynos5_clk_ip_peric_ctrl,
945 .devname = "s5pv210-uart.4",
946 .enable = exynos5_clk_ip_peric_ctrl,
950 .devname = "s5pv210-uart.5",
951 .enable = exynos5_clk_ip_peric_ctrl,
956 static struct clk exynos5_clk_pdma0 = {
958 .devname = "dma-pl330.0",
959 .enable = exynos5_clk_ip_fsys_ctrl,
963 static struct clk exynos5_clk_pdma1 = {
965 .devname = "dma-pl330.1",
966 .enable = exynos5_clk_ip_fsys_ctrl,
970 static struct clk exynos5_clk_mdma1 = {
972 .devname = "dma-pl330.2",
973 .enable = exynos5_clk_ip_gen_ctrl,
977 static struct clk exynos5_clk_fimd1 = {
979 .devname = "exynos5-fb.1",
980 .enable = exynos5_clk_ip_disp1_ctrl,
984 static struct clk *exynos5_clkset_group_list[] = {
985 [0] = &clk_ext_xtal_mux,
987 [2] = &exynos5_clk_sclk_hdmi24m,
988 [3] = &exynos5_clk_sclk_dptxphy,
989 [4] = &exynos5_clk_sclk_usbphy,
990 [5] = &exynos5_clk_sclk_hdmiphy,
991 [6] = &exynos5_clk_mout_mpll_user.clk,
992 [7] = &exynos5_clk_mout_epll.clk,
993 [8] = &exynos5_clk_sclk_vpll.clk,
994 [9] = &exynos5_clk_mout_cpll.clk,
997 static struct clksrc_sources exynos5_clkset_group = {
998 .sources = exynos5_clkset_group_list,
999 .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
1002 /* Possible clock sources for aclk_266_gscl_sub Mux */
1003 static struct clk *clk_src_gscl_266_list[] = {
1004 [0] = &clk_ext_xtal_mux,
1005 [1] = &exynos5_clk_aclk_266.clk,
1008 static struct clksrc_sources clk_src_gscl_266 = {
1009 .sources = clk_src_gscl_266_list,
1010 .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list),
1013 static struct clksrc_clk exynos5_clk_dout_mmc0 = {
1015 .name = "dout_mmc0",
1017 .sources = &exynos5_clkset_group,
1018 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
1019 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
1022 static struct clksrc_clk exynos5_clk_dout_mmc1 = {
1024 .name = "dout_mmc1",
1026 .sources = &exynos5_clkset_group,
1027 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
1028 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1031 static struct clksrc_clk exynos5_clk_dout_mmc2 = {
1033 .name = "dout_mmc2",
1035 .sources = &exynos5_clkset_group,
1036 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
1037 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1040 static struct clksrc_clk exynos5_clk_dout_mmc3 = {
1042 .name = "dout_mmc3",
1044 .sources = &exynos5_clkset_group,
1045 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
1046 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1049 static struct clksrc_clk exynos5_clk_dout_mmc4 = {
1051 .name = "dout_mmc4",
1053 .sources = &exynos5_clkset_group,
1054 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
1055 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1058 static struct clksrc_clk exynos5_clk_sclk_uart0 = {
1061 .devname = "exynos4210-uart.0",
1062 .enable = exynos5_clksrc_mask_peric0_ctrl,
1063 .ctrlbit = (1 << 0),
1065 .sources = &exynos5_clkset_group,
1066 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
1067 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
1070 static struct clksrc_clk exynos5_clk_sclk_uart1 = {
1073 .devname = "exynos4210-uart.1",
1074 .enable = exynos5_clksrc_mask_peric0_ctrl,
1075 .ctrlbit = (1 << 4),
1077 .sources = &exynos5_clkset_group,
1078 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
1079 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
1082 static struct clksrc_clk exynos5_clk_sclk_uart2 = {
1085 .devname = "exynos4210-uart.2",
1086 .enable = exynos5_clksrc_mask_peric0_ctrl,
1087 .ctrlbit = (1 << 8),
1089 .sources = &exynos5_clkset_group,
1090 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
1091 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
1094 static struct clksrc_clk exynos5_clk_sclk_uart3 = {
1097 .devname = "exynos4210-uart.3",
1098 .enable = exynos5_clksrc_mask_peric0_ctrl,
1099 .ctrlbit = (1 << 12),
1101 .sources = &exynos5_clkset_group,
1102 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
1103 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
1106 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
1108 .name = "ciu", /* card interface unit clock */
1109 .devname = "dw_mmc.0",
1110 .parent = &exynos5_clk_dout_mmc0.clk,
1111 .enable = exynos5_clksrc_mask_fsys_ctrl,
1112 .ctrlbit = (1 << 0),
1114 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1117 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
1120 .devname = "dw_mmc.1",
1121 .parent = &exynos5_clk_dout_mmc1.clk,
1122 .enable = exynos5_clksrc_mask_fsys_ctrl,
1123 .ctrlbit = (1 << 4),
1125 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1128 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
1131 .devname = "dw_mmc.2",
1132 .parent = &exynos5_clk_dout_mmc2.clk,
1133 .enable = exynos5_clksrc_mask_fsys_ctrl,
1134 .ctrlbit = (1 << 8),
1136 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1139 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1142 .devname = "dw_mmc.3",
1143 .parent = &exynos5_clk_dout_mmc3.clk,
1144 .enable = exynos5_clksrc_mask_fsys_ctrl,
1145 .ctrlbit = (1 << 12),
1147 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1150 static struct clksrc_clk exynos5_clk_mdout_spi0 = {
1152 .name = "mdout_spi",
1153 .devname = "exynos4210-spi.0",
1155 .sources = &exynos5_clkset_group,
1156 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
1157 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
1160 static struct clksrc_clk exynos5_clk_mdout_spi1 = {
1162 .name = "mdout_spi",
1163 .devname = "exynos4210-spi.1",
1165 .sources = &exynos5_clkset_group,
1166 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
1167 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
1170 static struct clksrc_clk exynos5_clk_mdout_spi2 = {
1172 .name = "mdout_spi",
1173 .devname = "exynos4210-spi.2",
1175 .sources = &exynos5_clkset_group,
1176 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
1177 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
1180 static struct clksrc_clk exynos5_clk_sclk_spi0 = {
1183 .devname = "exynos4210-spi.0",
1184 .parent = &exynos5_clk_mdout_spi0.clk,
1185 .enable = exynos5_clksrc_mask_peric1_ctrl,
1186 .ctrlbit = (1 << 16),
1188 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
1191 static struct clksrc_clk exynos5_clk_sclk_spi1 = {
1194 .devname = "exynos4210-spi.1",
1195 .parent = &exynos5_clk_mdout_spi1.clk,
1196 .enable = exynos5_clksrc_mask_peric1_ctrl,
1197 .ctrlbit = (1 << 20),
1199 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
1202 static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1205 .devname = "exynos4210-spi.2",
1206 .parent = &exynos5_clk_mdout_spi2.clk,
1207 .enable = exynos5_clksrc_mask_peric1_ctrl,
1208 .ctrlbit = (1 << 24),
1210 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1213 static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
1215 .name = "sclk_fimd",
1216 .devname = "exynos5-fb.1",
1217 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
1218 .ctrlbit = (1 << 0),
1220 .sources = &exynos5_clkset_group,
1221 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1222 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1225 static struct clksrc_clk exynos5_clksrcs[] = {
1228 .name = "aclk_266_gscl",
1230 .sources = &clk_src_gscl_266,
1231 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1235 .devname = "mali-t604.0",
1236 .enable = exynos5_clk_block_ctrl,
1237 .ctrlbit = (1 << 1),
1239 .sources = &exynos5_clkset_aclk,
1240 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1241 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1244 .name = "sclk_gscl_wrap",
1245 .devname = "s5p-mipi-csis.0",
1246 .enable = exynos5_clksrc_mask_gscl_ctrl,
1247 .ctrlbit = (1 << 24),
1249 .sources = &exynos5_clkset_group,
1250 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1251 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1254 .name = "sclk_gscl_wrap",
1255 .devname = "s5p-mipi-csis.1",
1256 .enable = exynos5_clksrc_mask_gscl_ctrl,
1257 .ctrlbit = (1 << 28),
1259 .sources = &exynos5_clkset_group,
1260 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1261 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1264 .name = "sclk_cam0",
1265 .enable = exynos5_clksrc_mask_gscl_ctrl,
1266 .ctrlbit = (1 << 16),
1268 .sources = &exynos5_clkset_group,
1269 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1270 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1273 .name = "sclk_cam1",
1274 .enable = exynos5_clksrc_mask_gscl_ctrl,
1275 .ctrlbit = (1 << 20),
1277 .sources = &exynos5_clkset_group,
1278 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1279 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1282 .name = "sclk_jpeg",
1283 .parent = &exynos5_clk_mout_cpll.clk,
1285 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1289 /* Clock initialization code */
1290 static struct clksrc_clk *exynos5_sysclks[] = {
1291 &exynos5_clk_mout_apll,
1292 &exynos5_clk_sclk_apll,
1293 &exynos5_clk_mout_bpll,
1294 &exynos5_clk_mout_bpll_fout,
1295 &exynos5_clk_mout_bpll_user,
1296 &exynos5_clk_mout_cpll,
1297 &exynos5_clk_mout_epll,
1298 &exynos5_clk_mout_mpll,
1299 &exynos5_clk_mout_mpll_fout,
1300 &exynos5_clk_mout_mpll_user,
1301 &exynos5_clk_vpllsrc,
1302 &exynos5_clk_sclk_vpll,
1303 &exynos5_clk_mout_cpu,
1304 &exynos5_clk_dout_armclk,
1305 &exynos5_clk_dout_arm2clk,
1307 &exynos5_clk_aclk_400,
1308 &exynos5_clk_aclk_333,
1309 &exynos5_clk_aclk_266,
1310 &exynos5_clk_aclk_200,
1311 &exynos5_clk_aclk_166,
1312 &exynos5_clk_aclk_300_gscl,
1313 &exynos5_clk_mout_aclk_300_gscl,
1314 &exynos5_clk_mout_aclk_300_gscl_mid,
1315 &exynos5_clk_mout_aclk_300_gscl_mid1,
1316 &exynos5_clk_aclk_66_pre,
1317 &exynos5_clk_aclk_66,
1318 &exynos5_clk_dout_mmc0,
1319 &exynos5_clk_dout_mmc1,
1320 &exynos5_clk_dout_mmc2,
1321 &exynos5_clk_dout_mmc3,
1322 &exynos5_clk_dout_mmc4,
1323 &exynos5_clk_aclk_acp,
1324 &exynos5_clk_pclk_acp,
1325 &exynos5_clk_sclk_spi0,
1326 &exynos5_clk_sclk_spi1,
1327 &exynos5_clk_sclk_spi2,
1328 &exynos5_clk_mdout_spi0,
1329 &exynos5_clk_mdout_spi1,
1330 &exynos5_clk_mdout_spi2,
1331 &exynos5_clk_sclk_fimd1,
1334 static struct clk *exynos5_clk_cdev[] = {
1341 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1342 &exynos5_clk_sclk_uart0,
1343 &exynos5_clk_sclk_uart1,
1344 &exynos5_clk_sclk_uart2,
1345 &exynos5_clk_sclk_uart3,
1346 &exynos5_clk_sclk_mmc0,
1347 &exynos5_clk_sclk_mmc1,
1348 &exynos5_clk_sclk_mmc2,
1349 &exynos5_clk_sclk_mmc3,
1352 static struct clk_lookup exynos5_clk_lookup[] = {
1353 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1354 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1355 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1356 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1357 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1358 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1359 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1360 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1361 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
1362 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
1363 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
1364 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1365 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1366 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1367 CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
1370 static unsigned long exynos5_epll_get_rate(struct clk *clk)
1375 static struct clk *exynos5_clks[] __initdata = {
1376 &exynos5_clk_sclk_hdmi27m,
1377 &exynos5_clk_sclk_hdmiphy,
1379 &clk_fout_bpll_div2,
1381 &clk_fout_mpll_div2,
1382 &exynos5_clk_armclk,
1385 static u32 epll_div[][6] = {
1386 { 192000000, 0, 48, 3, 1, 0 },
1387 { 180000000, 0, 45, 3, 1, 0 },
1388 { 73728000, 1, 73, 3, 3, 47710 },
1389 { 67737600, 1, 90, 4, 3, 20762 },
1390 { 49152000, 0, 49, 3, 3, 9961 },
1391 { 45158400, 0, 45, 3, 3, 10381 },
1392 { 180633600, 0, 45, 3, 1, 10381 },
1395 static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1397 unsigned int epll_con, epll_con_k;
1400 unsigned int epll_rate;
1401 unsigned int locktime;
1402 unsigned int lockcnt;
1404 /* Return if nothing changed */
1405 if (clk->rate == rate)
1409 epll_rate = clk_get_rate(clk->parent);
1411 epll_rate = clk_ext_xtal_mux.rate;
1413 if (epll_rate != 24000000) {
1414 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1418 epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1419 epll_con &= ~(0x1 << 27 | \
1420 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1421 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1422 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1424 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1425 if (epll_div[i][0] == rate) {
1426 epll_con_k = epll_div[i][5] << 0;
1427 epll_con |= epll_div[i][1] << 27;
1428 epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1429 epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1430 epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1435 if (i == ARRAY_SIZE(epll_div)) {
1436 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1441 epll_rate /= 1000000;
1443 /* 3000 max_cycls : specification data */
1444 locktime = 3000 / epll_rate * epll_div[i][3];
1445 lockcnt = locktime * 10000 / (10000 / epll_rate);
1447 __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1449 __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1450 __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1453 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1454 } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1461 static struct clk_ops exynos5_epll_ops = {
1462 .get_rate = exynos5_epll_get_rate,
1463 .set_rate = exynos5_epll_set_rate,
1466 static int xtal_rate;
1468 static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1470 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1473 static struct clk_ops exynos5_fout_apll_ops = {
1474 .get_rate = exynos5_fout_apll_get_rate,
1478 static int exynos5_clock_suspend(void)
1480 s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1485 static void exynos5_clock_resume(void)
1487 s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1490 #define exynos5_clock_suspend NULL
1491 #define exynos5_clock_resume NULL
1494 static struct syscore_ops exynos5_clock_syscore_ops = {
1495 .suspend = exynos5_clock_suspend,
1496 .resume = exynos5_clock_resume,
1499 void __init_or_cpufreq exynos5_setup_clocks(void)
1501 struct clk *xtal_clk;
1508 unsigned long vpllsrc;
1510 unsigned long armclk;
1511 unsigned long mout_cdrex;
1512 unsigned long aclk_400;
1513 unsigned long aclk_333;
1514 unsigned long aclk_266;
1515 unsigned long aclk_200;
1516 unsigned long aclk_166;
1517 unsigned long aclk_66;
1520 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1522 xtal_clk = clk_get(NULL, "xtal");
1523 BUG_ON(IS_ERR(xtal_clk));
1525 xtal = clk_get_rate(xtal_clk);
1531 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1533 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1534 bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1535 cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1536 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1537 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1538 __raw_readl(EXYNOS5_EPLL_CON1));
1540 vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1541 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1542 __raw_readl(EXYNOS5_VPLL_CON1));
1544 clk_fout_apll.ops = &exynos5_fout_apll_ops;
1545 clk_fout_bpll.rate = bpll;
1546 clk_fout_bpll_div2.rate = bpll >> 1;
1547 clk_fout_cpll.rate = cpll;
1548 clk_fout_mpll.rate = mpll;
1549 clk_fout_mpll_div2.rate = mpll >> 1;
1550 clk_fout_epll.rate = epll;
1551 clk_fout_vpll.rate = vpll;
1553 printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1554 "M=%ld, E=%ld V=%ld",
1555 apll, bpll, cpll, mpll, epll, vpll);
1557 armclk = clk_get_rate(&exynos5_clk_armclk);
1558 mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1560 aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1561 aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1562 aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1563 aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1564 aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1565 aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1567 printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1568 "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1569 "ACLK166=%ld, ACLK66=%ld\n",
1570 armclk, mout_cdrex, aclk_400,
1571 aclk_333, aclk_266, aclk_200,
1575 clk_fout_epll.ops = &exynos5_epll_ops;
1577 if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1578 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1579 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1581 clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1582 clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1584 clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1585 clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1587 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1588 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1591 void __init exynos5_register_clocks(void)
1595 s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1597 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1598 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1600 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1601 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1603 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1604 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1606 s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1607 s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1609 s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1610 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1611 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1613 s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1614 s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1615 clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1617 register_syscore_ops(&exynos5_clock_syscore_ops);