arch/arm/mach-exynos/clock-exynos5.c

   1 /*
   2  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Clock support for EXYNOS5 SoCs
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/syscore_ops.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23 #include <plat/pm.h>
  24
  25 #include <mach/map.h>
  26 #include <mach/regs-clock.h>
  27 #include <mach/sysmmu.h>
  28
  29 #include "common.h"
  30
  31 #ifdef CONFIG_PM_SLEEP
  32 static struct sleep_save exynos5_clock_save[] = {
  33         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
  34         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
  35         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
  36         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
  37         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
  38         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
  39         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
  40         SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
  41         SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
  42         SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
  43         SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
  44         SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
  45         SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
  46         SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
  47         SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
  48         SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
  49         SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
  50         SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
  51         SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
  52         SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
  53         SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
  54         SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
  55         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
  56         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
  57         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
  58         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
  59         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
  60         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
  61         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
  62         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
  63         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
  64         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
  65         SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
  66         SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
  67         SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
  68         SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
  69         SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
  70         SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
  71         SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
  72         SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
  73         SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
  74         SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
  75         SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
  76         SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
  77         SAVE_ITEM(EXYNOS5_EPLL_CON0),
  78         SAVE_ITEM(EXYNOS5_EPLL_CON1),
  79         SAVE_ITEM(EXYNOS5_EPLL_CON2),
  80         SAVE_ITEM(EXYNOS5_VPLL_CON0),
  81         SAVE_ITEM(EXYNOS5_VPLL_CON1),
  82         SAVE_ITEM(EXYNOS5_VPLL_CON2),
  83         SAVE_ITEM(EXYNOS5_PWR_CTRL1),
  84         SAVE_ITEM(EXYNOS5_PWR_CTRL2),
  85 };
  86 #endif
  87
  88 static struct clk exynos5_clk_sclk_dptxphy = {
  89         .name           = "sclk_dptx",
  90 };
  91
  92 static struct clk exynos5_clk_sclk_hdmi24m = {
  93         .name           = "sclk_hdmi24m",
  94         .rate           = 24000000,
  95 };
  96
  97 static struct clk exynos5_clk_sclk_hdmi27m = {
  98         .name           = "sclk_hdmi27m",
  99         .rate           = 27000000,
 100 };
 101
 102 static struct clk exynos5_clk_sclk_hdmiphy = {
 103         .name           = "sclk_hdmiphy",
 104 };
 105
 106 static struct clk exynos5_clk_sclk_usbphy = {
 107         .name           = "sclk_usbphy",
 108         .rate           = 48000000,
 109 };
 110
 111 static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 112 {
 113         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
 114 }
 115
 116 static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
 117 {
 118         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
 119 }
 120
 121 static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 122 {
 123         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
 124 }
 125
 126 static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
 127 {
 128         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
 129 }
 130
 131 static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
 132 {
 133         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
 134 }
 135
 136 static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
 137 {
 138         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
 139 }
 140
 141 static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
 142 {
 143         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
 144 }
 145
 146 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
 147 {
 148         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
 149 }
 150
 151 static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
 152 {
 153         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
 154 }
 155
 156 static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 157 {
 158         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
 159 }
 160
 161 static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
 162 {
 163         return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
 164 }
 165
 166 static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
 167 {
 168         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
 169 }
 170
 171 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 172 {
 173         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
 174 }
 175
 176 static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
 177 {
 178         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
 179 }
 180
 181 static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
 182 {
 183         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
 184 }
 185
 186 static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
 187 {
 188         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
 189 }
 190
 191 static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
 192 {
 193         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
 194 }
 195
 196 static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
 197 {
 198         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
 199 }
 200
 201 static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 202 {
 203         return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
 204 }
 205
 206 /* Core list of CMU_CPU side */
 207
 208 static struct clksrc_clk exynos5_clk_mout_apll = {
 209         .clk    = {
 210                 .name           = "mout_apll",
 211         },
 212         .sources = &clk_src_apll,
 213         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
 214 };
 215
 216 static struct clksrc_clk exynos5_clk_sclk_apll = {
 217         .clk    = {
 218                 .name           = "sclk_apll",
 219                 .parent         = &exynos5_clk_mout_apll.clk,
 220         },
 221         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 222 };
 223
 224 static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
 225         .clk    = {
 226                 .name           = "mout_bpll_fout",
 227         },
 228         .sources = &clk_src_bpll_fout,
 229         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
 230 };
 231
 232 static struct clk *exynos5_clk_src_bpll_list[] = {
 233         [0] = &clk_fin_bpll,
 234         [1] = &exynos5_clk_mout_bpll_fout.clk,
 235 };
 236
 237 static struct clksrc_sources exynos5_clk_src_bpll = {
 238         .sources        = exynos5_clk_src_bpll_list,
 239         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
 240 };
 241
 242 static struct clksrc_clk exynos5_clk_mout_bpll = {
 243         .clk    = {
 244                 .name           = "mout_bpll",
 245         },
 246         .sources = &exynos5_clk_src_bpll,
 247         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
 248 };
 249
 250 static struct clk *exynos5_clk_src_bpll_user_list[] = {
 251         [0] = &clk_fin_mpll,
 252         [1] = &exynos5_clk_mout_bpll.clk,
 253 };
 254
 255 static struct clksrc_sources exynos5_clk_src_bpll_user = {
 256         .sources        = exynos5_clk_src_bpll_user_list,
 257         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
 258 };
 259
 260 static struct clksrc_clk exynos5_clk_mout_bpll_user = {
 261         .clk    = {
 262                 .name           = "mout_bpll_user",
 263         },
 264         .sources = &exynos5_clk_src_bpll_user,
 265         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
 266 };
 267
 268 static struct clksrc_clk exynos5_clk_mout_cpll = {
 269         .clk    = {
 270                 .name           = "mout_cpll",
 271         },
 272         .sources = &clk_src_cpll,
 273         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
 274 };
 275
 276 static struct clksrc_clk exynos5_clk_mout_epll = {
 277         .clk    = {
 278                 .name           = "mout_epll",
 279         },
 280         .sources = &clk_src_epll,
 281         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 282 };
 283
 284 static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
 285         .clk    = {
 286                 .name           = "mout_mpll_fout",
 287         },
 288         .sources = &clk_src_mpll_fout,
 289         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
 290 };
 291
 292 static struct clk *exynos5_clk_src_mpll_list[] = {
 293         [0] = &clk_fin_mpll,
 294         [1] = &exynos5_clk_mout_mpll_fout.clk,
 295 };
 296
 297 static struct clksrc_sources exynos5_clk_src_mpll = {
 298         .sources        = exynos5_clk_src_mpll_list,
 299         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
 300 };
 301
 302 struct clksrc_clk exynos5_clk_mout_mpll = {
 303         .clk = {
 304                 .name           = "mout_mpll",
 305         },
 306         .sources = &exynos5_clk_src_mpll,
 307         .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 308 };
 309
 310 static struct clk *exynos_clkset_vpllsrc_list[] = {
 311         [0] = &clk_fin_vpll,
 312         [1] = &exynos5_clk_sclk_hdmi27m,
 313 };
 314
 315 static struct clksrc_sources exynos5_clkset_vpllsrc = {
 316         .sources        = exynos_clkset_vpllsrc_list,
 317         .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
 318 };
 319
 320 static struct clksrc_clk exynos5_clk_vpllsrc = {
 321         .clk    = {
 322                 .name           = "vpll_src",
 323                 .enable         = exynos5_clksrc_mask_top_ctrl,
 324                 .ctrlbit        = (1 << 0),
 325         },
 326         .sources = &exynos5_clkset_vpllsrc,
 327         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
 328 };
 329
 330 static struct clk *exynos5_clkset_sclk_vpll_list[] = {
 331         [0] = &exynos5_clk_vpllsrc.clk,
 332         [1] = &clk_fout_vpll,
 333 };
 334
 335 static struct clksrc_sources exynos5_clkset_sclk_vpll = {
 336         .sources        = exynos5_clkset_sclk_vpll_list,
 337         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
 338 };
 339
 340 static struct clksrc_clk exynos5_clk_sclk_vpll = {
 341         .clk    = {
 342                 .name           = "sclk_vpll",
 343         },
 344         .sources = &exynos5_clkset_sclk_vpll,
 345         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
 346 };
 347
 348 static struct clksrc_clk exynos5_clk_sclk_pixel = {
 349         .clk    = {
 350                 .name           = "sclk_pixel",
 351                 .parent         = &exynos5_clk_sclk_vpll.clk,
 352         },
 353         .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
 354 };
 355
 356 static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
 357         [0] = &exynos5_clk_sclk_pixel.clk,
 358         [1] = &exynos5_clk_sclk_hdmiphy,
 359 };
 360
 361 static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
 362         .sources        = exynos5_clkset_sclk_hdmi_list,
 363         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
 364 };
 365
 366 static struct clksrc_clk exynos5_clk_sclk_hdmi = {
 367         .clk    = {
 368                 .name           = "sclk_hdmi",
 369                 .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
 370                 .ctrlbit        = (1 << 20),
 371         },
 372         .sources = &exynos5_clkset_sclk_hdmi,
 373         .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
 374 };
 375
 376 static struct clksrc_clk *exynos5_sclk_tv[] = {
 377         &exynos5_clk_sclk_pixel,
 378         &exynos5_clk_sclk_hdmi,
 379 };
 380
 381 static struct clk *exynos5_clk_src_mpll_user_list[] = {
 382         [0] = &clk_fin_mpll,
 383         [1] = &exynos5_clk_mout_mpll.clk,
 384 };
 385
 386 static struct clksrc_sources exynos5_clk_src_mpll_user = {
 387         .sources        = exynos5_clk_src_mpll_user_list,
 388         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
 389 };
 390
 391 static struct clksrc_clk exynos5_clk_mout_mpll_user = {
 392         .clk    = {
 393                 .name           = "mout_mpll_user",
 394         },
 395         .sources = &exynos5_clk_src_mpll_user,
 396         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
 397 };
 398
 399 static struct clk *exynos5_clkset_mout_cpu_list[] = {
 400         [0] = &exynos5_clk_mout_apll.clk,
 401         [1] = &exynos5_clk_mout_mpll.clk,
 402 };
 403
 404 static struct clksrc_sources exynos5_clkset_mout_cpu = {
 405         .sources        = exynos5_clkset_mout_cpu_list,
 406         .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
 407 };
 408
 409 static struct clksrc_clk exynos5_clk_mout_cpu = {
 410         .clk    = {
 411                 .name           = "mout_cpu",
 412         },
 413         .sources = &exynos5_clkset_mout_cpu,
 414         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
 415 };
 416
 417 static struct clksrc_clk exynos5_clk_dout_armclk = {
 418         .clk    = {
 419                 .name           = "dout_armclk",
 420                 .parent         = &exynos5_clk_mout_cpu.clk,
 421         },
 422         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
 423 };
 424
 425 static struct clksrc_clk exynos5_clk_dout_arm2clk = {
 426         .clk    = {
 427                 .name           = "dout_arm2clk",
 428                 .parent         = &exynos5_clk_dout_armclk.clk,
 429         },
 430         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
 431 };
 432
 433 static struct clk exynos5_clk_armclk = {
 434         .name           = "armclk",
 435         .parent         = &exynos5_clk_dout_arm2clk.clk,
 436 };
 437
 438 /* Core list of CMU_CDREX side */
 439
 440 static struct clk *exynos5_clkset_cdrex_list[] = {
 441         [0] = &exynos5_clk_mout_mpll.clk,
 442         [1] = &exynos5_clk_mout_bpll.clk,
 443 };
 444
 445 static struct clksrc_sources exynos5_clkset_cdrex = {
 446         .sources        = exynos5_clkset_cdrex_list,
 447         .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
 448 };
 449
 450 static struct clksrc_clk exynos5_clk_cdrex = {
 451         .clk    = {
 452                 .name           = "clk_cdrex",
 453         },
 454         .sources = &exynos5_clkset_cdrex,
 455         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
 456         .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
 457 };
 458
 459 static struct clksrc_clk exynos5_clk_aclk_acp = {
 460         .clk    = {
 461                 .name           = "aclk_acp",
 462                 .parent         = &exynos5_clk_mout_mpll.clk,
 463         },
 464         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
 465 };
 466
 467 static struct clksrc_clk exynos5_clk_pclk_acp = {
 468         .clk    = {
 469                 .name           = "pclk_acp",
 470                 .parent         = &exynos5_clk_aclk_acp.clk,
 471         },
 472         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
 473 };
 474
 475 /* Core list of CMU_TOP side */
 476
 477 struct clk *exynos5_clkset_aclk_top_list[] = {
 478         [0] = &exynos5_clk_mout_mpll_user.clk,
 479         [1] = &exynos5_clk_mout_bpll_user.clk,
 480 };
 481
 482 struct clksrc_sources exynos5_clkset_aclk = {
 483         .sources        = exynos5_clkset_aclk_top_list,
 484         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
 485 };
 486
 487 static struct clksrc_clk exynos5_clk_aclk_400 = {
 488         .clk    = {
 489                 .name           = "aclk_400",
 490         },
 491         .sources = &exynos5_clkset_aclk,
 492         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
 493         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
 494 };
 495
 496 struct clk *exynos5_clkset_aclk_333_166_list[] = {
 497         [0] = &exynos5_clk_mout_cpll.clk,
 498         [1] = &exynos5_clk_mout_mpll_user.clk,
 499 };
 500
 501 struct clksrc_sources exynos5_clkset_aclk_333_166 = {
 502         .sources        = exynos5_clkset_aclk_333_166_list,
 503         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
 504 };
 505
 506 static struct clksrc_clk exynos5_clk_aclk_333 = {
 507         .clk    = {
 508                 .name           = "aclk_333",
 509         },
 510         .sources = &exynos5_clkset_aclk_333_166,
 511         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
 512         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
 513 };
 514
 515 static struct clksrc_clk exynos5_clk_aclk_166 = {
 516         .clk    = {
 517                 .name           = "aclk_166",
 518         },
 519         .sources = &exynos5_clkset_aclk_333_166,
 520         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
 521         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
 522 };
 523
 524 static struct clksrc_clk exynos5_clk_aclk_266 = {
 525         .clk    = {
 526                 .name           = "aclk_266",
 527                 .parent         = &exynos5_clk_mout_mpll_user.clk,
 528         },
 529         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
 530 };
 531
 532 static struct clksrc_clk exynos5_clk_aclk_200 = {
 533         .clk    = {
 534                 .name           = "aclk_200",
 535         },
 536         .sources = &exynos5_clkset_aclk,
 537         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
 538         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
 539 };
 540
 541 static struct clksrc_clk exynos5_clk_aclk_66_pre = {
 542         .clk    = {
 543                 .name           = "aclk_66_pre",
 544                 .parent         = &exynos5_clk_mout_mpll_user.clk,
 545         },
 546         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
 547 };
 548
 549 static struct clksrc_clk exynos5_clk_aclk_66 = {
 550         .clk    = {
 551                 .name           = "aclk_66",
 552                 .parent         = &exynos5_clk_aclk_66_pre.clk,
 553         },
 554         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
 555 };
 556
 557 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
 558         .clk    = {
 559                 .name           = "mout_aclk_300_gscl_mid",
 560         },
 561         .sources = &exynos5_clkset_aclk,
 562         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
 563 };
 564
 565 static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
 566         [0] = &exynos5_clk_sclk_vpll.clk,
 567         [1] = &exynos5_clk_mout_cpll.clk,
 568 };
 569
 570 static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
 571         .sources        = exynos5_clkset_aclk_300_mid1_list,
 572         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
 573 };
 574
 575 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
 576         .clk    = {
 577                 .name           = "mout_aclk_300_gscl_mid1",
 578         },
 579         .sources = &exynos5_clkset_aclk_300_gscl_mid1,
 580         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
 581 };
 582
 583 static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
 584         [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
 585         [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
 586 };
 587
 588 static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
 589         .sources        = exynos5_clkset_aclk_300_gscl_list,
 590         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
 591 };
 592
 593 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
 594         .clk    = {
 595                 .name           = "mout_aclk_300_gscl",
 596         },
 597         .sources = &exynos5_clkset_aclk_300_gscl,
 598         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
 599 };
 600
 601 static struct clk *exynos5_clk_src_gscl_300_list[] = {
 602         [0] = &clk_ext_xtal_mux,
 603         [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
 604 };
 605
 606 static struct clksrc_sources exynos5_clk_src_gscl_300 = {
 607         .sources        = exynos5_clk_src_gscl_300_list,
 608         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
 609 };
 610
 611 static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
 612         .clk    = {
 613                 .name           = "aclk_300_gscl",
 614         },
 615         .sources = &exynos5_clk_src_gscl_300,
 616         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
 617 };
 618
 619 static struct clk exynos5_init_clocks_off[] = {
 620         {
 621                 .name           = "timers",
 622                 .parent         = &exynos5_clk_aclk_66.clk,
 623                 .enable         = exynos5_clk_ip_peric_ctrl,
 624                 .ctrlbit        = (1 << 24),
 625         }, {
 626                 .name           = "rtc",
 627                 .parent         = &exynos5_clk_aclk_66.clk,
 628                 .enable         = exynos5_clk_ip_peris_ctrl,
 629                 .ctrlbit        = (1 << 20),
 630         }, {
 631                 .name           = "watchdog",
 632                 .parent         = &exynos5_clk_aclk_66.clk,
 633                 .enable         = exynos5_clk_ip_peris_ctrl,
 634                 .ctrlbit        = (1 << 19),
 635         }, {
 636                 .name           = "biu",        /* bus interface unit clock */
 637                 .devname        = "dw_mmc.0",
 638                 .parent         = &exynos5_clk_aclk_200.clk,
 639                 .enable         = exynos5_clk_ip_fsys_ctrl,
 640                 .ctrlbit        = (1 << 12),
 641         }, {
 642                 .name           = "biu",
 643                 .devname        = "dw_mmc.1",
 644                 .parent         = &exynos5_clk_aclk_200.clk,
 645                 .enable         = exynos5_clk_ip_fsys_ctrl,
 646                 .ctrlbit        = (1 << 13),
 647         }, {
 648                 .name           = "biu",
 649                 .devname        = "dw_mmc.2",
 650                 .parent         = &exynos5_clk_aclk_200.clk,
 651                 .enable         = exynos5_clk_ip_fsys_ctrl,
 652                 .ctrlbit        = (1 << 14),
 653         }, {
 654                 .name           = "biu",
 655                 .devname        = "dw_mmc.3",
 656                 .parent         = &exynos5_clk_aclk_200.clk,
 657                 .enable         = exynos5_clk_ip_fsys_ctrl,
 658                 .ctrlbit        = (1 << 15),
 659         }, {
 660                 .name           = "sata",
 661                 .devname        = "exynos5-sata",
 662                 .parent         = &exynos5_clk_aclk_200.clk,
 663                 .enable         = exynos5_clk_ip_fsys_ctrl,
 664                 .ctrlbit        = (1 << 6),
 665         }, {
 666                 .name           = "sata-phy",
 667                 .devname        = "exynos5-sata-phy",
 668                 .parent         = &exynos5_clk_aclk_200.clk,
 669                 .enable         = exynos5_clk_ip_fsys_ctrl,
 670                 .ctrlbit        = (1 << 24),
 671         }, {
 672                 .name           = "i2c",
 673                 .devname        = "exynos5-sata-phy-i2c",
 674                 .parent         = &exynos5_clk_aclk_200.clk,
 675                 .enable         = exynos5_clk_ip_fsys_ctrl,
 676                 .ctrlbit        = (1 << 25),
 677         }, {
 678                 .name           = "mfc",
 679                 .devname        = "s5p-mfc",
 680                 .enable         = exynos5_clk_ip_mfc_ctrl,
 681                 .ctrlbit        = (1 << 0),
 682         }, {
 683                 .name           = "hdmi",
 684                 .devname        = "exynos5-hdmi",
 685                 .enable         = exynos5_clk_ip_disp1_ctrl,
 686                 .ctrlbit        = (1 << 6),
 687         }, {
 688                 .name           = "hdmiphy",
 689                 .devname        = "exynos5-hdmi",
 690                 .enable         = exynos5_clk_hdmiphy_ctrl,
 691                 .ctrlbit        = (1 << 0),
 692         }, {
 693                 .name           = "mixer",
 694                 .devname        = "exynos5-mixer",
 695                 .enable         = exynos5_clk_ip_disp1_ctrl,
 696                 .ctrlbit        = (1 << 5),
 697         }, {
 698                 .name           = "dp",
 699                 .devname        = "exynos-dp",
 700                 .enable         = exynos5_clk_ip_disp1_ctrl,
 701                 .ctrlbit        = (1 << 4),
 702         }, {
 703                 .name           = "jpeg",
 704                 .enable         = exynos5_clk_ip_gen_ctrl,
 705                 .ctrlbit        = (1 << 2),
 706         }, {
 707                 .name           = "dsim0",
 708                 .enable         = exynos5_clk_ip_disp1_ctrl,
 709                 .ctrlbit        = (1 << 3),
 710         }, {
 711                 .name           = "iis",
 712                 .devname        = "samsung-i2s.1",
 713                 .enable         = exynos5_clk_ip_peric_ctrl,
 714                 .ctrlbit        = (1 << 20),
 715         }, {
 716                 .name           = "iis",
 717                 .devname        = "samsung-i2s.2",
 718                 .enable         = exynos5_clk_ip_peric_ctrl,
 719                 .ctrlbit        = (1 << 21),
 720         }, {
 721                 .name           = "pcm",
 722                 .devname        = "samsung-pcm.1",
 723                 .enable         = exynos5_clk_ip_peric_ctrl,
 724                 .ctrlbit        = (1 << 22),
 725         }, {
 726                 .name           = "pcm",
 727                 .devname        = "samsung-pcm.2",
 728                 .enable         = exynos5_clk_ip_peric_ctrl,
 729                 .ctrlbit        = (1 << 23),
 730         }, {
 731                 .name           = "spdif",
 732                 .devname        = "samsung-spdif",
 733                 .enable         = exynos5_clk_ip_peric_ctrl,
 734                 .ctrlbit        = (1 << 26),
 735         }, {
 736                 .name           = "ac97",
 737                 .devname        = "samsung-ac97",
 738                 .enable         = exynos5_clk_ip_peric_ctrl,
 739                 .ctrlbit        = (1 << 27),
 740         }, {
 741                 .name           = "usbhost",
 742                 .enable         = exynos5_clk_ip_fsys_ctrl ,
 743                 .ctrlbit        = (1 << 18),
 744         }, {
 745                 .name           = "usbotg",
 746                 .enable         = exynos5_clk_ip_fsys_ctrl,
 747                 .ctrlbit        = (1 << 7),
 748         }, {
 749                 .name           = "nfcon",
 750                 .enable         = exynos5_clk_ip_fsys_ctrl,
 751                 .ctrlbit        = (1 << 22),
 752         }, {
 753                 .name           = "iop",
 754                 .enable         = exynos5_clk_ip_fsys_ctrl,
 755                 .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
 756         }, {
 757                 .name           = "core_iop",
 758                 .enable         = exynos5_clk_ip_core_ctrl,
 759                 .ctrlbit        = ((1 << 21) | (1 << 3)),
 760         }, {
 761                 .name           = "mcu_iop",
 762                 .enable         = exynos5_clk_ip_fsys_ctrl,
 763                 .ctrlbit        = (1 << 0),
 764         }, {
 765                 .name           = "i2c",
 766                 .devname        = "s3c2440-i2c.0",
 767                 .parent         = &exynos5_clk_aclk_66.clk,
 768                 .enable         = exynos5_clk_ip_peric_ctrl,
 769                 .ctrlbit        = (1 << 6),
 770         }, {
 771                 .name           = "i2c",
 772                 .devname        = "s3c2440-i2c.1",
 773                 .parent         = &exynos5_clk_aclk_66.clk,
 774                 .enable         = exynos5_clk_ip_peric_ctrl,
 775                 .ctrlbit        = (1 << 7),
 776         }, {
 777                 .name           = "i2c",
 778                 .devname        = "s3c2440-i2c.2",
 779                 .parent         = &exynos5_clk_aclk_66.clk,
 780                 .enable         = exynos5_clk_ip_peric_ctrl,
 781                 .ctrlbit        = (1 << 8),
 782         }, {
 783                 .name           = "i2c",
 784                 .devname        = "s3c2440-i2c.3",
 785                 .parent         = &exynos5_clk_aclk_66.clk,
 786                 .enable         = exynos5_clk_ip_peric_ctrl,
 787                 .ctrlbit        = (1 << 9),
 788         }, {
 789                 .name           = "i2c",
 790                 .devname        = "s3c2440-i2c.4",
 791                 .parent         = &exynos5_clk_aclk_66.clk,
 792                 .enable         = exynos5_clk_ip_peric_ctrl,
 793                 .ctrlbit        = (1 << 10),
 794         }, {
 795                 .name           = "i2c",
 796                 .devname        = "s3c2440-i2c.5",
 797                 .parent         = &exynos5_clk_aclk_66.clk,
 798                 .enable         = exynos5_clk_ip_peric_ctrl,
 799                 .ctrlbit        = (1 << 11),
 800         }, {
 801                 .name           = "i2c",
 802                 .devname        = "s3c2440-i2c.6",
 803                 .parent         = &exynos5_clk_aclk_66.clk,
 804                 .enable         = exynos5_clk_ip_peric_ctrl,
 805                 .ctrlbit        = (1 << 12),
 806         }, {
 807                 .name           = "i2c",
 808                 .devname        = "s3c2440-i2c.7",
 809                 .parent         = &exynos5_clk_aclk_66.clk,
 810                 .enable         = exynos5_clk_ip_peric_ctrl,
 811                 .ctrlbit        = (1 << 13),
 812         }, {
 813                 .name           = "i2c",
 814                 .devname        = "s3c2440-hdmiphy-i2c",
 815                 .parent         = &exynos5_clk_aclk_66.clk,
 816                 .enable         = exynos5_clk_ip_peric_ctrl,
 817                 .ctrlbit        = (1 << 14),
 818         }, {
 819                 .name           = "spi",
 820                 .devname        = "exynos4210-spi.0",
 821                 .parent         = &exynos5_clk_aclk_66.clk,
 822                 .enable         = exynos5_clk_ip_peric_ctrl,
 823                 .ctrlbit        = (1 << 16),
 824         }, {
 825                 .name           = "spi",
 826                 .devname        = "exynos4210-spi.1",
 827                 .parent         = &exynos5_clk_aclk_66.clk,
 828                 .enable         = exynos5_clk_ip_peric_ctrl,
 829                 .ctrlbit        = (1 << 17),
 830         }, {
 831                 .name           = "spi",
 832                 .devname        = "exynos4210-spi.2",
 833                 .parent         = &exynos5_clk_aclk_66.clk,
 834                 .enable         = exynos5_clk_ip_peric_ctrl,
 835                 .ctrlbit        = (1 << 18),
 836         }, {
 837                 .name           = "gscl",
 838                 .devname        = "exynos-gsc.0",
 839                 .enable         = exynos5_clk_ip_gscl_ctrl,
 840                 .ctrlbit        = (1 << 0),
 841         }, {
 842                 .name           = "gscl",
 843                 .devname        = "exynos-gsc.1",
 844                 .enable         = exynos5_clk_ip_gscl_ctrl,
 845                 .ctrlbit        = (1 << 1),
 846         }, {
 847                 .name           = "gscl",
 848                 .devname        = "exynos-gsc.2",
 849                 .enable         = exynos5_clk_ip_gscl_ctrl,
 850                 .ctrlbit        = (1 << 2),
 851         }, {
 852                 .name           = "gscl",
 853                 .devname        = "exynos-gsc.3",
 854                 .enable         = exynos5_clk_ip_gscl_ctrl,
 855                 .ctrlbit        = (1 << 3),
 856         }, {
 857                 .name           = SYSMMU_CLOCK_NAME,
 858                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
 859                 .enable         = &exynos5_clk_ip_mfc_ctrl,
 860                 .ctrlbit        = (1 << 1),
 861         }, {
 862                 .name           = SYSMMU_CLOCK_NAME,
 863                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
 864                 .enable         = &exynos5_clk_ip_mfc_ctrl,
 865                 .ctrlbit        = (1 << 2),
 866         }, {
 867                 .name           = SYSMMU_CLOCK_NAME,
 868                 .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
 869                 .enable         = &exynos5_clk_ip_disp1_ctrl,
 870                 .ctrlbit        = (1 << 9)
 871         }, {
 872                 .name           = SYSMMU_CLOCK_NAME,
 873                 .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
 874                 .enable         = &exynos5_clk_ip_gen_ctrl,
 875                 .ctrlbit        = (1 << 7),
 876         }, {
 877                 .name           = SYSMMU_CLOCK_NAME,
 878                 .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
 879                 .enable         = &exynos5_clk_ip_gen_ctrl,
 880                 .ctrlbit        = (1 << 6)
 881         }, {
 882                 .name           = SYSMMU_CLOCK_NAME,
 883                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
 884                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 885                 .ctrlbit        = (1 << 7),
 886         }, {
 887                 .name           = SYSMMU_CLOCK_NAME,
 888                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
 889                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 890                 .ctrlbit        = (1 << 8),
 891         }, {
 892                 .name           = SYSMMU_CLOCK_NAME,
 893                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
 894                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 895                 .ctrlbit        = (1 << 9),
 896         }, {
 897                 .name           = SYSMMU_CLOCK_NAME,
 898                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
 899                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 900                 .ctrlbit        = (1 << 10),
 901         }, {
 902                 .name           = SYSMMU_CLOCK_NAME,
 903                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 904                 .enable         = &exynos5_clk_ip_isp0_ctrl,
 905                 .ctrlbit        = (0x3F << 8),
 906         }, {
 907                 .name           = SYSMMU_CLOCK_NAME2,
 908                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 909                 .enable         = &exynos5_clk_ip_isp1_ctrl,
 910                 .ctrlbit        = (0xF << 4),
 911         }, {
 912                 .name           = SYSMMU_CLOCK_NAME,
 913                 .devname        = SYSMMU_CLOCK_DEVNAME(camif0, 12),
 914                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 915                 .ctrlbit        = (1 << 11),
 916         }, {
 917                 .name           = SYSMMU_CLOCK_NAME,
 918                 .devname        = SYSMMU_CLOCK_DEVNAME(camif1, 13),
 919                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 920                 .ctrlbit        = (1 << 12),
 921         }, {
 922                 .name           = SYSMMU_CLOCK_NAME,
 923                 .devname        = SYSMMU_CLOCK_DEVNAME(2d, 14),
 924                 .enable         = &exynos5_clk_ip_acp_ctrl,
 925                 .ctrlbit        = (1 << 7)
 926         }
 927 };
 928
 929 static struct clk exynos5_init_clocks_on[] = {
 930         {
 931                 .name           = "uart",
 932                 .devname        = "s5pv210-uart.0",
 933                 .enable         = exynos5_clk_ip_peric_ctrl,
 934                 .ctrlbit        = (1 << 0),
 935         }, {
 936                 .name           = "uart",
 937                 .devname        = "s5pv210-uart.1",
 938                 .enable         = exynos5_clk_ip_peric_ctrl,
 939                 .ctrlbit        = (1 << 1),
 940         }, {
 941                 .name           = "uart",
 942                 .devname        = "s5pv210-uart.2",
 943                 .enable         = exynos5_clk_ip_peric_ctrl,
 944                 .ctrlbit        = (1 << 2),
 945         }, {
 946                 .name           = "uart",
 947                 .devname        = "s5pv210-uart.3",
 948                 .enable         = exynos5_clk_ip_peric_ctrl,
 949                 .ctrlbit        = (1 << 3),
 950         }, {
 951                 .name           = "uart",
 952                 .devname        = "s5pv210-uart.4",
 953                 .enable         = exynos5_clk_ip_peric_ctrl,
 954                 .ctrlbit        = (1 << 4),
 955         }, {
 956                 .name           = "uart",
 957                 .devname        = "s5pv210-uart.5",
 958                 .enable         = exynos5_clk_ip_peric_ctrl,
 959                 .ctrlbit        = (1 << 5),
 960         }
 961 };
 962
 963 static struct clk exynos5_clk_pdma0 = {
 964         .name           = "dma",
 965         .devname        = "dma-pl330.0",
 966         .enable         = exynos5_clk_ip_fsys_ctrl,
 967         .ctrlbit        = (1 << 1),
 968 };
 969
 970 static struct clk exynos5_clk_pdma1 = {
 971         .name           = "dma",
 972         .devname        = "dma-pl330.1",
 973         .enable         = exynos5_clk_ip_fsys_ctrl,
 974         .ctrlbit        = (1 << 2),
 975 };
 976
 977 static struct clk exynos5_clk_mdma1 = {
 978         .name           = "dma",
 979         .devname        = "dma-pl330.2",
 980         .enable         = exynos5_clk_ip_gen_ctrl,
 981         .ctrlbit        = (1 << 4),
 982 };
 983
 984 static struct clk exynos5_clk_fimd1 = {
 985         .name           = "fimd",
 986         .devname        = "exynos5-fb.1",
 987         .enable         = exynos5_clk_ip_disp1_ctrl,
 988         .ctrlbit        = (1 << 0),
 989 };
 990
 991 struct clk *exynos5_clkset_group_list[] = {
 992         [0] = &clk_ext_xtal_mux,
 993         [1] = NULL,
 994         [2] = &exynos5_clk_sclk_hdmi24m,
 995         [3] = &exynos5_clk_sclk_dptxphy,
 996         [4] = &exynos5_clk_sclk_usbphy,
 997         [5] = &exynos5_clk_sclk_hdmiphy,
 998         [6] = &exynos5_clk_mout_mpll_user.clk,
 999         [7] = &exynos5_clk_mout_epll.clk,
1000         [8] = &exynos5_clk_sclk_vpll.clk,
1001         [9] = &exynos5_clk_mout_cpll.clk,
1002 };
1003
1004 struct clksrc_sources exynos5_clkset_group = {
1005         .sources        = exynos5_clkset_group_list,
1006         .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
1007 };
1008
1009 /* Possible clock sources for aclk_266_gscl_sub Mux */
1010 static struct clk *clk_src_gscl_266_list[] = {
1011         [0] = &clk_ext_xtal_mux,
1012         [1] = &exynos5_clk_aclk_266.clk,
1013 };
1014
1015 static struct clksrc_sources clk_src_gscl_266 = {
1016         .sources        = clk_src_gscl_266_list,
1017         .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
1018 };
1019
1020 static struct clksrc_clk exynos5_clk_dout_mmc0 = {
1021         .clk            = {
1022                 .name           = "dout_mmc0",
1023         },
1024         .sources = &exynos5_clkset_group,
1025         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
1026         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
1027 };
1028
1029 static struct clksrc_clk exynos5_clk_dout_mmc1 = {
1030         .clk            = {
1031                 .name           = "dout_mmc1",
1032         },
1033         .sources = &exynos5_clkset_group,
1034         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
1035         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1036 };
1037
1038 static struct clksrc_clk exynos5_clk_dout_mmc2 = {
1039         .clk            = {
1040                 .name           = "dout_mmc2",
1041         },
1042         .sources = &exynos5_clkset_group,
1043         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
1044         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1045 };
1046
1047 static struct clksrc_clk exynos5_clk_dout_mmc3 = {
1048         .clk            = {
1049                 .name           = "dout_mmc3",
1050         },
1051         .sources = &exynos5_clkset_group,
1052         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
1053         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1054 };
1055
1056 static struct clksrc_clk exynos5_clk_dout_mmc4 = {
1057         .clk            = {
1058                 .name           = "dout_mmc4",
1059         },
1060         .sources = &exynos5_clkset_group,
1061         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
1062         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1063 };
1064
1065 static struct clksrc_clk exynos5_clk_sclk_uart0 = {
1066         .clk    = {
1067                 .name           = "uclk1",
1068                 .devname        = "exynos4210-uart.0",
1069                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1070                 .ctrlbit        = (1 << 0),
1071         },
1072         .sources = &exynos5_clkset_group,
1073         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
1074         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
1075 };
1076
1077 static struct clksrc_clk exynos5_clk_sclk_uart1 = {
1078         .clk    = {
1079                 .name           = "uclk1",
1080                 .devname        = "exynos4210-uart.1",
1081                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1082                 .ctrlbit        = (1 << 4),
1083         },
1084         .sources = &exynos5_clkset_group,
1085         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
1086         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
1087 };
1088
1089 static struct clksrc_clk exynos5_clk_sclk_uart2 = {
1090         .clk    = {
1091                 .name           = "uclk1",
1092                 .devname        = "exynos4210-uart.2",
1093                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1094                 .ctrlbit        = (1 << 8),
1095         },
1096         .sources = &exynos5_clkset_group,
1097         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
1098         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
1099 };
1100
1101 static struct clksrc_clk exynos5_clk_sclk_uart3 = {
1102         .clk    = {
1103                 .name           = "uclk1",
1104                 .devname        = "exynos4210-uart.3",
1105                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1106                 .ctrlbit        = (1 << 12),
1107         },
1108         .sources = &exynos5_clkset_group,
1109         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
1110         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
1111 };
1112
1113 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
1114         .clk    = {
1115                 .name           = "ciu",        /* card interface unit clock */
1116                 .devname        = "dw_mmc.0",
1117                 .parent         = &exynos5_clk_dout_mmc0.clk,
1118                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1119                 .ctrlbit        = (1 << 0),
1120         },
1121         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1122 };
1123
1124 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
1125         .clk    = {
1126                 .name           = "ciu",
1127                 .devname        = "dw_mmc.1",
1128                 .parent         = &exynos5_clk_dout_mmc1.clk,
1129                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1130                 .ctrlbit        = (1 << 4),
1131         },
1132         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1133 };
1134
1135 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
1136         .clk    = {
1137                 .name           = "ciu",
1138                 .devname        = "dw_mmc.2",
1139                 .parent         = &exynos5_clk_dout_mmc2.clk,
1140                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1141                 .ctrlbit        = (1 << 8),
1142         },
1143         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1144 };
1145
1146 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1147         .clk    = {
1148                 .name           = "ciu",
1149                 .devname        = "dw_mmc.3",
1150                 .parent         = &exynos5_clk_dout_mmc3.clk,
1151                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1152                 .ctrlbit        = (1 << 12),
1153         },
1154         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1155 };
1156
1157 static struct clksrc_clk exynos5_clk_mdout_spi0 = {
1158         .clk    = {
1159                 .name           = "mdout_spi",
1160                 .devname        = "exynos4210-spi.0",
1161         },
1162         .sources = &exynos5_clkset_group,
1163         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
1164         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
1165 };
1166
1167 static struct clksrc_clk exynos5_clk_mdout_spi1 = {
1168         .clk    = {
1169                 .name           = "mdout_spi",
1170                 .devname        = "exynos4210-spi.1",
1171         },
1172         .sources = &exynos5_clkset_group,
1173         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
1174         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
1175 };
1176
1177 static struct clksrc_clk exynos5_clk_mdout_spi2 = {
1178         .clk    = {
1179                 .name           = "mdout_spi",
1180                 .devname        = "exynos4210-spi.2",
1181         },
1182         .sources = &exynos5_clkset_group,
1183         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
1184         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
1185 };
1186
1187 static struct clksrc_clk exynos5_clk_sclk_spi0 = {
1188         .clk    = {
1189                 .name           = "sclk_spi",
1190                 .devname        = "exynos4210-spi.0",
1191                 .parent         = &exynos5_clk_mdout_spi0.clk,
1192                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1193                 .ctrlbit        = (1 << 16),
1194         },
1195         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
1196 };
1197
1198 static struct clksrc_clk exynos5_clk_sclk_spi1 = {
1199         .clk    = {
1200                 .name           = "sclk_spi",
1201                 .devname        = "exynos4210-spi.1",
1202                 .parent         = &exynos5_clk_mdout_spi1.clk,
1203                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1204                 .ctrlbit        = (1 << 20),
1205         },
1206         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
1207 };
1208
1209 static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1210         .clk    = {
1211                 .name           = "sclk_spi",
1212                 .devname        = "exynos4210-spi.2",
1213                 .parent         = &exynos5_clk_mdout_spi2.clk,
1214                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1215                 .ctrlbit        = (1 << 24),
1216         },
1217         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1218 };
1219
1220 struct clksrc_clk exynos5_clk_sclk_fimd1 = {
1221         .clk    = {
1222                 .name           = "sclk_fimd",
1223                 .devname        = "exynos5-fb.1",
1224                 .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
1225                 .ctrlbit        = (1 << 0),
1226         },
1227         .sources = &exynos5_clkset_group,
1228         .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1229         .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1230 };
1231
1232 static struct clksrc_clk exynos5_clksrcs[] = {
1233         {
1234                 .clk    = {
1235                         .name           = "aclk_266_gscl",
1236                 },
1237                 .sources = &clk_src_gscl_266,
1238                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1239         }, {
1240                 .clk    = {
1241                         .name           = "sclk_g3d",
1242                         .devname        = "mali-t604.0",
1243                         .enable         = exynos5_clk_block_ctrl,
1244                         .ctrlbit        = (1 << 1),
1245                 },
1246                 .sources = &exynos5_clkset_aclk,
1247                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1248                 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1249         }, {
1250                 .clk    = {
1251                         .name           = "sclk_sata",
1252                         .devname        = "exynos5-sata",
1253                         .enable         = exynos5_clksrc_mask_fsys_ctrl,
1254                         .ctrlbit        = (1 << 24),
1255                 },
1256                 .sources = &exynos5_clkset_aclk,
1257                 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
1258                 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
1259         }, {
1260                 .clk    = {
1261                         .name           = "sclk_gscl_wrap",
1262                         .devname        = "s5p-mipi-csis.0",
1263                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1264                         .ctrlbit        = (1 << 24),
1265                 },
1266                 .sources = &exynos5_clkset_group,
1267                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1268                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1269         }, {
1270                 .clk    = {
1271                         .name           = "sclk_gscl_wrap",
1272                         .devname        = "s5p-mipi-csis.1",
1273                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1274                         .ctrlbit        = (1 << 28),
1275                 },
1276                 .sources = &exynos5_clkset_group,
1277                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1278                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1279         }, {
1280                 .clk    = {
1281                         .name           = "sclk_cam0",
1282                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1283                         .ctrlbit        = (1 << 16),
1284                 },
1285                 .sources = &exynos5_clkset_group,
1286                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1287                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1288         }, {
1289                 .clk    = {
1290                         .name           = "sclk_cam1",
1291                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1292                         .ctrlbit        = (1 << 20),
1293                 },
1294                 .sources = &exynos5_clkset_group,
1295                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1296                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1297         }, {
1298                 .clk    = {
1299                         .name           = "sclk_jpeg",
1300                         .parent         = &exynos5_clk_mout_cpll.clk,
1301                 },
1302                 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1303         },
1304 };
1305
1306 /* Clock initialization code */
1307 static struct clksrc_clk *exynos5_sysclks[] = {
1308         &exynos5_clk_mout_apll,
1309         &exynos5_clk_sclk_apll,
1310         &exynos5_clk_mout_bpll,
1311         &exynos5_clk_mout_bpll_fout,
1312         &exynos5_clk_mout_bpll_user,
1313         &exynos5_clk_mout_cpll,
1314         &exynos5_clk_mout_epll,
1315         &exynos5_clk_mout_mpll,
1316         &exynos5_clk_mout_mpll_fout,
1317         &exynos5_clk_mout_mpll_user,
1318         &exynos5_clk_vpllsrc,
1319         &exynos5_clk_sclk_vpll,
1320         &exynos5_clk_mout_cpu,
1321         &exynos5_clk_dout_armclk,
1322         &exynos5_clk_dout_arm2clk,
1323         &exynos5_clk_cdrex,
1324         &exynos5_clk_aclk_400,
1325         &exynos5_clk_aclk_333,
1326         &exynos5_clk_aclk_266,
1327         &exynos5_clk_aclk_200,
1328         &exynos5_clk_aclk_166,
1329         &exynos5_clk_aclk_300_gscl,
1330         &exynos5_clk_mout_aclk_300_gscl,
1331         &exynos5_clk_mout_aclk_300_gscl_mid,
1332         &exynos5_clk_mout_aclk_300_gscl_mid1,
1333         &exynos5_clk_aclk_66_pre,
1334         &exynos5_clk_aclk_66,
1335         &exynos5_clk_dout_mmc0,
1336         &exynos5_clk_dout_mmc1,
1337         &exynos5_clk_dout_mmc2,
1338         &exynos5_clk_dout_mmc3,
1339         &exynos5_clk_dout_mmc4,
1340         &exynos5_clk_aclk_acp,
1341         &exynos5_clk_pclk_acp,
1342         &exynos5_clk_sclk_spi0,
1343         &exynos5_clk_sclk_spi1,
1344         &exynos5_clk_sclk_spi2,
1345         &exynos5_clk_mdout_spi0,
1346         &exynos5_clk_mdout_spi1,
1347         &exynos5_clk_mdout_spi2,
1348         &exynos5_clk_sclk_fimd1,
1349 };
1350
1351 static struct clk *exynos5_clk_cdev[] = {
1352         &exynos5_clk_pdma0,
1353         &exynos5_clk_pdma1,
1354         &exynos5_clk_mdma1,
1355         &exynos5_clk_fimd1,
1356 };
1357
1358 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1359         &exynos5_clk_sclk_uart0,
1360         &exynos5_clk_sclk_uart1,
1361         &exynos5_clk_sclk_uart2,
1362         &exynos5_clk_sclk_uart3,
1363         &exynos5_clk_sclk_mmc0,
1364         &exynos5_clk_sclk_mmc1,
1365         &exynos5_clk_sclk_mmc2,
1366         &exynos5_clk_sclk_mmc3,
1367 };
1368
1369 static struct clk_lookup exynos5_clk_lookup[] = {
1370         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1371         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1372         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1373         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1374         CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1375         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1376         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1377         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1378         CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
1379         CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
1380         CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
1381         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1382         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1383         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1384         CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
1385 };
1386
1387 static unsigned long exynos5_epll_get_rate(struct clk *clk)
1388 {
1389         return clk->rate;
1390 }
1391
1392 static struct clk *exynos5_clks[] __initdata = {
1393         &exynos5_clk_sclk_hdmi27m,
1394         &exynos5_clk_sclk_hdmiphy,
1395         &clk_fout_bpll,
1396         &clk_fout_bpll_div2,
1397         &clk_fout_cpll,
1398         &clk_fout_mpll_div2,
1399         &exynos5_clk_armclk,
1400 };
1401
1402 static u32 epll_div[][6] = {
1403         { 192000000, 0, 48, 3, 1, 0 },
1404         { 180000000, 0, 45, 3, 1, 0 },
1405         {  73728000, 1, 73, 3, 3, 47710 },
1406         {  67737600, 1, 90, 4, 3, 20762 },
1407         {  49152000, 0, 49, 3, 3, 9961 },
1408         {  45158400, 0, 45, 3, 3, 10381 },
1409         { 180633600, 0, 45, 3, 1, 10381 },
1410 };
1411
1412 static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1413 {
1414         unsigned int epll_con, epll_con_k;
1415         unsigned int i;
1416         unsigned int tmp;
1417         unsigned int epll_rate;
1418         unsigned int locktime;
1419         unsigned int lockcnt;
1420
1421         /* Return if nothing changed */
1422         if (clk->rate == rate)
1423                 return 0;
1424
1425         if (clk->parent)
1426                 epll_rate = clk_get_rate(clk->parent);
1427         else
1428                 epll_rate = clk_ext_xtal_mux.rate;
1429
1430         if (epll_rate != 24000000) {
1431                 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1432                 return -EINVAL;
1433         }
1434
1435         epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1436         epll_con &= ~(0x1 << 27 | \
1437                         PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
1438                         PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1439                         PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1440
1441         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1442                 if (epll_div[i][0] == rate) {
1443                         epll_con_k = epll_div[i][5] << 0;
1444                         epll_con |= epll_div[i][1] << 27;
1445                         epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1446                         epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1447                         epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1448                         break;
1449                 }
1450         }
1451
1452         if (i == ARRAY_SIZE(epll_div)) {
1453                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1454                                 __func__);
1455                 return -EINVAL;
1456         }
1457
1458         epll_rate /= 1000000;
1459
1460         /* 3000 max_cycls : specification data */
1461         locktime = 3000 / epll_rate * epll_div[i][3];
1462         lockcnt = locktime * 10000 / (10000 / epll_rate);
1463
1464         __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1465
1466         __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1467         __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1468
1469         do {
1470                 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1471         } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1472
1473         clk->rate = rate;
1474
1475         return 0;
1476 }
1477
1478 static struct clk_ops exynos5_epll_ops = {
1479         .get_rate = exynos5_epll_get_rate,
1480         .set_rate = exynos5_epll_set_rate,
1481 };
1482
1483 static int xtal_rate;
1484
1485 static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1486 {
1487         return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1488 }
1489
1490 static struct clk_ops exynos5_fout_apll_ops = {
1491         .get_rate = exynos5_fout_apll_get_rate,
1492 };
1493
1494 #ifdef CONFIG_PM
1495 static int exynos5_clock_suspend(void)
1496 {
1497         s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1498
1499         return 0;
1500 }
1501
1502 static void exynos5_clock_resume(void)
1503 {
1504         s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1505 }
1506 #else
1507 #define exynos5_clock_suspend NULL
1508 #define exynos5_clock_resume NULL
1509 #endif
1510
1511 struct syscore_ops exynos5_clock_syscore_ops = {
1512         .suspend        = exynos5_clock_suspend,
1513         .resume         = exynos5_clock_resume,
1514 };
1515
1516 void __init_or_cpufreq exynos5_setup_clocks(void)
1517 {
1518         struct clk *xtal_clk;
1519         unsigned long apll;
1520         unsigned long bpll;
1521         unsigned long cpll;
1522         unsigned long mpll;
1523         unsigned long epll;
1524         unsigned long vpll;
1525         unsigned long vpllsrc;
1526         unsigned long xtal;
1527         unsigned long armclk;
1528         unsigned long mout_cdrex;
1529         unsigned long aclk_400;
1530         unsigned long aclk_333;
1531         unsigned long aclk_266;
1532         unsigned long aclk_200;
1533         unsigned long aclk_166;
1534         unsigned long aclk_66;
1535         unsigned int ptr;
1536
1537         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1538
1539         xtal_clk = clk_get(NULL, "xtal");
1540         BUG_ON(IS_ERR(xtal_clk));
1541
1542         xtal = clk_get_rate(xtal_clk);
1543
1544         xtal_rate = xtal;
1545
1546         clk_put(xtal_clk);
1547
1548         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1549
1550         apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1551         bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1552         cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1553         mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1554         epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1555                         __raw_readl(EXYNOS5_EPLL_CON1));
1556
1557         vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1558         vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1559                         __raw_readl(EXYNOS5_VPLL_CON1));
1560
1561         clk_fout_apll.ops = &exynos5_fout_apll_ops;
1562         clk_fout_bpll.rate = bpll;
1563         clk_fout_bpll_div2.rate = bpll >> 1;
1564         clk_fout_cpll.rate = cpll;
1565         clk_fout_mpll.rate = mpll;
1566         clk_fout_mpll_div2.rate = mpll >> 1;
1567         clk_fout_epll.rate = epll;
1568         clk_fout_vpll.rate = vpll;
1569
1570         printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1571                         "M=%ld, E=%ld V=%ld",
1572                         apll, bpll, cpll, mpll, epll, vpll);
1573
1574         armclk = clk_get_rate(&exynos5_clk_armclk);
1575         mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1576
1577         aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1578         aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1579         aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1580         aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1581         aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1582         aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1583
1584         printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1585                         "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1586                         "ACLK166=%ld, ACLK66=%ld\n",
1587                         armclk, mout_cdrex, aclk_400,
1588                         aclk_333, aclk_266, aclk_200,
1589                         aclk_166, aclk_66);
1590
1591
1592         clk_fout_epll.ops = &exynos5_epll_ops;
1593
1594         if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1595                 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1596                                 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1597
1598         clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1599         clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1600
1601         clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1602         clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1603
1604         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1605                 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1606 }
1607
1608 void __init exynos5_register_clocks(void)
1609 {
1610         int ptr;
1611
1612         s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1613
1614         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1615                 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1616
1617         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1618                 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1619
1620         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1621                 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1622
1623         s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1624         s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1625
1626         s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1627         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1628                 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1629
1630         s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1631         s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1632         clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1633
1634         register_syscore_ops(&exynos5_clock_syscore_ops);
1635         s3c_pwmclk_init();
1636 }