1 /* linux/arch/arm/mach-exynos4/clock.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/err.h>
16 #include <linux/syscore_ops.h>
18 #include <plat/cpu-freq.h>
19 #include <plat/clock.h>
22 #include <plat/s5p-clock.h>
23 #include <plat/clock-clksrc.h>
24 #include <plat/exynos4.h>
28 #include <mach/regs-clock.h>
29 #include <mach/sysmmu.h>
30 #include <mach/exynos4-clock.h>
32 static struct sleep_save exynos4_clock_save[] = {
33 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
34 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
35 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
36 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
37 SAVE_ITEM(S5P_CLKSRC_TOP0),
38 SAVE_ITEM(S5P_CLKSRC_TOP1),
39 SAVE_ITEM(S5P_CLKSRC_CAM),
40 SAVE_ITEM(S5P_CLKSRC_TV),
41 SAVE_ITEM(S5P_CLKSRC_MFC),
42 SAVE_ITEM(S5P_CLKSRC_G3D),
43 SAVE_ITEM(S5P_CLKSRC_LCD0),
44 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
45 SAVE_ITEM(S5P_CLKSRC_FSYS),
46 SAVE_ITEM(S5P_CLKSRC_PERIL0),
47 SAVE_ITEM(S5P_CLKSRC_PERIL1),
48 SAVE_ITEM(S5P_CLKDIV_CAM),
49 SAVE_ITEM(S5P_CLKDIV_TV),
50 SAVE_ITEM(S5P_CLKDIV_MFC),
51 SAVE_ITEM(S5P_CLKDIV_G3D),
52 SAVE_ITEM(S5P_CLKDIV_LCD0),
53 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
54 SAVE_ITEM(S5P_CLKDIV_FSYS0),
55 SAVE_ITEM(S5P_CLKDIV_FSYS1),
56 SAVE_ITEM(S5P_CLKDIV_FSYS2),
57 SAVE_ITEM(S5P_CLKDIV_FSYS3),
58 SAVE_ITEM(S5P_CLKDIV_PERIL0),
59 SAVE_ITEM(S5P_CLKDIV_PERIL1),
60 SAVE_ITEM(S5P_CLKDIV_PERIL2),
61 SAVE_ITEM(S5P_CLKDIV_PERIL3),
62 SAVE_ITEM(S5P_CLKDIV_PERIL4),
63 SAVE_ITEM(S5P_CLKDIV_PERIL5),
64 SAVE_ITEM(S5P_CLKDIV_TOP),
65 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
66 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
67 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
68 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
69 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
70 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
71 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
72 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
73 SAVE_ITEM(S5P_CLKDIV2_RATIO),
74 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
75 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
76 SAVE_ITEM(S5P_CLKGATE_IP_TV),
77 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
78 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
79 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
80 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
81 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
82 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
83 SAVE_ITEM(S5P_CLKGATE_BLOCK),
84 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
85 SAVE_ITEM(S5P_CLKSRC_DMC),
86 SAVE_ITEM(S5P_CLKDIV_DMC0),
87 SAVE_ITEM(S5P_CLKDIV_DMC1),
88 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
89 SAVE_ITEM(S5P_CLKSRC_CPU),
90 SAVE_ITEM(S5P_CLKDIV_CPU),
91 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
92 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
93 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
96 struct clk clk_sclk_hdmi27m = {
97 .name = "sclk_hdmi27m",
101 struct clk clk_sclk_hdmiphy = {
102 .name = "sclk_hdmiphy",
105 struct clk clk_sclk_usbphy0 = {
106 .name = "sclk_usbphy0",
110 struct clk clk_sclk_usbphy1 = {
111 .name = "sclk_usbphy1",
114 static struct clk dummy_apb_pclk = {
119 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
121 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
124 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
126 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
129 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
131 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
134 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
136 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
139 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
141 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
144 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
146 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
149 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
151 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
154 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
156 return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
159 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
161 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
164 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
166 return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
169 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
171 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
174 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
176 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
179 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
181 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
184 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
186 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
189 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
191 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
194 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
196 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
199 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
201 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
204 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
206 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
209 /* Core list of CMU_CPU side */
211 static struct clksrc_clk clk_mout_apll = {
215 .sources = &clk_src_apll,
216 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
219 struct clksrc_clk clk_sclk_apll = {
222 .parent = &clk_mout_apll.clk,
224 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
227 struct clksrc_clk clk_mout_epll = {
231 .sources = &clk_src_epll,
232 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
235 struct clksrc_clk clk_mout_mpll = {
239 .sources = &clk_src_mpll,
241 /* reg_src will be added in each SoCs' clock */
244 static struct clk *clkset_moutcore_list[] = {
245 [0] = &clk_mout_apll.clk,
246 [1] = &clk_mout_mpll.clk,
249 static struct clksrc_sources clkset_moutcore = {
250 .sources = clkset_moutcore_list,
251 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
254 static struct clksrc_clk clk_moutcore = {
258 .sources = &clkset_moutcore,
259 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
262 static struct clksrc_clk clk_coreclk = {
265 .parent = &clk_moutcore.clk,
267 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
270 static struct clksrc_clk clk_armclk = {
273 .parent = &clk_coreclk.clk,
277 static struct clksrc_clk clk_aclk_corem0 = {
279 .name = "aclk_corem0",
280 .parent = &clk_coreclk.clk,
282 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
285 static struct clksrc_clk clk_aclk_cores = {
287 .name = "aclk_cores",
288 .parent = &clk_coreclk.clk,
290 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
293 static struct clksrc_clk clk_aclk_corem1 = {
295 .name = "aclk_corem1",
296 .parent = &clk_coreclk.clk,
298 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
301 static struct clksrc_clk clk_periphclk = {
304 .parent = &clk_coreclk.clk,
306 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
309 /* Core list of CMU_CORE side */
311 struct clk *clkset_corebus_list[] = {
312 [0] = &clk_mout_mpll.clk,
313 [1] = &clk_sclk_apll.clk,
316 struct clksrc_sources clkset_mout_corebus = {
317 .sources = clkset_corebus_list,
318 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
321 static struct clksrc_clk clk_mout_corebus = {
323 .name = "mout_corebus",
325 .sources = &clkset_mout_corebus,
326 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
329 static struct clksrc_clk clk_sclk_dmc = {
332 .parent = &clk_mout_corebus.clk,
334 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
337 static struct clksrc_clk clk_aclk_cored = {
339 .name = "aclk_cored",
340 .parent = &clk_sclk_dmc.clk,
342 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
345 static struct clksrc_clk clk_aclk_corep = {
347 .name = "aclk_corep",
348 .parent = &clk_aclk_cored.clk,
350 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
353 static struct clksrc_clk clk_aclk_acp = {
356 .parent = &clk_mout_corebus.clk,
358 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
361 static struct clksrc_clk clk_pclk_acp = {
364 .parent = &clk_aclk_acp.clk,
366 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
369 /* Core list of CMU_TOP side */
371 struct clk *clkset_aclk_top_list[] = {
372 [0] = &clk_mout_mpll.clk,
373 [1] = &clk_sclk_apll.clk,
376 struct clksrc_sources clkset_aclk = {
377 .sources = clkset_aclk_top_list,
378 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
381 static struct clksrc_clk clk_aclk_200 = {
385 .sources = &clkset_aclk,
386 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
387 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
390 static struct clksrc_clk clk_aclk_100 = {
394 .sources = &clkset_aclk,
395 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
396 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
399 static struct clksrc_clk clk_aclk_160 = {
403 .sources = &clkset_aclk,
404 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
405 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
408 struct clksrc_clk clk_aclk_133 = {
412 .sources = &clkset_aclk,
413 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
414 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
417 static struct clk *clkset_vpllsrc_list[] = {
419 [1] = &clk_sclk_hdmi27m,
422 static struct clksrc_sources clkset_vpllsrc = {
423 .sources = clkset_vpllsrc_list,
424 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
427 static struct clksrc_clk clk_vpllsrc = {
430 .enable = exynos4_clksrc_mask_top_ctrl,
433 .sources = &clkset_vpllsrc,
434 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
437 static struct clk *clkset_sclk_vpll_list[] = {
438 [0] = &clk_vpllsrc.clk,
439 [1] = &clk_fout_vpll,
442 static struct clksrc_sources clkset_sclk_vpll = {
443 .sources = clkset_sclk_vpll_list,
444 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
447 struct clksrc_clk clk_sclk_vpll = {
451 .sources = &clkset_sclk_vpll,
452 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
455 static struct clk init_clocks_off[] = {
458 .parent = &clk_aclk_100.clk,
459 .enable = exynos4_clk_ip_peril_ctrl,
463 .devname = "s5p-mipi-csis.0",
464 .enable = exynos4_clk_ip_cam_ctrl,
468 .devname = "s5p-mipi-csis.1",
469 .enable = exynos4_clk_ip_cam_ctrl,
473 .devname = "exynos4-fimc.0",
474 .enable = exynos4_clk_ip_cam_ctrl,
478 .devname = "exynos4-fimc.1",
479 .enable = exynos4_clk_ip_cam_ctrl,
483 .devname = "exynos4-fimc.2",
484 .enable = exynos4_clk_ip_cam_ctrl,
488 .devname = "exynos4-fimc.3",
489 .enable = exynos4_clk_ip_cam_ctrl,
493 .devname = "exynos4-fb.0",
494 .enable = exynos4_clk_ip_lcd0_ctrl,
498 .devname = "s3c-sdhci.0",
499 .parent = &clk_aclk_133.clk,
500 .enable = exynos4_clk_ip_fsys_ctrl,
504 .devname = "s3c-sdhci.1",
505 .parent = &clk_aclk_133.clk,
506 .enable = exynos4_clk_ip_fsys_ctrl,
510 .devname = "s3c-sdhci.2",
511 .parent = &clk_aclk_133.clk,
512 .enable = exynos4_clk_ip_fsys_ctrl,
516 .devname = "s3c-sdhci.3",
517 .parent = &clk_aclk_133.clk,
518 .enable = exynos4_clk_ip_fsys_ctrl,
522 .parent = &clk_aclk_133.clk,
523 .enable = exynos4_clk_ip_fsys_ctrl,
527 .devname = "s5p-sdo",
528 .enable = exynos4_clk_ip_tv_ctrl,
532 .devname = "s5p-mixer",
533 .enable = exynos4_clk_ip_tv_ctrl,
537 .devname = "s5p-mixer",
538 .enable = exynos4_clk_ip_tv_ctrl,
542 .devname = "exynos4-hdmi",
543 .enable = exynos4_clk_ip_tv_ctrl,
547 .devname = "exynos4-hdmi",
548 .enable = exynos4_clk_hdmiphy_ctrl,
552 .devname = "s5p-sdo",
553 .enable = exynos4_clk_dac_ctrl,
557 .enable = exynos4_clk_ip_peril_ctrl,
558 .ctrlbit = (1 << 15),
561 .enable = exynos4_clk_ip_perir_ctrl,
562 .ctrlbit = (1 << 16),
565 .enable = exynos4_clk_ip_perir_ctrl,
566 .ctrlbit = (1 << 15),
569 .parent = &clk_aclk_100.clk,
570 .enable = exynos4_clk_ip_perir_ctrl,
571 .ctrlbit = (1 << 14),
574 .enable = exynos4_clk_ip_fsys_ctrl ,
575 .ctrlbit = (1 << 12),
578 .enable = exynos4_clk_ip_fsys_ctrl,
579 .ctrlbit = (1 << 13),
582 .devname = "s3c64xx-spi.0",
583 .enable = exynos4_clk_ip_peril_ctrl,
584 .ctrlbit = (1 << 16),
587 .devname = "s3c64xx-spi.1",
588 .enable = exynos4_clk_ip_peril_ctrl,
589 .ctrlbit = (1 << 17),
592 .devname = "s3c64xx-spi.2",
593 .enable = exynos4_clk_ip_peril_ctrl,
594 .ctrlbit = (1 << 18),
597 .devname = "samsung-i2s.0",
598 .enable = exynos4_clk_ip_peril_ctrl,
599 .ctrlbit = (1 << 19),
602 .devname = "samsung-i2s.1",
603 .enable = exynos4_clk_ip_peril_ctrl,
604 .ctrlbit = (1 << 20),
607 .devname = "samsung-i2s.2",
608 .enable = exynos4_clk_ip_peril_ctrl,
609 .ctrlbit = (1 << 21),
612 .devname = "samsung-ac97",
613 .enable = exynos4_clk_ip_peril_ctrl,
614 .ctrlbit = (1 << 27),
617 .enable = exynos4_clk_ip_image_ctrl,
621 .devname = "s5p-mfc",
622 .enable = exynos4_clk_ip_mfc_ctrl,
626 .devname = "s3c2440-i2c.0",
627 .parent = &clk_aclk_100.clk,
628 .enable = exynos4_clk_ip_peril_ctrl,
632 .devname = "s3c2440-i2c.1",
633 .parent = &clk_aclk_100.clk,
634 .enable = exynos4_clk_ip_peril_ctrl,
638 .devname = "s3c2440-i2c.2",
639 .parent = &clk_aclk_100.clk,
640 .enable = exynos4_clk_ip_peril_ctrl,
644 .devname = "s3c2440-i2c.3",
645 .parent = &clk_aclk_100.clk,
646 .enable = exynos4_clk_ip_peril_ctrl,
650 .devname = "s3c2440-i2c.4",
651 .parent = &clk_aclk_100.clk,
652 .enable = exynos4_clk_ip_peril_ctrl,
653 .ctrlbit = (1 << 10),
656 .devname = "s3c2440-i2c.5",
657 .parent = &clk_aclk_100.clk,
658 .enable = exynos4_clk_ip_peril_ctrl,
659 .ctrlbit = (1 << 11),
662 .devname = "s3c2440-i2c.6",
663 .parent = &clk_aclk_100.clk,
664 .enable = exynos4_clk_ip_peril_ctrl,
665 .ctrlbit = (1 << 12),
668 .devname = "s3c2440-i2c.7",
669 .parent = &clk_aclk_100.clk,
670 .enable = exynos4_clk_ip_peril_ctrl,
671 .ctrlbit = (1 << 13),
674 .devname = "s3c2440-hdmiphy-i2c",
675 .parent = &clk_aclk_100.clk,
676 .enable = exynos4_clk_ip_peril_ctrl,
677 .ctrlbit = (1 << 14),
679 .name = "SYSMMU_MDMA",
680 .enable = exynos4_clk_ip_image_ctrl,
683 .name = "SYSMMU_FIMC0",
684 .enable = exynos4_clk_ip_cam_ctrl,
687 .name = "SYSMMU_FIMC1",
688 .enable = exynos4_clk_ip_cam_ctrl,
691 .name = "SYSMMU_FIMC2",
692 .enable = exynos4_clk_ip_cam_ctrl,
695 .name = "SYSMMU_FIMC3",
696 .enable = exynos4_clk_ip_cam_ctrl,
697 .ctrlbit = (1 << 10),
699 .name = "SYSMMU_JPEG",
700 .enable = exynos4_clk_ip_cam_ctrl,
701 .ctrlbit = (1 << 11),
703 .name = "SYSMMU_FIMD0",
704 .enable = exynos4_clk_ip_lcd0_ctrl,
707 .name = "SYSMMU_FIMD1",
708 .enable = exynos4_clk_ip_lcd1_ctrl,
711 .name = "SYSMMU_PCIe",
712 .enable = exynos4_clk_ip_fsys_ctrl,
713 .ctrlbit = (1 << 18),
715 .name = "SYSMMU_G2D",
716 .enable = exynos4_clk_ip_image_ctrl,
719 .name = "SYSMMU_ROTATOR",
720 .enable = exynos4_clk_ip_image_ctrl,
724 .enable = exynos4_clk_ip_tv_ctrl,
727 .name = "SYSMMU_MFC_L",
728 .enable = exynos4_clk_ip_mfc_ctrl,
731 .name = "SYSMMU_MFC_R",
732 .enable = exynos4_clk_ip_mfc_ctrl,
737 static struct clk init_clocks[] = {
740 .devname = "s5pv210-uart.0",
741 .enable = exynos4_clk_ip_peril_ctrl,
745 .devname = "s5pv210-uart.1",
746 .enable = exynos4_clk_ip_peril_ctrl,
750 .devname = "s5pv210-uart.2",
751 .enable = exynos4_clk_ip_peril_ctrl,
755 .devname = "s5pv210-uart.3",
756 .enable = exynos4_clk_ip_peril_ctrl,
760 .devname = "s5pv210-uart.4",
761 .enable = exynos4_clk_ip_peril_ctrl,
765 .devname = "s5pv210-uart.5",
766 .enable = exynos4_clk_ip_peril_ctrl,
771 static struct clk clk_pdma0 = {
773 .devname = "dma-pl330.0",
774 .enable = exynos4_clk_ip_fsys_ctrl,
778 static struct clk clk_pdma1 = {
780 .devname = "dma-pl330.1",
781 .enable = exynos4_clk_ip_fsys_ctrl,
785 struct clk *clkset_group_list[] = {
786 [0] = &clk_ext_xtal_mux,
788 [2] = &clk_sclk_hdmi27m,
789 [3] = &clk_sclk_usbphy0,
790 [4] = &clk_sclk_usbphy1,
791 [5] = &clk_sclk_hdmiphy,
792 [6] = &clk_mout_mpll.clk,
793 [7] = &clk_mout_epll.clk,
794 [8] = &clk_sclk_vpll.clk,
797 struct clksrc_sources clkset_group = {
798 .sources = clkset_group_list,
799 .nr_sources = ARRAY_SIZE(clkset_group_list),
802 static struct clk *clkset_mout_g2d0_list[] = {
803 [0] = &clk_mout_mpll.clk,
804 [1] = &clk_sclk_apll.clk,
807 static struct clksrc_sources clkset_mout_g2d0 = {
808 .sources = clkset_mout_g2d0_list,
809 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
812 static struct clksrc_clk clk_mout_g2d0 = {
816 .sources = &clkset_mout_g2d0,
817 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
820 static struct clk *clkset_mout_g2d1_list[] = {
821 [0] = &clk_mout_epll.clk,
822 [1] = &clk_sclk_vpll.clk,
825 static struct clksrc_sources clkset_mout_g2d1 = {
826 .sources = clkset_mout_g2d1_list,
827 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
830 static struct clksrc_clk clk_mout_g2d1 = {
834 .sources = &clkset_mout_g2d1,
835 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
838 static struct clk *clkset_mout_g2d_list[] = {
839 [0] = &clk_mout_g2d0.clk,
840 [1] = &clk_mout_g2d1.clk,
843 static struct clksrc_sources clkset_mout_g2d = {
844 .sources = clkset_mout_g2d_list,
845 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
848 static struct clk *clkset_mout_mfc0_list[] = {
849 [0] = &clk_mout_mpll.clk,
850 [1] = &clk_sclk_apll.clk,
853 static struct clksrc_sources clkset_mout_mfc0 = {
854 .sources = clkset_mout_mfc0_list,
855 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
858 static struct clksrc_clk clk_mout_mfc0 = {
862 .sources = &clkset_mout_mfc0,
863 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
866 static struct clk *clkset_mout_mfc1_list[] = {
867 [0] = &clk_mout_epll.clk,
868 [1] = &clk_sclk_vpll.clk,
871 static struct clksrc_sources clkset_mout_mfc1 = {
872 .sources = clkset_mout_mfc1_list,
873 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
876 static struct clksrc_clk clk_mout_mfc1 = {
880 .sources = &clkset_mout_mfc1,
881 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
884 static struct clk *clkset_mout_mfc_list[] = {
885 [0] = &clk_mout_mfc0.clk,
886 [1] = &clk_mout_mfc1.clk,
889 static struct clksrc_sources clkset_mout_mfc = {
890 .sources = clkset_mout_mfc_list,
891 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
894 static struct clk *clkset_sclk_dac_list[] = {
895 [0] = &clk_sclk_vpll.clk,
896 [1] = &clk_sclk_hdmiphy,
899 static struct clksrc_sources clkset_sclk_dac = {
900 .sources = clkset_sclk_dac_list,
901 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
904 static struct clksrc_clk clk_sclk_dac = {
907 .enable = exynos4_clksrc_mask_tv_ctrl,
910 .sources = &clkset_sclk_dac,
911 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
914 static struct clksrc_clk clk_sclk_pixel = {
916 .name = "sclk_pixel",
917 .parent = &clk_sclk_vpll.clk,
919 .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
922 static struct clk *clkset_sclk_hdmi_list[] = {
923 [0] = &clk_sclk_pixel.clk,
924 [1] = &clk_sclk_hdmiphy,
927 static struct clksrc_sources clkset_sclk_hdmi = {
928 .sources = clkset_sclk_hdmi_list,
929 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
932 static struct clksrc_clk clk_sclk_hdmi = {
935 .enable = exynos4_clksrc_mask_tv_ctrl,
938 .sources = &clkset_sclk_hdmi,
939 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
942 static struct clk *clkset_sclk_mixer_list[] = {
943 [0] = &clk_sclk_dac.clk,
944 [1] = &clk_sclk_hdmi.clk,
947 static struct clksrc_sources clkset_sclk_mixer = {
948 .sources = clkset_sclk_mixer_list,
949 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
952 static struct clksrc_clk clk_sclk_mixer = {
954 .name = "sclk_mixer",
955 .enable = exynos4_clksrc_mask_tv_ctrl,
958 .sources = &clkset_sclk_mixer,
959 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
962 static struct clksrc_clk *sclk_tv[] = {
969 static struct clksrc_clk clk_dout_mmc0 = {
973 .sources = &clkset_group,
974 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
975 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
978 static struct clksrc_clk clk_dout_mmc1 = {
982 .sources = &clkset_group,
983 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
984 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
987 static struct clksrc_clk clk_dout_mmc2 = {
991 .sources = &clkset_group,
992 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
993 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
996 static struct clksrc_clk clk_dout_mmc3 = {
1000 .sources = &clkset_group,
1001 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
1002 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1005 static struct clksrc_clk clk_dout_mmc4 = {
1007 .name = "dout_mmc4",
1009 .sources = &clkset_group,
1010 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
1011 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1014 static struct clksrc_clk clksrcs[] = {
1018 .enable = exynos4_clksrc_mask_peril0_ctrl,
1019 .ctrlbit = (1 << 24),
1021 .sources = &clkset_group,
1022 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1023 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1026 .name = "sclk_csis",
1027 .devname = "s5p-mipi-csis.0",
1028 .enable = exynos4_clksrc_mask_cam_ctrl,
1029 .ctrlbit = (1 << 24),
1031 .sources = &clkset_group,
1032 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
1033 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
1036 .name = "sclk_csis",
1037 .devname = "s5p-mipi-csis.1",
1038 .enable = exynos4_clksrc_mask_cam_ctrl,
1039 .ctrlbit = (1 << 28),
1041 .sources = &clkset_group,
1042 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
1043 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
1046 .name = "sclk_cam0",
1047 .enable = exynos4_clksrc_mask_cam_ctrl,
1048 .ctrlbit = (1 << 16),
1050 .sources = &clkset_group,
1051 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
1052 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
1055 .name = "sclk_cam1",
1056 .enable = exynos4_clksrc_mask_cam_ctrl,
1057 .ctrlbit = (1 << 20),
1059 .sources = &clkset_group,
1060 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
1061 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
1064 .name = "sclk_fimc",
1065 .devname = "exynos4-fimc.0",
1066 .enable = exynos4_clksrc_mask_cam_ctrl,
1067 .ctrlbit = (1 << 0),
1069 .sources = &clkset_group,
1070 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
1071 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
1074 .name = "sclk_fimc",
1075 .devname = "exynos4-fimc.1",
1076 .enable = exynos4_clksrc_mask_cam_ctrl,
1077 .ctrlbit = (1 << 4),
1079 .sources = &clkset_group,
1080 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
1081 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
1084 .name = "sclk_fimc",
1085 .devname = "exynos4-fimc.2",
1086 .enable = exynos4_clksrc_mask_cam_ctrl,
1087 .ctrlbit = (1 << 8),
1089 .sources = &clkset_group,
1090 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
1091 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1094 .name = "sclk_fimc",
1095 .devname = "exynos4-fimc.3",
1096 .enable = exynos4_clksrc_mask_cam_ctrl,
1097 .ctrlbit = (1 << 12),
1099 .sources = &clkset_group,
1100 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1101 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1104 .name = "sclk_fimd",
1105 .devname = "exynos4-fb.0",
1106 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1107 .ctrlbit = (1 << 0),
1109 .sources = &clkset_group,
1110 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1111 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1115 .devname = "s3c64xx-spi.0",
1116 .enable = exynos4_clksrc_mask_peril1_ctrl,
1117 .ctrlbit = (1 << 16),
1119 .sources = &clkset_group,
1120 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1121 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1125 .devname = "s3c64xx-spi.1",
1126 .enable = exynos4_clksrc_mask_peril1_ctrl,
1127 .ctrlbit = (1 << 20),
1129 .sources = &clkset_group,
1130 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1131 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1135 .devname = "s3c64xx-spi.2",
1136 .enable = exynos4_clksrc_mask_peril1_ctrl,
1137 .ctrlbit = (1 << 24),
1139 .sources = &clkset_group,
1140 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1141 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1144 .name = "sclk_fimg2d",
1146 .sources = &clkset_mout_g2d,
1147 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1148 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1152 .devname = "s5p-mfc",
1154 .sources = &clkset_mout_mfc,
1155 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1156 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1160 .devname = "s3c-sdhci.0",
1161 .parent = &clk_dout_mmc0.clk,
1162 .enable = exynos4_clksrc_mask_fsys_ctrl,
1163 .ctrlbit = (1 << 0),
1165 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1169 .devname = "s3c-sdhci.1",
1170 .parent = &clk_dout_mmc1.clk,
1171 .enable = exynos4_clksrc_mask_fsys_ctrl,
1172 .ctrlbit = (1 << 4),
1174 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1178 .devname = "s3c-sdhci.2",
1179 .parent = &clk_dout_mmc2.clk,
1180 .enable = exynos4_clksrc_mask_fsys_ctrl,
1181 .ctrlbit = (1 << 8),
1183 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1187 .devname = "s3c-sdhci.3",
1188 .parent = &clk_dout_mmc3.clk,
1189 .enable = exynos4_clksrc_mask_fsys_ctrl,
1190 .ctrlbit = (1 << 12),
1192 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1195 .name = "sclk_dwmmc",
1196 .parent = &clk_dout_mmc4.clk,
1197 .enable = exynos4_clksrc_mask_fsys_ctrl,
1198 .ctrlbit = (1 << 16),
1200 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1204 static struct clksrc_clk clk_sclk_uart0 = {
1207 .devname = "exynos4210-uart.0",
1208 .enable = exynos4_clksrc_mask_peril0_ctrl,
1209 .ctrlbit = (1 << 0),
1211 .sources = &clkset_group,
1212 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1213 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1216 static struct clksrc_clk clk_sclk_uart1 = {
1219 .devname = "exynos4210-uart.1",
1220 .enable = exynos4_clksrc_mask_peril0_ctrl,
1221 .ctrlbit = (1 << 4),
1223 .sources = &clkset_group,
1224 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1225 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1228 static struct clksrc_clk clk_sclk_uart2 = {
1231 .devname = "exynos4210-uart.2",
1232 .enable = exynos4_clksrc_mask_peril0_ctrl,
1233 .ctrlbit = (1 << 8),
1235 .sources = &clkset_group,
1236 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1237 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1240 static struct clksrc_clk clk_sclk_uart3 = {
1243 .devname = "exynos4210-uart.3",
1244 .enable = exynos4_clksrc_mask_peril0_ctrl,
1245 .ctrlbit = (1 << 12),
1247 .sources = &clkset_group,
1248 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1249 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1252 /* Clock initialization code */
1253 static struct clksrc_clk *sysclks[] = {
1286 static struct clk *clk_cdev[] = {
1291 static struct clksrc_clk *clksrc_cdev[] = {
1298 static struct clk_lookup exynos4_clk_lookup[] = {
1299 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
1300 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1301 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1302 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1303 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1304 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1307 static int xtal_rate;
1309 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1311 if (soc_is_exynos4210())
1312 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1314 else if (soc_is_exynos4212() || soc_is_exynos4412())
1315 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1320 static struct clk_ops exynos4_fout_apll_ops = {
1321 .get_rate = exynos4_fout_apll_get_rate,
1324 static u32 vpll_div[][8] = {
1325 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1326 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1329 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1334 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1336 unsigned int vpll_con0, vpll_con1 = 0;
1339 /* Return if nothing changed */
1340 if (clk->rate == rate)
1343 vpll_con0 = __raw_readl(S5P_VPLL_CON0);
1344 vpll_con0 &= ~(0x1 << 27 | \
1345 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1346 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1347 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1349 vpll_con1 = __raw_readl(S5P_VPLL_CON1);
1350 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1351 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1352 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1354 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1355 if (vpll_div[i][0] == rate) {
1356 vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1357 vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1358 vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1359 vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1360 vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1361 vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1362 vpll_con0 |= vpll_div[i][7] << 27;
1367 if (i == ARRAY_SIZE(vpll_div)) {
1368 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1373 __raw_writel(vpll_con0, S5P_VPLL_CON0);
1374 __raw_writel(vpll_con1, S5P_VPLL_CON1);
1376 /* Wait for VPLL lock */
1377 while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1384 static struct clk_ops exynos4_vpll_ops = {
1385 .get_rate = exynos4_vpll_get_rate,
1386 .set_rate = exynos4_vpll_set_rate,
1389 void __init_or_cpufreq exynos4_setup_clocks(void)
1391 struct clk *xtal_clk;
1392 unsigned long apll = 0;
1393 unsigned long mpll = 0;
1394 unsigned long epll = 0;
1395 unsigned long vpll = 0;
1396 unsigned long vpllsrc;
1398 unsigned long armclk;
1399 unsigned long sclk_dmc;
1400 unsigned long aclk_200;
1401 unsigned long aclk_100;
1402 unsigned long aclk_160;
1403 unsigned long aclk_133;
1406 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1408 xtal_clk = clk_get(NULL, "xtal");
1409 BUG_ON(IS_ERR(xtal_clk));
1411 xtal = clk_get_rate(xtal_clk);
1417 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1419 if (soc_is_exynos4210()) {
1420 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1422 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1424 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1425 __raw_readl(S5P_EPLL_CON1), pll_4600);
1427 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1428 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1429 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1430 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1431 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1432 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1433 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1434 __raw_readl(S5P_EPLL_CON1));
1436 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1437 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1438 __raw_readl(S5P_VPLL_CON1));
1443 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1444 clk_fout_mpll.rate = mpll;
1445 clk_fout_epll.rate = epll;
1446 clk_fout_vpll.ops = &exynos4_vpll_ops;
1447 clk_fout_vpll.rate = vpll;
1449 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1450 apll, mpll, epll, vpll);
1452 armclk = clk_get_rate(&clk_armclk.clk);
1453 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1455 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1456 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1457 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1458 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1460 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1461 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1462 armclk, sclk_dmc, aclk_200,
1463 aclk_100, aclk_160, aclk_133);
1465 clk_f.rate = armclk;
1466 clk_h.rate = sclk_dmc;
1467 clk_p.rate = aclk_100;
1469 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1470 s3c_set_clksrc(&clksrcs[ptr], true);
1473 static struct clk *clks[] __initdata = {
1480 #ifdef CONFIG_PM_SLEEP
1481 static int exynos4_clock_suspend(void)
1483 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1487 static void exynos4_clock_resume(void)
1489 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1493 #define exynos4_clock_suspend NULL
1494 #define exynos4_clock_resume NULL
1497 struct syscore_ops exynos4_clock_syscore_ops = {
1498 .suspend = exynos4_clock_suspend,
1499 .resume = exynos4_clock_resume,
1502 void __init exynos4_register_clocks(void)
1506 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1508 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1509 s3c_register_clksrc(sysclks[ptr], 1);
1511 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1512 s3c_register_clksrc(sclk_tv[ptr], 1);
1514 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1515 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1517 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1518 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1520 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1521 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1522 s3c_disable_clocks(clk_cdev[ptr], 1);
1524 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1525 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1526 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1528 register_syscore_ops(&exynos4_clock_syscore_ops);
1529 s3c24xx_register_clock(&dummy_apb_pclk);