arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/irqchip.h>
  16 #include <linux/io.h>
  17 #include <linux/device.h>
  18 #include <linux/gpio.h>
  19 #include <linux/sched.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/of.h>
  22 #include <linux/of_fdt.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/export.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/irqchip.h>
  27 #include <linux/of_address.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/clk-provider.h>
  30 #include <linux/irqchip/arm-gic.h>
  31
  32 #include <asm/proc-fns.h>
  33 #include <asm/exception.h>
  34 #include <asm/hardware/cache-l2x0.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/cacheflush.h>
  38
  39 #include <mach/regs-irq.h>
  40 #include <mach/regs-pmu.h>
  41 #include <mach/regs-gpio.h>
  42
  43 #include <plat/cpu.h>
  44 #include <plat/devs.h>
  45 #include <plat/pm.h>
  46 #include <plat/sdhci.h>
  47 #include <plat/gpio-cfg.h>
  48 #include <plat/adc-core.h>
  49 #include <plat/fb-core.h>
  50 #include <plat/fimc-core.h>
  51 #include <plat/iic-core.h>
  52 #include <plat/tv-core.h>
  53 #include <plat/spi-core.h>
  54 #include <plat/regs-serial.h>
  55
  56 #include "common.h"
  57 #define L2_AUX_VAL 0x7C470001
  58 #define L2_AUX_MASK 0xC200ffff
  59
  60 static const char name_exynos4210[] = "EXYNOS4210";
  61 static const char name_exynos4212[] = "EXYNOS4212";
  62 static const char name_exynos4412[] = "EXYNOS4412";
  63 static const char name_exynos5250[] = "EXYNOS5250";
  64 static const char name_exynos5440[] = "EXYNOS5440";
  65
  66 static void exynos4_map_io(void);
  67 static void exynos5_map_io(void);
  68 static void exynos5440_map_io(void);
  69 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  70 static int exynos_init(void);
  71
  72 static struct cpu_table cpu_ids[] __initdata = {
  73         {
  74                 .idcode         = EXYNOS4210_CPU_ID,
  75                 .idmask         = EXYNOS4_CPU_MASK,
  76                 .map_io         = exynos4_map_io,
  77                 .init_uarts     = exynos4_init_uarts,
  78                 .init           = exynos_init,
  79                 .name           = name_exynos4210,
  80         }, {
  81                 .idcode         = EXYNOS4212_CPU_ID,
  82                 .idmask         = EXYNOS4_CPU_MASK,
  83                 .map_io         = exynos4_map_io,
  84                 .init_uarts     = exynos4_init_uarts,
  85                 .init           = exynos_init,
  86                 .name           = name_exynos4212,
  87         }, {
  88                 .idcode         = EXYNOS4412_CPU_ID,
  89                 .idmask         = EXYNOS4_CPU_MASK,
  90                 .map_io         = exynos4_map_io,
  91                 .init_uarts     = exynos4_init_uarts,
  92                 .init           = exynos_init,
  93                 .name           = name_exynos4412,
  94         }, {
  95                 .idcode         = EXYNOS5250_SOC_ID,
  96                 .idmask         = EXYNOS5_SOC_MASK,
  97                 .map_io         = exynos5_map_io,
  98                 .init           = exynos_init,
  99                 .name           = name_exynos5250,
 100         }, {
 101                 .idcode         = EXYNOS5440_SOC_ID,
 102                 .idmask         = EXYNOS5_SOC_MASK,
 103                 .map_io         = exynos5440_map_io,
 104                 .init           = exynos_init,
 105                 .name           = name_exynos5440,
 106         },
 107 };
 108
 109 /* Initial IO mappings */
 110
 111 static struct map_desc exynos_iodesc[] __initdata = {
 112         {
 113                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 114                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 115                 .length         = SZ_4K,
 116                 .type           = MT_DEVICE,
 117         },
 118 };
 119
 120 #ifdef CONFIG_ARCH_EXYNOS5
 121 static struct map_desc exynos5440_iodesc[] __initdata = {
 122         {
 123                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 124                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
 125                 .length         = SZ_4K,
 126                 .type           = MT_DEVICE,
 127         },
 128 };
 129 #endif
 130
 131 static struct map_desc exynos4_iodesc[] __initdata = {
 132         {
 133                 .virtual        = (unsigned long)S3C_VA_SYS,
 134                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 135                 .length         = SZ_64K,
 136                 .type           = MT_DEVICE,
 137         }, {
 138                 .virtual        = (unsigned long)S3C_VA_TIMER,
 139                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 140                 .length         = SZ_16K,
 141                 .type           = MT_DEVICE,
 142         }, {
 143                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 144                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 145                 .length         = SZ_4K,
 146                 .type           = MT_DEVICE,
 147         }, {
 148                 .virtual        = (unsigned long)S5P_VA_SROMC,
 149                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 150                 .length         = SZ_4K,
 151                 .type           = MT_DEVICE,
 152         }, {
 153                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 154                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 155                 .length         = SZ_4K,
 156                 .type           = MT_DEVICE,
 157         }, {
 158                 .virtual        = (unsigned long)S5P_VA_PMU,
 159                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 160                 .length         = SZ_64K,
 161                 .type           = MT_DEVICE,
 162         }, {
 163                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 164                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 165                 .length         = SZ_4K,
 166                 .type           = MT_DEVICE,
 167         }, {
 168                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 169                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 170                 .length         = SZ_64K,
 171                 .type           = MT_DEVICE,
 172         }, {
 173                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 174                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 175                 .length         = SZ_64K,
 176                 .type           = MT_DEVICE,
 177         }, {
 178                 .virtual        = (unsigned long)S3C_VA_UART,
 179                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 180                 .length         = SZ_512K,
 181                 .type           = MT_DEVICE,
 182         }, {
 183                 .virtual        = (unsigned long)S5P_VA_CMU,
 184                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 185                 .length         = SZ_128K,
 186                 .type           = MT_DEVICE,
 187         }, {
 188                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 189                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 190                 .length         = SZ_8K,
 191                 .type           = MT_DEVICE,
 192         }, {
 193                 .virtual        = (unsigned long)S5P_VA_L2CC,
 194                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 195                 .length         = SZ_4K,
 196                 .type           = MT_DEVICE,
 197         }, {
 198                 .virtual        = (unsigned long)S5P_VA_DMC0,
 199                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 200                 .length         = SZ_64K,
 201                 .type           = MT_DEVICE,
 202         }, {
 203                 .virtual        = (unsigned long)S5P_VA_DMC1,
 204                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 205                 .length         = SZ_64K,
 206                 .type           = MT_DEVICE,
 207         }, {
 208                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 209                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 210                 .length         = SZ_4K,
 211                 .type           = MT_DEVICE,
 212         },
 213 };
 214
 215 static struct map_desc exynos4_iodesc0[] __initdata = {
 216         {
 217                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 218                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 219                 .length         = SZ_4K,
 220                 .type           = MT_DEVICE,
 221         },
 222 };
 223
 224 static struct map_desc exynos4_iodesc1[] __initdata = {
 225         {
 226                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 227                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 228                 .length         = SZ_4K,
 229                 .type           = MT_DEVICE,
 230         },
 231 };
 232
 233 static struct map_desc exynos5_iodesc[] __initdata = {
 234         {
 235                 .virtual        = (unsigned long)S3C_VA_SYS,
 236                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 237                 .length         = SZ_64K,
 238                 .type           = MT_DEVICE,
 239         }, {
 240                 .virtual        = (unsigned long)S3C_VA_TIMER,
 241                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 242                 .length         = SZ_16K,
 243                 .type           = MT_DEVICE,
 244         }, {
 245                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 246                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 247                 .length         = SZ_4K,
 248                 .type           = MT_DEVICE,
 249         }, {
 250                 .virtual        = (unsigned long)S5P_VA_SROMC,
 251                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 252                 .length         = SZ_4K,
 253                 .type           = MT_DEVICE,
 254         }, {
 255                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 256                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 257                 .length         = SZ_4K,
 258                 .type           = MT_DEVICE,
 259         }, {
 260                 .virtual        = (unsigned long)S5P_VA_CMU,
 261                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 262                 .length         = 144 * SZ_1K,
 263                 .type           = MT_DEVICE,
 264         }, {
 265                 .virtual        = (unsigned long)S5P_VA_PMU,
 266                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 267                 .length         = SZ_64K,
 268                 .type           = MT_DEVICE,
 269         }, {
 270                 .virtual        = (unsigned long)S3C_VA_UART,
 271                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 272                 .length         = SZ_512K,
 273                 .type           = MT_DEVICE,
 274         },
 275 };
 276
 277 static struct map_desc exynos5440_iodesc0[] __initdata = {
 278         {
 279                 .virtual        = (unsigned long)S3C_VA_UART,
 280                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 281                 .length         = SZ_512K,
 282                 .type           = MT_DEVICE,
 283         },
 284 };
 285
 286 void exynos4_restart(char mode, const char *cmd)
 287 {
 288         __raw_writel(0x1, S5P_SWRESET);
 289 }
 290
 291 void exynos5_restart(char mode, const char *cmd)
 292 {
 293         struct device_node *np;
 294         u32 val;
 295         void __iomem *addr;
 296
 297         if (of_machine_is_compatible("samsung,exynos5250")) {
 298                 val = 0x1;
 299                 addr = EXYNOS_SWRESET;
 300         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 301                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 302                 addr = of_iomap(np, 0) + 0xcc;
 303                 val = (0xfff << 20) | (0x1 << 16);
 304         } else {
 305                 pr_err("%s: cannot support non-DT\n", __func__);
 306                 return;
 307         }
 308
 309         __raw_writel(val, addr);
 310 }
 311
 312 void __init exynos_init_late(void)
 313 {
 314         if (of_machine_is_compatible("samsung,exynos5440"))
 315                 /* to be supported later */
 316                 return;
 317
 318         exynos_pm_late_initcall();
 319 }
 320
 321 /*
 322  * exynos_map_io
 323  *
 324  * register the standard cpu IO areas
 325  */
 326
 327 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 328 {
 329         struct map_desc *iodesc = exynos_iodesc;
 330         int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
 331 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
 332         unsigned long root = of_get_flat_dt_root();
 333
 334         /* initialize the io descriptors we need for initialization */
 335         if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
 336                 iodesc = exynos5440_iodesc;
 337                 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
 338         }
 339 #endif
 340
 341         iotable_init(iodesc, iodesc_sz);
 342
 343         if (mach_desc)
 344                 iotable_init(mach_desc, size);
 345
 346         /* detect cpu id and rev. */
 347         s5p_init_cpu(S5P_VA_CHIPID);
 348
 349         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 350 }
 351
 352 static void __init exynos4_map_io(void)
 353 {
 354         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 355
 356         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 357                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 358         else
 359                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 360
 361         /* initialize device information early */
 362         exynos4_default_sdhci0();
 363         exynos4_default_sdhci1();
 364         exynos4_default_sdhci2();
 365         exynos4_default_sdhci3();
 366
 367         s3c_adc_setname("samsung-adc-v3");
 368
 369         s3c_fimc_setname(0, "exynos4-fimc");
 370         s3c_fimc_setname(1, "exynos4-fimc");
 371         s3c_fimc_setname(2, "exynos4-fimc");
 372         s3c_fimc_setname(3, "exynos4-fimc");
 373
 374         s3c_sdhci_setname(0, "exynos4-sdhci");
 375         s3c_sdhci_setname(1, "exynos4-sdhci");
 376         s3c_sdhci_setname(2, "exynos4-sdhci");
 377         s3c_sdhci_setname(3, "exynos4-sdhci");
 378
 379         /* The I2C bus controllers are directly compatible with s3c2440 */
 380         s3c_i2c0_setname("s3c2440-i2c");
 381         s3c_i2c1_setname("s3c2440-i2c");
 382         s3c_i2c2_setname("s3c2440-i2c");
 383
 384         s5p_fb_setname(0, "exynos4-fb");
 385         s5p_hdmi_setname("exynos4-hdmi");
 386
 387         s3c64xx_spi_setname("exynos4210-spi");
 388 }
 389
 390 static void __init exynos5_map_io(void)
 391 {
 392         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 393 }
 394
 395 static void __init exynos5440_map_io(void)
 396 {
 397         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 398 }
 399
 400 void __init exynos_init_time(void)
 401 {
 402         if (of_have_populated_dt()) {
 403 #ifdef CONFIG_OF
 404                 of_clk_init(NULL);
 405                 clocksource_of_init();
 406 #endif
 407         } else {
 408                 /* todo: remove after migrating legacy E4 platforms to dt */
 409                 exynos4_clk_init(NULL);
 410                 mct_init();
 411         }
 412 }
 413
 414 void __init exynos4_init_irq(void)
 415 {
 416         unsigned int gic_bank_offset;
 417
 418         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 419
 420         if (!of_have_populated_dt())
 421                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 422 #ifdef CONFIG_OF
 423         else
 424                 irqchip_init();
 425 #endif
 426
 427         if (!of_have_populated_dt())
 428                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 429
 430         /*
 431          * The parameters of s5p_init_irq() are for VIC init.
 432          * Theses parameters should be NULL and 0 because EXYNOS4
 433          * uses GIC instead of VIC.
 434          */
 435         s5p_init_irq(NULL, 0);
 436 }
 437
 438 void __init exynos5_init_irq(void)
 439 {
 440 #ifdef CONFIG_OF
 441         irqchip_init();
 442 #endif
 443         /*
 444          * The parameters of s5p_init_irq() are for VIC init.
 445          * Theses parameters should be NULL and 0 because EXYNOS4
 446          * uses GIC instead of VIC.
 447          */
 448         if (!of_machine_is_compatible("samsung,exynos5440"))
 449                 s5p_init_irq(NULL, 0);
 450
 451         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 452 }
 453
 454 struct bus_type exynos_subsys = {
 455         .name           = "exynos-core",
 456         .dev_name       = "exynos-core",
 457 };
 458
 459 static struct device exynos4_dev = {
 460         .bus    = &exynos_subsys,
 461 };
 462
 463 static int __init exynos_core_init(void)
 464 {
 465         return subsys_system_register(&exynos_subsys, NULL);
 466 }
 467 core_initcall(exynos_core_init);
 468
 469 #ifdef CONFIG_CACHE_L2X0
 470 static int __init exynos4_l2x0_cache_init(void)
 471 {
 472         int ret;
 473
 474         if (soc_is_exynos5250() || soc_is_exynos5440())
 475                 return 0;
 476
 477         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 478         if (!ret) {
 479                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 480                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 481                 return 0;
 482         }
 483
 484         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 485                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 486                 /* TAG, Data Latency Control: 2 cycles */
 487                 l2x0_saved_regs.tag_latency = 0x110;
 488
 489                 if (soc_is_exynos4212() || soc_is_exynos4412())
 490                         l2x0_saved_regs.data_latency = 0x120;
 491                 else
 492                         l2x0_saved_regs.data_latency = 0x110;
 493
 494                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 495                 l2x0_saved_regs.pwr_ctrl =
 496                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 497
 498                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 499
 500                 __raw_writel(l2x0_saved_regs.tag_latency,
 501                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 502                 __raw_writel(l2x0_saved_regs.data_latency,
 503                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 504
 505                 /* L2X0 Prefetch Control */
 506                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 507                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 508
 509                 /* L2X0 Power Control */
 510                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 511                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 512
 513                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 514                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 515         }
 516
 517         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 518         return 0;
 519 }
 520 early_initcall(exynos4_l2x0_cache_init);
 521 #endif
 522
 523 static int __init exynos_init(void)
 524 {
 525         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 526
 527         return device_register(&exynos4_dev);
 528 }
 529
 530 /* uart registration process */
 531
 532 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 533 {
 534         struct s3c2410_uartcfg *tcfg = cfg;
 535         u32 ucnt;
 536
 537         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 538                 tcfg->has_fracval = 1;
 539
 540         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 541 }
 542
 543 static void __iomem *exynos_eint_base;
 544
 545 static DEFINE_SPINLOCK(eint_lock);
 546
 547 static unsigned int eint0_15_data[16];
 548
 549 static inline int exynos4_irq_to_gpio(unsigned int irq)
 550 {
 551         if (irq < IRQ_EINT(0))
 552                 return -EINVAL;
 553
 554         irq -= IRQ_EINT(0);
 555         if (irq < 8)
 556                 return EXYNOS4_GPX0(irq);
 557
 558         irq -= 8;
 559         if (irq < 8)
 560                 return EXYNOS4_GPX1(irq);
 561
 562         irq -= 8;
 563         if (irq < 8)
 564                 return EXYNOS4_GPX2(irq);
 565
 566         irq -= 8;
 567         if (irq < 8)
 568                 return EXYNOS4_GPX3(irq);
 569
 570         return -EINVAL;
 571 }
 572
 573 static inline int exynos5_irq_to_gpio(unsigned int irq)
 574 {
 575         if (irq < IRQ_EINT(0))
 576                 return -EINVAL;
 577
 578         irq -= IRQ_EINT(0);
 579         if (irq < 8)
 580                 return EXYNOS5_GPX0(irq);
 581
 582         irq -= 8;
 583         if (irq < 8)
 584                 return EXYNOS5_GPX1(irq);
 585
 586         irq -= 8;
 587         if (irq < 8)
 588                 return EXYNOS5_GPX2(irq);
 589
 590         irq -= 8;
 591         if (irq < 8)
 592                 return EXYNOS5_GPX3(irq);
 593
 594         return -EINVAL;
 595 }
 596
 597 static unsigned int exynos4_eint0_15_src_int[16] = {
 598         EXYNOS4_IRQ_EINT0,
 599         EXYNOS4_IRQ_EINT1,
 600         EXYNOS4_IRQ_EINT2,
 601         EXYNOS4_IRQ_EINT3,
 602         EXYNOS4_IRQ_EINT4,
 603         EXYNOS4_IRQ_EINT5,
 604         EXYNOS4_IRQ_EINT6,
 605         EXYNOS4_IRQ_EINT7,
 606         EXYNOS4_IRQ_EINT8,
 607         EXYNOS4_IRQ_EINT9,
 608         EXYNOS4_IRQ_EINT10,
 609         EXYNOS4_IRQ_EINT11,
 610         EXYNOS4_IRQ_EINT12,
 611         EXYNOS4_IRQ_EINT13,
 612         EXYNOS4_IRQ_EINT14,
 613         EXYNOS4_IRQ_EINT15,
 614 };
 615
 616 static unsigned int exynos5_eint0_15_src_int[16] = {
 617         EXYNOS5_IRQ_EINT0,
 618         EXYNOS5_IRQ_EINT1,
 619         EXYNOS5_IRQ_EINT2,
 620         EXYNOS5_IRQ_EINT3,
 621         EXYNOS5_IRQ_EINT4,
 622         EXYNOS5_IRQ_EINT5,
 623         EXYNOS5_IRQ_EINT6,
 624         EXYNOS5_IRQ_EINT7,
 625         EXYNOS5_IRQ_EINT8,
 626         EXYNOS5_IRQ_EINT9,
 627         EXYNOS5_IRQ_EINT10,
 628         EXYNOS5_IRQ_EINT11,
 629         EXYNOS5_IRQ_EINT12,
 630         EXYNOS5_IRQ_EINT13,
 631         EXYNOS5_IRQ_EINT14,
 632         EXYNOS5_IRQ_EINT15,
 633 };
 634 static inline void exynos_irq_eint_mask(struct irq_data *data)
 635 {
 636         u32 mask;
 637
 638         spin_lock(&eint_lock);
 639         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 640         mask |= EINT_OFFSET_BIT(data->irq);
 641         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 642         spin_unlock(&eint_lock);
 643 }
 644
 645 static void exynos_irq_eint_unmask(struct irq_data *data)
 646 {
 647         u32 mask;
 648
 649         spin_lock(&eint_lock);
 650         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 651         mask &= ~(EINT_OFFSET_BIT(data->irq));
 652         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 653         spin_unlock(&eint_lock);
 654 }
 655
 656 static inline void exynos_irq_eint_ack(struct irq_data *data)
 657 {
 658         __raw_writel(EINT_OFFSET_BIT(data->irq),
 659                      EINT_PEND(exynos_eint_base, data->irq));
 660 }
 661
 662 static void exynos_irq_eint_maskack(struct irq_data *data)
 663 {
 664         exynos_irq_eint_mask(data);
 665         exynos_irq_eint_ack(data);
 666 }
 667
 668 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 669 {
 670         int offs = EINT_OFFSET(data->irq);
 671         int shift;
 672         u32 ctrl, mask;
 673         u32 newvalue = 0;
 674
 675         switch (type) {
 676         case IRQ_TYPE_EDGE_RISING:
 677                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 678                 break;
 679
 680         case IRQ_TYPE_EDGE_FALLING:
 681                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 682                 break;
 683
 684         case IRQ_TYPE_EDGE_BOTH:
 685                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 686                 break;
 687
 688         case IRQ_TYPE_LEVEL_LOW:
 689                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 690                 break;
 691
 692         case IRQ_TYPE_LEVEL_HIGH:
 693                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 694                 break;
 695
 696         default:
 697                 printk(KERN_ERR "No such irq type %d", type);
 698                 return -EINVAL;
 699         }
 700
 701         shift = (offs & 0x7) * 4;
 702         mask = 0x7 << shift;
 703
 704         spin_lock(&eint_lock);
 705         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 706         ctrl &= ~mask;
 707         ctrl |= newvalue << shift;
 708         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 709         spin_unlock(&eint_lock);
 710
 711         if (soc_is_exynos5250())
 712                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 713         else
 714                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 715
 716         return 0;
 717 }
 718
 719 static struct irq_chip exynos_irq_eint = {
 720         .name           = "exynos-eint",
 721         .irq_mask       = exynos_irq_eint_mask,
 722         .irq_unmask     = exynos_irq_eint_unmask,
 723         .irq_mask_ack   = exynos_irq_eint_maskack,
 724         .irq_ack        = exynos_irq_eint_ack,
 725         .irq_set_type   = exynos_irq_eint_set_type,
 726 #ifdef CONFIG_PM
 727         .irq_set_wake   = s3c_irqext_wake,
 728 #endif
 729 };
 730
 731 /*
 732  * exynos4_irq_demux_eint
 733  *
 734  * This function demuxes the IRQ from from EINTs 16 to 31.
 735  * It is designed to be inlined into the specific handler
 736  * s5p_irq_demux_eintX_Y.
 737  *
 738  * Each EINT pend/mask registers handle eight of them.
 739  */
 740 static inline void exynos_irq_demux_eint(unsigned int start)
 741 {
 742         unsigned int irq;
 743
 744         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 745         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 746
 747         status &= ~mask;
 748         status &= 0xff;
 749
 750         while (status) {
 751                 irq = fls(status) - 1;
 752                 generic_handle_irq(irq + start);
 753                 status &= ~(1 << irq);
 754         }
 755 }
 756
 757 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 758 {
 759         struct irq_chip *chip = irq_get_chip(irq);
 760         chained_irq_enter(chip, desc);
 761         exynos_irq_demux_eint(IRQ_EINT(16));
 762         exynos_irq_demux_eint(IRQ_EINT(24));
 763         chained_irq_exit(chip, desc);
 764 }
 765
 766 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 767 {
 768         u32 *irq_data = irq_get_handler_data(irq);
 769         struct irq_chip *chip = irq_get_chip(irq);
 770
 771         chained_irq_enter(chip, desc);
 772         generic_handle_irq(*irq_data);
 773         chained_irq_exit(chip, desc);
 774 }
 775
 776 static int __init exynos_init_irq_eint(void)
 777 {
 778         int irq;
 779
 780 #ifdef CONFIG_PINCTRL_SAMSUNG
 781         /*
 782          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
 783          * functionality along with support for external gpio and wakeup
 784          * interrupts. If the samsung pinctrl driver is enabled and includes
 785          * the wakeup interrupt support, then the setting up external wakeup
 786          * interrupts here can be skipped. This check here is temporary to
 787          * allow exynos4 platforms that do not use Samsung pinctrl driver to
 788          * co-exist with platforms that do. When all of the Samsung Exynos4
 789          * platforms switch over to using the pinctrl driver, the wakeup
 790          * interrupt support code here can be completely removed.
 791          */
 792         static const struct of_device_id exynos_pinctrl_ids[] = {
 793                 { .compatible = "samsung,exynos4210-pinctrl", },
 794                 { .compatible = "samsung,exynos4x12-pinctrl", },
 795         };
 796         struct device_node *pctrl_np, *wkup_np;
 797         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
 798
 799         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
 800                 if (of_device_is_available(pctrl_np)) {
 801                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
 802                                                         wkup_compat);
 803                         if (wkup_np)
 804                                 return -ENODEV;
 805                 }
 806         }
 807 #endif
 808         if (soc_is_exynos5440())
 809                 return 0;
 810
 811         if (soc_is_exynos5250())
 812                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 813         else
 814                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 815
 816         if (exynos_eint_base == NULL) {
 817                 pr_err("unable to ioremap for EINT base address\n");
 818                 return -ENOMEM;
 819         }
 820
 821         for (irq = 0 ; irq <= 31 ; irq++) {
 822                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 823                                          handle_level_irq);
 824                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 825         }
 826
 827         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 828
 829         for (irq = 0 ; irq <= 15 ; irq++) {
 830                 eint0_15_data[irq] = IRQ_EINT(irq);
 831
 832                 if (soc_is_exynos5250()) {
 833                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
 834                                              &eint0_15_data[irq]);
 835                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
 836                                                 exynos_irq_eint0_15);
 837                 } else {
 838                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
 839                                              &eint0_15_data[irq]);
 840                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
 841                                                 exynos_irq_eint0_15);
 842                 }
 843         }
 844
 845         return 0;
 846 }
 847 arch_initcall(exynos_init_irq_eint);