arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/irqchip.h>
  16 #include <linux/io.h>
  17 #include <linux/device.h>
  18 #include <linux/gpio.h>
  19 #include <linux/sched.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/of.h>
  22 #include <linux/of_fdt.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/export.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/irqchip.h>
  27 #include <linux/of_address.h>
  28 #include <linux/irqchip/arm-gic.h>
  29
  30 #include <asm/proc-fns.h>
  31 #include <asm/exception.h>
  32 #include <asm/hardware/cache-l2x0.h>
  33 #include <asm/mach/map.h>
  34 #include <asm/mach/irq.h>
  35 #include <asm/cacheflush.h>
  36
  37 #include <mach/regs-irq.h>
  38 #include <mach/regs-pmu.h>
  39 #include <mach/regs-gpio.h>
  40
  41 #include <plat/cpu.h>
  42 #include <plat/devs.h>
  43 #include <plat/pm.h>
  44 #include <plat/sdhci.h>
  45 #include <plat/gpio-cfg.h>
  46 #include <plat/adc-core.h>
  47 #include <plat/fb-core.h>
  48 #include <plat/fimc-core.h>
  49 #include <plat/iic-core.h>
  50 #include <plat/tv-core.h>
  51 #include <plat/spi-core.h>
  52 #include <plat/regs-serial.h>
  53
  54 #include "common.h"
  55 #define L2_AUX_VAL 0x7C470001
  56 #define L2_AUX_MASK 0xC200ffff
  57
  58 static const char name_exynos4210[] = "EXYNOS4210";
  59 static const char name_exynos4212[] = "EXYNOS4212";
  60 static const char name_exynos4412[] = "EXYNOS4412";
  61 static const char name_exynos5250[] = "EXYNOS5250";
  62 static const char name_exynos5440[] = "EXYNOS5440";
  63
  64 static void exynos4_map_io(void);
  65 static void exynos5_map_io(void);
  66 static void exynos5440_map_io(void);
  67 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  68 static int exynos_init(void);
  69
  70 static struct cpu_table cpu_ids[] __initdata = {
  71         {
  72                 .idcode         = EXYNOS4210_CPU_ID,
  73                 .idmask         = EXYNOS4_CPU_MASK,
  74                 .map_io         = exynos4_map_io,
  75                 .init_uarts     = exynos4_init_uarts,
  76                 .init           = exynos_init,
  77                 .name           = name_exynos4210,
  78         }, {
  79                 .idcode         = EXYNOS4212_CPU_ID,
  80                 .idmask         = EXYNOS4_CPU_MASK,
  81                 .map_io         = exynos4_map_io,
  82                 .init_uarts     = exynos4_init_uarts,
  83                 .init           = exynos_init,
  84                 .name           = name_exynos4212,
  85         }, {
  86                 .idcode         = EXYNOS4412_CPU_ID,
  87                 .idmask         = EXYNOS4_CPU_MASK,
  88                 .map_io         = exynos4_map_io,
  89                 .init_uarts     = exynos4_init_uarts,
  90                 .init           = exynos_init,
  91                 .name           = name_exynos4412,
  92         }, {
  93                 .idcode         = EXYNOS5250_SOC_ID,
  94                 .idmask         = EXYNOS5_SOC_MASK,
  95                 .map_io         = exynos5_map_io,
  96                 .init           = exynos_init,
  97                 .name           = name_exynos5250,
  98         }, {
  99                 .idcode         = EXYNOS5440_SOC_ID,
 100                 .idmask         = EXYNOS5_SOC_MASK,
 101                 .map_io         = exynos5440_map_io,
 102                 .init           = exynos_init,
 103                 .name           = name_exynos5440,
 104         },
 105 };
 106
 107 /* Initial IO mappings */
 108
 109 static struct map_desc exynos_iodesc[] __initdata = {
 110         {
 111                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 112                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 113                 .length         = SZ_4K,
 114                 .type           = MT_DEVICE,
 115         },
 116 };
 117
 118 #ifdef CONFIG_ARCH_EXYNOS5
 119 static struct map_desc exynos5440_iodesc[] __initdata = {
 120         {
 121                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 122                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
 123                 .length         = SZ_4K,
 124                 .type           = MT_DEVICE,
 125         },
 126 };
 127 #endif
 128
 129 static struct map_desc exynos4_iodesc[] __initdata = {
 130         {
 131                 .virtual        = (unsigned long)S3C_VA_SYS,
 132                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 133                 .length         = SZ_64K,
 134                 .type           = MT_DEVICE,
 135         }, {
 136                 .virtual        = (unsigned long)S3C_VA_TIMER,
 137                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 138                 .length         = SZ_16K,
 139                 .type           = MT_DEVICE,
 140         }, {
 141                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 142                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 143                 .length         = SZ_4K,
 144                 .type           = MT_DEVICE,
 145         }, {
 146                 .virtual        = (unsigned long)S5P_VA_SROMC,
 147                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 148                 .length         = SZ_4K,
 149                 .type           = MT_DEVICE,
 150         }, {
 151                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 152                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 153                 .length         = SZ_4K,
 154                 .type           = MT_DEVICE,
 155         }, {
 156                 .virtual        = (unsigned long)S5P_VA_PMU,
 157                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 158                 .length         = SZ_64K,
 159                 .type           = MT_DEVICE,
 160         }, {
 161                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 162                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 163                 .length         = SZ_4K,
 164                 .type           = MT_DEVICE,
 165         }, {
 166                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 167                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 168                 .length         = SZ_64K,
 169                 .type           = MT_DEVICE,
 170         }, {
 171                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 172                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 173                 .length         = SZ_64K,
 174                 .type           = MT_DEVICE,
 175         }, {
 176                 .virtual        = (unsigned long)S3C_VA_UART,
 177                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 178                 .length         = SZ_512K,
 179                 .type           = MT_DEVICE,
 180         }, {
 181                 .virtual        = (unsigned long)S5P_VA_CMU,
 182                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 183                 .length         = SZ_128K,
 184                 .type           = MT_DEVICE,
 185         }, {
 186                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 187                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 188                 .length         = SZ_8K,
 189                 .type           = MT_DEVICE,
 190         }, {
 191                 .virtual        = (unsigned long)S5P_VA_L2CC,
 192                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 193                 .length         = SZ_4K,
 194                 .type           = MT_DEVICE,
 195         }, {
 196                 .virtual        = (unsigned long)S5P_VA_DMC0,
 197                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 198                 .length         = SZ_64K,
 199                 .type           = MT_DEVICE,
 200         }, {
 201                 .virtual        = (unsigned long)S5P_VA_DMC1,
 202                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 203                 .length         = SZ_64K,
 204                 .type           = MT_DEVICE,
 205         }, {
 206                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 207                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 208                 .length         = SZ_4K,
 209                 .type           = MT_DEVICE,
 210         },
 211 };
 212
 213 static struct map_desc exynos4_iodesc0[] __initdata = {
 214         {
 215                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 216                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 217                 .length         = SZ_4K,
 218                 .type           = MT_DEVICE,
 219         },
 220 };
 221
 222 static struct map_desc exynos4_iodesc1[] __initdata = {
 223         {
 224                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 225                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 226                 .length         = SZ_4K,
 227                 .type           = MT_DEVICE,
 228         },
 229 };
 230
 231 static struct map_desc exynos5_iodesc[] __initdata = {
 232         {
 233                 .virtual        = (unsigned long)S3C_VA_SYS,
 234                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 235                 .length         = SZ_64K,
 236                 .type           = MT_DEVICE,
 237         }, {
 238                 .virtual        = (unsigned long)S3C_VA_TIMER,
 239                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 240                 .length         = SZ_16K,
 241                 .type           = MT_DEVICE,
 242         }, {
 243                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 244                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 245                 .length         = SZ_4K,
 246                 .type           = MT_DEVICE,
 247         }, {
 248                 .virtual        = (unsigned long)S5P_VA_SROMC,
 249                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 250                 .length         = SZ_4K,
 251                 .type           = MT_DEVICE,
 252         }, {
 253                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 254                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 255                 .length         = SZ_4K,
 256                 .type           = MT_DEVICE,
 257         }, {
 258                 .virtual        = (unsigned long)S5P_VA_CMU,
 259                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 260                 .length         = 144 * SZ_1K,
 261                 .type           = MT_DEVICE,
 262         }, {
 263                 .virtual        = (unsigned long)S5P_VA_PMU,
 264                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 265                 .length         = SZ_64K,
 266                 .type           = MT_DEVICE,
 267         }, {
 268                 .virtual        = (unsigned long)S3C_VA_UART,
 269                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 270                 .length         = SZ_512K,
 271                 .type           = MT_DEVICE,
 272         },
 273 };
 274
 275 static struct map_desc exynos5440_iodesc0[] __initdata = {
 276         {
 277                 .virtual        = (unsigned long)S3C_VA_UART,
 278                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 279                 .length         = SZ_512K,
 280                 .type           = MT_DEVICE,
 281         },
 282 };
 283
 284 void exynos4_restart(char mode, const char *cmd)
 285 {
 286         __raw_writel(0x1, S5P_SWRESET);
 287 }
 288
 289 void exynos5_restart(char mode, const char *cmd)
 290 {
 291         struct device_node *np;
 292         u32 val;
 293         void __iomem *addr;
 294
 295         if (of_machine_is_compatible("samsung,exynos5250")) {
 296                 val = 0x1;
 297                 addr = EXYNOS_SWRESET;
 298         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 299                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 300                 addr = of_iomap(np, 0) + 0xcc;
 301                 val = (0xfff << 20) | (0x1 << 16);
 302         } else {
 303                 pr_err("%s: cannot support non-DT\n", __func__);
 304                 return;
 305         }
 306
 307         __raw_writel(val, addr);
 308 }
 309
 310 void __init exynos_init_late(void)
 311 {
 312         if (of_machine_is_compatible("samsung,exynos5440"))
 313                 /* to be supported later */
 314                 return;
 315
 316         exynos_pm_late_initcall();
 317 }
 318
 319 /*
 320  * exynos_map_io
 321  *
 322  * register the standard cpu IO areas
 323  */
 324
 325 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 326 {
 327         struct map_desc *iodesc = exynos_iodesc;
 328         int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
 329 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
 330         unsigned long root = of_get_flat_dt_root();
 331
 332         /* initialize the io descriptors we need for initialization */
 333         if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
 334                 iodesc = exynos5440_iodesc;
 335                 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
 336         }
 337 #endif
 338
 339         iotable_init(iodesc, iodesc_sz);
 340
 341         if (mach_desc)
 342                 iotable_init(mach_desc, size);
 343
 344         /* detect cpu id and rev. */
 345         s5p_init_cpu(S5P_VA_CHIPID);
 346
 347         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 348 }
 349
 350 static void __init exynos4_map_io(void)
 351 {
 352         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 353
 354         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 355                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 356         else
 357                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 358
 359         /* initialize device information early */
 360         exynos4_default_sdhci0();
 361         exynos4_default_sdhci1();
 362         exynos4_default_sdhci2();
 363         exynos4_default_sdhci3();
 364
 365         s3c_adc_setname("samsung-adc-v3");
 366
 367         s3c_fimc_setname(0, "exynos4-fimc");
 368         s3c_fimc_setname(1, "exynos4-fimc");
 369         s3c_fimc_setname(2, "exynos4-fimc");
 370         s3c_fimc_setname(3, "exynos4-fimc");
 371
 372         s3c_sdhci_setname(0, "exynos4-sdhci");
 373         s3c_sdhci_setname(1, "exynos4-sdhci");
 374         s3c_sdhci_setname(2, "exynos4-sdhci");
 375         s3c_sdhci_setname(3, "exynos4-sdhci");
 376
 377         /* The I2C bus controllers are directly compatible with s3c2440 */
 378         s3c_i2c0_setname("s3c2440-i2c");
 379         s3c_i2c1_setname("s3c2440-i2c");
 380         s3c_i2c2_setname("s3c2440-i2c");
 381
 382         s5p_fb_setname(0, "exynos4-fb");
 383         s5p_hdmi_setname("exynos4-hdmi");
 384
 385         s3c64xx_spi_setname("exynos4210-spi");
 386 }
 387
 388 static void __init exynos5_map_io(void)
 389 {
 390         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 391 }
 392
 393 static void __init exynos5440_map_io(void)
 394 {
 395         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 396 }
 397
 398 void __init exynos4_init_irq(void)
 399 {
 400         unsigned int gic_bank_offset;
 401
 402         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 403
 404         if (!of_have_populated_dt())
 405                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 406 #ifdef CONFIG_OF
 407         else
 408                 irqchip_init();
 409 #endif
 410
 411         if (!of_have_populated_dt())
 412                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 413
 414         /*
 415          * The parameters of s5p_init_irq() are for VIC init.
 416          * Theses parameters should be NULL and 0 because EXYNOS4
 417          * uses GIC instead of VIC.
 418          */
 419         s5p_init_irq(NULL, 0);
 420 }
 421
 422 void __init exynos5_init_irq(void)
 423 {
 424 #ifdef CONFIG_OF
 425         irqchip_init();
 426 #endif
 427         /*
 428          * The parameters of s5p_init_irq() are for VIC init.
 429          * Theses parameters should be NULL and 0 because EXYNOS4
 430          * uses GIC instead of VIC.
 431          */
 432         if (!of_machine_is_compatible("samsung,exynos5440"))
 433                 s5p_init_irq(NULL, 0);
 434
 435         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 436 }
 437
 438 struct bus_type exynos_subsys = {
 439         .name           = "exynos-core",
 440         .dev_name       = "exynos-core",
 441 };
 442
 443 static struct device exynos4_dev = {
 444         .bus    = &exynos_subsys,
 445 };
 446
 447 static int __init exynos_core_init(void)
 448 {
 449         return subsys_system_register(&exynos_subsys, NULL);
 450 }
 451 core_initcall(exynos_core_init);
 452
 453 #ifdef CONFIG_CACHE_L2X0
 454 static int __init exynos4_l2x0_cache_init(void)
 455 {
 456         int ret;
 457
 458         if (soc_is_exynos5250() || soc_is_exynos5440())
 459                 return 0;
 460
 461         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 462         if (!ret) {
 463                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 464                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 465                 return 0;
 466         }
 467
 468         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 469                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 470                 /* TAG, Data Latency Control: 2 cycles */
 471                 l2x0_saved_regs.tag_latency = 0x110;
 472
 473                 if (soc_is_exynos4212() || soc_is_exynos4412())
 474                         l2x0_saved_regs.data_latency = 0x120;
 475                 else
 476                         l2x0_saved_regs.data_latency = 0x110;
 477
 478                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 479                 l2x0_saved_regs.pwr_ctrl =
 480                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 481
 482                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 483
 484                 __raw_writel(l2x0_saved_regs.tag_latency,
 485                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 486                 __raw_writel(l2x0_saved_regs.data_latency,
 487                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 488
 489                 /* L2X0 Prefetch Control */
 490                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 491                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 492
 493                 /* L2X0 Power Control */
 494                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 495                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 496
 497                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 498                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 499         }
 500
 501         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 502         return 0;
 503 }
 504 early_initcall(exynos4_l2x0_cache_init);
 505 #endif
 506
 507 static int __init exynos_init(void)
 508 {
 509         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 510
 511         return device_register(&exynos4_dev);
 512 }
 513
 514 /* uart registration process */
 515
 516 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 517 {
 518         struct s3c2410_uartcfg *tcfg = cfg;
 519         u32 ucnt;
 520
 521         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 522                 tcfg->has_fracval = 1;
 523
 524         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 525 }
 526
 527 static void __iomem *exynos_eint_base;
 528
 529 static DEFINE_SPINLOCK(eint_lock);
 530
 531 static unsigned int eint0_15_data[16];
 532
 533 static inline int exynos4_irq_to_gpio(unsigned int irq)
 534 {
 535         if (irq < IRQ_EINT(0))
 536                 return -EINVAL;
 537
 538         irq -= IRQ_EINT(0);
 539         if (irq < 8)
 540                 return EXYNOS4_GPX0(irq);
 541
 542         irq -= 8;
 543         if (irq < 8)
 544                 return EXYNOS4_GPX1(irq);
 545
 546         irq -= 8;
 547         if (irq < 8)
 548                 return EXYNOS4_GPX2(irq);
 549
 550         irq -= 8;
 551         if (irq < 8)
 552                 return EXYNOS4_GPX3(irq);
 553
 554         return -EINVAL;
 555 }
 556
 557 static inline int exynos5_irq_to_gpio(unsigned int irq)
 558 {
 559         if (irq < IRQ_EINT(0))
 560                 return -EINVAL;
 561
 562         irq -= IRQ_EINT(0);
 563         if (irq < 8)
 564                 return EXYNOS5_GPX0(irq);
 565
 566         irq -= 8;
 567         if (irq < 8)
 568                 return EXYNOS5_GPX1(irq);
 569
 570         irq -= 8;
 571         if (irq < 8)
 572                 return EXYNOS5_GPX2(irq);
 573
 574         irq -= 8;
 575         if (irq < 8)
 576                 return EXYNOS5_GPX3(irq);
 577
 578         return -EINVAL;
 579 }
 580
 581 static unsigned int exynos4_eint0_15_src_int[16] = {
 582         EXYNOS4_IRQ_EINT0,
 583         EXYNOS4_IRQ_EINT1,
 584         EXYNOS4_IRQ_EINT2,
 585         EXYNOS4_IRQ_EINT3,
 586         EXYNOS4_IRQ_EINT4,
 587         EXYNOS4_IRQ_EINT5,
 588         EXYNOS4_IRQ_EINT6,
 589         EXYNOS4_IRQ_EINT7,
 590         EXYNOS4_IRQ_EINT8,
 591         EXYNOS4_IRQ_EINT9,
 592         EXYNOS4_IRQ_EINT10,
 593         EXYNOS4_IRQ_EINT11,
 594         EXYNOS4_IRQ_EINT12,
 595         EXYNOS4_IRQ_EINT13,
 596         EXYNOS4_IRQ_EINT14,
 597         EXYNOS4_IRQ_EINT15,
 598 };
 599
 600 static unsigned int exynos5_eint0_15_src_int[16] = {
 601         EXYNOS5_IRQ_EINT0,
 602         EXYNOS5_IRQ_EINT1,
 603         EXYNOS5_IRQ_EINT2,
 604         EXYNOS5_IRQ_EINT3,
 605         EXYNOS5_IRQ_EINT4,
 606         EXYNOS5_IRQ_EINT5,
 607         EXYNOS5_IRQ_EINT6,
 608         EXYNOS5_IRQ_EINT7,
 609         EXYNOS5_IRQ_EINT8,
 610         EXYNOS5_IRQ_EINT9,
 611         EXYNOS5_IRQ_EINT10,
 612         EXYNOS5_IRQ_EINT11,
 613         EXYNOS5_IRQ_EINT12,
 614         EXYNOS5_IRQ_EINT13,
 615         EXYNOS5_IRQ_EINT14,
 616         EXYNOS5_IRQ_EINT15,
 617 };
 618 static inline void exynos_irq_eint_mask(struct irq_data *data)
 619 {
 620         u32 mask;
 621
 622         spin_lock(&eint_lock);
 623         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 624         mask |= EINT_OFFSET_BIT(data->irq);
 625         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 626         spin_unlock(&eint_lock);
 627 }
 628
 629 static void exynos_irq_eint_unmask(struct irq_data *data)
 630 {
 631         u32 mask;
 632
 633         spin_lock(&eint_lock);
 634         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 635         mask &= ~(EINT_OFFSET_BIT(data->irq));
 636         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 637         spin_unlock(&eint_lock);
 638 }
 639
 640 static inline void exynos_irq_eint_ack(struct irq_data *data)
 641 {
 642         __raw_writel(EINT_OFFSET_BIT(data->irq),
 643                      EINT_PEND(exynos_eint_base, data->irq));
 644 }
 645
 646 static void exynos_irq_eint_maskack(struct irq_data *data)
 647 {
 648         exynos_irq_eint_mask(data);
 649         exynos_irq_eint_ack(data);
 650 }
 651
 652 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 653 {
 654         int offs = EINT_OFFSET(data->irq);
 655         int shift;
 656         u32 ctrl, mask;
 657         u32 newvalue = 0;
 658
 659         switch (type) {
 660         case IRQ_TYPE_EDGE_RISING:
 661                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 662                 break;
 663
 664         case IRQ_TYPE_EDGE_FALLING:
 665                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 666                 break;
 667
 668         case IRQ_TYPE_EDGE_BOTH:
 669                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 670                 break;
 671
 672         case IRQ_TYPE_LEVEL_LOW:
 673                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 674                 break;
 675
 676         case IRQ_TYPE_LEVEL_HIGH:
 677                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 678                 break;
 679
 680         default:
 681                 printk(KERN_ERR "No such irq type %d", type);
 682                 return -EINVAL;
 683         }
 684
 685         shift = (offs & 0x7) * 4;
 686         mask = 0x7 << shift;
 687
 688         spin_lock(&eint_lock);
 689         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 690         ctrl &= ~mask;
 691         ctrl |= newvalue << shift;
 692         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 693         spin_unlock(&eint_lock);
 694
 695         if (soc_is_exynos5250())
 696                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 697         else
 698                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 699
 700         return 0;
 701 }
 702
 703 static struct irq_chip exynos_irq_eint = {
 704         .name           = "exynos-eint",
 705         .irq_mask       = exynos_irq_eint_mask,
 706         .irq_unmask     = exynos_irq_eint_unmask,
 707         .irq_mask_ack   = exynos_irq_eint_maskack,
 708         .irq_ack        = exynos_irq_eint_ack,
 709         .irq_set_type   = exynos_irq_eint_set_type,
 710 #ifdef CONFIG_PM
 711         .irq_set_wake   = s3c_irqext_wake,
 712 #endif
 713 };
 714
 715 /*
 716  * exynos4_irq_demux_eint
 717  *
 718  * This function demuxes the IRQ from from EINTs 16 to 31.
 719  * It is designed to be inlined into the specific handler
 720  * s5p_irq_demux_eintX_Y.
 721  *
 722  * Each EINT pend/mask registers handle eight of them.
 723  */
 724 static inline void exynos_irq_demux_eint(unsigned int start)
 725 {
 726         unsigned int irq;
 727
 728         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 729         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 730
 731         status &= ~mask;
 732         status &= 0xff;
 733
 734         while (status) {
 735                 irq = fls(status) - 1;
 736                 generic_handle_irq(irq + start);
 737                 status &= ~(1 << irq);
 738         }
 739 }
 740
 741 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 742 {
 743         struct irq_chip *chip = irq_get_chip(irq);
 744         chained_irq_enter(chip, desc);
 745         exynos_irq_demux_eint(IRQ_EINT(16));
 746         exynos_irq_demux_eint(IRQ_EINT(24));
 747         chained_irq_exit(chip, desc);
 748 }
 749
 750 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 751 {
 752         u32 *irq_data = irq_get_handler_data(irq);
 753         struct irq_chip *chip = irq_get_chip(irq);
 754
 755         chained_irq_enter(chip, desc);
 756         generic_handle_irq(*irq_data);
 757         chained_irq_exit(chip, desc);
 758 }
 759
 760 static int __init exynos_init_irq_eint(void)
 761 {
 762         int irq;
 763
 764 #ifdef CONFIG_PINCTRL_SAMSUNG
 765         /*
 766          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
 767          * functionality along with support for external gpio and wakeup
 768          * interrupts. If the samsung pinctrl driver is enabled and includes
 769          * the wakeup interrupt support, then the setting up external wakeup
 770          * interrupts here can be skipped. This check here is temporary to
 771          * allow exynos4 platforms that do not use Samsung pinctrl driver to
 772          * co-exist with platforms that do. When all of the Samsung Exynos4
 773          * platforms switch over to using the pinctrl driver, the wakeup
 774          * interrupt support code here can be completely removed.
 775          */
 776         static const struct of_device_id exynos_pinctrl_ids[] = {
 777                 { .compatible = "samsung,exynos4210-pinctrl", },
 778                 { .compatible = "samsung,exynos4x12-pinctrl", },
 779         };
 780         struct device_node *pctrl_np, *wkup_np;
 781         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
 782
 783         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
 784                 if (of_device_is_available(pctrl_np)) {
 785                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
 786                                                         wkup_compat);
 787                         if (wkup_np)
 788                                 return -ENODEV;
 789                 }
 790         }
 791 #endif
 792         if (soc_is_exynos5440())
 793                 return 0;
 794
 795         if (soc_is_exynos5250())
 796                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 797         else
 798                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 799
 800         if (exynos_eint_base == NULL) {
 801                 pr_err("unable to ioremap for EINT base address\n");
 802                 return -ENOMEM;
 803         }
 804
 805         for (irq = 0 ; irq <= 31 ; irq++) {
 806                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 807                                          handle_level_irq);
 808                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 809         }
 810
 811         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 812
 813         for (irq = 0 ; irq <= 15 ; irq++) {
 814                 eint0_15_data[irq] = IRQ_EINT(irq);
 815
 816                 if (soc_is_exynos5250()) {
 817                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
 818                                              &eint0_15_data[irq]);
 819                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
 820                                                 exynos_irq_eint0_15);
 821                 } else {
 822                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
 823                                              &eint0_15_data[irq]);
 824                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
 825                                                 exynos_irq_eint0_15);
 826                 }
 827         }
 828
 829         return 0;
 830 }
 831 arch_initcall(exynos_init_irq_eint);