2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Common Codes for EXYNOS
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/irqchip.h>
17 #include <linux/device.h>
18 #include <linux/gpio.h>
19 #include <linux/sched.h>
20 #include <linux/serial_core.h>
22 #include <linux/of_fdt.h>
23 #include <linux/of_irq.h>
24 #include <linux/export.h>
25 #include <linux/irqdomain.h>
26 #include <linux/irqchip.h>
27 #include <linux/of_address.h>
28 #include <linux/irqchip/arm-gic.h>
30 #include <asm/proc-fns.h>
31 #include <asm/exception.h>
32 #include <asm/hardware/cache-l2x0.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/irq.h>
35 #include <asm/cacheflush.h>
37 #include <mach/regs-irq.h>
38 #include <mach/regs-pmu.h>
39 #include <mach/regs-gpio.h>
42 #include <plat/clock.h>
43 #include <plat/devs.h>
45 #include <plat/sdhci.h>
46 #include <plat/gpio-cfg.h>
47 #include <plat/adc-core.h>
48 #include <plat/fb-core.h>
49 #include <plat/fimc-core.h>
50 #include <plat/iic-core.h>
51 #include <plat/tv-core.h>
52 #include <plat/spi-core.h>
53 #include <plat/regs-serial.h>
56 #define L2_AUX_VAL 0x7C470001
57 #define L2_AUX_MASK 0xC200ffff
59 static const char name_exynos4210[] = "EXYNOS4210";
60 static const char name_exynos4212[] = "EXYNOS4212";
61 static const char name_exynos4412[] = "EXYNOS4412";
62 static const char name_exynos5250[] = "EXYNOS5250";
63 static const char name_exynos5440[] = "EXYNOS5440";
65 static void exynos4_map_io(void);
66 static void exynos5_map_io(void);
67 static void exynos5440_map_io(void);
68 static void exynos4_init_clocks(int xtal);
69 static void exynos5_init_clocks(int xtal);
70 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
71 static int exynos_init(void);
73 static struct cpu_table cpu_ids[] __initdata = {
75 .idcode = EXYNOS4210_CPU_ID,
76 .idmask = EXYNOS4_CPU_MASK,
77 .map_io = exynos4_map_io,
78 .init_clocks = exynos4_init_clocks,
79 .init_uarts = exynos4_init_uarts,
81 .name = name_exynos4210,
83 .idcode = EXYNOS4212_CPU_ID,
84 .idmask = EXYNOS4_CPU_MASK,
85 .map_io = exynos4_map_io,
86 .init_clocks = exynos4_init_clocks,
87 .init_uarts = exynos4_init_uarts,
89 .name = name_exynos4212,
91 .idcode = EXYNOS4412_CPU_ID,
92 .idmask = EXYNOS4_CPU_MASK,
93 .map_io = exynos4_map_io,
94 .init_clocks = exynos4_init_clocks,
95 .init_uarts = exynos4_init_uarts,
97 .name = name_exynos4412,
99 .idcode = EXYNOS5250_SOC_ID,
100 .idmask = EXYNOS5_SOC_MASK,
101 .map_io = exynos5_map_io,
102 .init_clocks = exynos5_init_clocks,
104 .name = name_exynos5250,
106 .idcode = EXYNOS5440_SOC_ID,
107 .idmask = EXYNOS5_SOC_MASK,
108 .map_io = exynos5440_map_io,
110 .name = name_exynos5440,
114 /* Initial IO mappings */
116 static struct map_desc exynos_iodesc[] __initdata = {
118 .virtual = (unsigned long)S5P_VA_CHIPID,
119 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
125 #ifdef CONFIG_ARCH_EXYNOS5
126 static struct map_desc exynos5440_iodesc[] __initdata = {
128 .virtual = (unsigned long)S5P_VA_CHIPID,
129 .pfn = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
136 static struct map_desc exynos4_iodesc[] __initdata = {
138 .virtual = (unsigned long)S3C_VA_SYS,
139 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
143 .virtual = (unsigned long)S3C_VA_TIMER,
144 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
148 .virtual = (unsigned long)S3C_VA_WATCHDOG,
149 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
153 .virtual = (unsigned long)S5P_VA_SROMC,
154 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
158 .virtual = (unsigned long)S5P_VA_SYSTIMER,
159 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
163 .virtual = (unsigned long)S5P_VA_PMU,
164 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
168 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
169 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
173 .virtual = (unsigned long)S5P_VA_GIC_CPU,
174 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
178 .virtual = (unsigned long)S5P_VA_GIC_DIST,
179 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
183 .virtual = (unsigned long)S3C_VA_UART,
184 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
188 .virtual = (unsigned long)S5P_VA_CMU,
189 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
193 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
194 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
198 .virtual = (unsigned long)S5P_VA_L2CC,
199 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
203 .virtual = (unsigned long)S5P_VA_DMC0,
204 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
208 .virtual = (unsigned long)S5P_VA_DMC1,
209 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
213 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
214 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
220 static struct map_desc exynos4_iodesc0[] __initdata = {
222 .virtual = (unsigned long)S5P_VA_SYSRAM,
223 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
229 static struct map_desc exynos4_iodesc1[] __initdata = {
231 .virtual = (unsigned long)S5P_VA_SYSRAM,
232 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
238 static struct map_desc exynos5_iodesc[] __initdata = {
240 .virtual = (unsigned long)S3C_VA_SYS,
241 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
245 .virtual = (unsigned long)S3C_VA_TIMER,
246 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
250 .virtual = (unsigned long)S3C_VA_WATCHDOG,
251 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
255 .virtual = (unsigned long)S5P_VA_SROMC,
256 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
260 .virtual = (unsigned long)S5P_VA_SYSTIMER,
261 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
265 .virtual = (unsigned long)S5P_VA_SYSRAM,
266 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
270 .virtual = (unsigned long)S5P_VA_CMU,
271 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
272 .length = 144 * SZ_1K,
275 .virtual = (unsigned long)S5P_VA_PMU,
276 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
280 .virtual = (unsigned long)S3C_VA_UART,
281 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
287 static struct map_desc exynos5440_iodesc0[] __initdata = {
289 .virtual = (unsigned long)S3C_VA_UART,
290 .pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
296 void exynos4_restart(char mode, const char *cmd)
298 __raw_writel(0x1, S5P_SWRESET);
301 void exynos5_restart(char mode, const char *cmd)
303 struct device_node *np;
307 if (of_machine_is_compatible("samsung,exynos5250")) {
309 addr = EXYNOS_SWRESET;
310 } else if (of_machine_is_compatible("samsung,exynos5440")) {
311 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
312 addr = of_iomap(np, 0) + 0xcc;
313 val = (0xfff << 20) | (0x1 << 16);
315 pr_err("%s: cannot support non-DT\n", __func__);
319 __raw_writel(val, addr);
322 void __init exynos_init_late(void)
324 if (of_machine_is_compatible("samsung,exynos5440"))
325 /* to be supported later */
328 exynos_pm_late_initcall();
334 * register the standard cpu IO areas
337 void __init exynos_init_io(struct map_desc *mach_desc, int size)
339 struct map_desc *iodesc = exynos_iodesc;
340 int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
341 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
342 unsigned long root = of_get_flat_dt_root();
344 /* initialize the io descriptors we need for initialization */
345 if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
346 iodesc = exynos5440_iodesc;
347 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
351 iotable_init(iodesc, iodesc_sz);
354 iotable_init(mach_desc, size);
356 /* detect cpu id and rev. */
357 s5p_init_cpu(S5P_VA_CHIPID);
359 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
362 static void __init exynos4_map_io(void)
364 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
366 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
367 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
369 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
371 if (!IS_ENABLED(CONFIG_EXYNOS_ATAGS))
374 /* initialize device information early */
375 exynos4_default_sdhci0();
376 exynos4_default_sdhci1();
377 exynos4_default_sdhci2();
378 exynos4_default_sdhci3();
380 s3c_adc_setname("samsung-adc-v3");
382 s3c_fimc_setname(0, "exynos4-fimc");
383 s3c_fimc_setname(1, "exynos4-fimc");
384 s3c_fimc_setname(2, "exynos4-fimc");
385 s3c_fimc_setname(3, "exynos4-fimc");
387 s3c_sdhci_setname(0, "exynos4-sdhci");
388 s3c_sdhci_setname(1, "exynos4-sdhci");
389 s3c_sdhci_setname(2, "exynos4-sdhci");
390 s3c_sdhci_setname(3, "exynos4-sdhci");
392 /* The I2C bus controllers are directly compatible with s3c2440 */
393 s3c_i2c0_setname("s3c2440-i2c");
394 s3c_i2c1_setname("s3c2440-i2c");
395 s3c_i2c2_setname("s3c2440-i2c");
397 s5p_fb_setname(0, "exynos4-fb");
398 s5p_hdmi_setname("exynos4-hdmi");
400 s3c64xx_spi_setname("exynos4210-spi");
403 static void __init exynos5_map_io(void)
405 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
408 static void __init exynos4_init_clocks(int xtal)
410 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
412 s3c24xx_register_baseclocks(xtal);
413 s5p_register_clocks(xtal);
415 if (soc_is_exynos4210())
416 exynos4210_register_clocks();
417 else if (soc_is_exynos4212() || soc_is_exynos4412())
418 exynos4212_register_clocks();
420 exynos4_register_clocks();
421 exynos4_setup_clocks();
424 static void __init exynos5440_map_io(void)
426 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
429 static void __init exynos5_init_clocks(int xtal)
431 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
433 /* EXYNOS5440 can support only common clock framework */
435 if (soc_is_exynos5440())
438 #ifdef CONFIG_SOC_EXYNOS5250
439 s3c24xx_register_baseclocks(xtal);
440 s5p_register_clocks(xtal);
442 exynos5_register_clocks();
443 exynos5_setup_clocks();
447 void __init exynos4_init_irq(void)
449 unsigned int gic_bank_offset;
451 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
453 if (!of_have_populated_dt())
454 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
460 if (!of_have_populated_dt())
461 combiner_init(S5P_VA_COMBINER_BASE, NULL);
464 * The parameters of s5p_init_irq() are for VIC init.
465 * Theses parameters should be NULL and 0 because EXYNOS4
466 * uses GIC instead of VIC.
468 s5p_init_irq(NULL, 0);
471 void __init exynos5_init_irq(void)
477 * The parameters of s5p_init_irq() are for VIC init.
478 * Theses parameters should be NULL and 0 because EXYNOS4
479 * uses GIC instead of VIC.
481 if (!of_machine_is_compatible("samsung,exynos5440"))
482 s5p_init_irq(NULL, 0);
484 gic_arch_extn.irq_set_wake = s3c_irq_wake;
487 struct bus_type exynos_subsys = {
488 .name = "exynos-core",
489 .dev_name = "exynos-core",
492 static struct device exynos4_dev = {
493 .bus = &exynos_subsys,
496 static int __init exynos_core_init(void)
498 return subsys_system_register(&exynos_subsys, NULL);
500 core_initcall(exynos_core_init);
502 #ifdef CONFIG_CACHE_L2X0
503 static int __init exynos4_l2x0_cache_init(void)
507 if (soc_is_exynos5250() || soc_is_exynos5440())
510 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
512 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
513 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
517 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
518 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
519 /* TAG, Data Latency Control: 2 cycles */
520 l2x0_saved_regs.tag_latency = 0x110;
522 if (soc_is_exynos4212() || soc_is_exynos4412())
523 l2x0_saved_regs.data_latency = 0x120;
525 l2x0_saved_regs.data_latency = 0x110;
527 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
528 l2x0_saved_regs.pwr_ctrl =
529 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
531 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
533 __raw_writel(l2x0_saved_regs.tag_latency,
534 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
535 __raw_writel(l2x0_saved_regs.data_latency,
536 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
538 /* L2X0 Prefetch Control */
539 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
540 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
542 /* L2X0 Power Control */
543 __raw_writel(l2x0_saved_regs.pwr_ctrl,
544 S5P_VA_L2CC + L2X0_POWER_CTRL);
546 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
547 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
550 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
553 early_initcall(exynos4_l2x0_cache_init);
556 static int __init exynos_init(void)
558 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
560 return device_register(&exynos4_dev);
563 /* uart registration process */
565 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
567 struct s3c2410_uartcfg *tcfg = cfg;
570 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
571 tcfg->has_fracval = 1;
573 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
577 #ifdef CONFIG_EXYNOS_ATAGS
578 static void __iomem *exynos_eint_base;
580 static DEFINE_SPINLOCK(eint_lock);
582 static unsigned int eint0_15_data[16];
584 static inline int exynos4_irq_to_gpio(unsigned int irq)
586 if (irq < IRQ_EINT(0))
591 return EXYNOS4_GPX0(irq);
595 return EXYNOS4_GPX1(irq);
599 return EXYNOS4_GPX2(irq);
603 return EXYNOS4_GPX3(irq);
608 static inline int exynos5_irq_to_gpio(unsigned int irq)
610 if (irq < IRQ_EINT(0))
615 return EXYNOS5_GPX0(irq);
619 return EXYNOS5_GPX1(irq);
623 return EXYNOS5_GPX2(irq);
627 return EXYNOS5_GPX3(irq);
632 static unsigned int exynos4_eint0_15_src_int[16] = {
651 static unsigned int exynos5_eint0_15_src_int[16] = {
669 static inline void exynos_irq_eint_mask(struct irq_data *data)
673 spin_lock(&eint_lock);
674 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
675 mask |= EINT_OFFSET_BIT(data->irq);
676 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
677 spin_unlock(&eint_lock);
680 static void exynos_irq_eint_unmask(struct irq_data *data)
684 spin_lock(&eint_lock);
685 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
686 mask &= ~(EINT_OFFSET_BIT(data->irq));
687 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
688 spin_unlock(&eint_lock);
691 static inline void exynos_irq_eint_ack(struct irq_data *data)
693 __raw_writel(EINT_OFFSET_BIT(data->irq),
694 EINT_PEND(exynos_eint_base, data->irq));
697 static void exynos_irq_eint_maskack(struct irq_data *data)
699 exynos_irq_eint_mask(data);
700 exynos_irq_eint_ack(data);
703 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
705 int offs = EINT_OFFSET(data->irq);
711 case IRQ_TYPE_EDGE_RISING:
712 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
715 case IRQ_TYPE_EDGE_FALLING:
716 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
719 case IRQ_TYPE_EDGE_BOTH:
720 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
723 case IRQ_TYPE_LEVEL_LOW:
724 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
727 case IRQ_TYPE_LEVEL_HIGH:
728 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
732 printk(KERN_ERR "No such irq type %d", type);
736 shift = (offs & 0x7) * 4;
739 spin_lock(&eint_lock);
740 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
742 ctrl |= newvalue << shift;
743 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
744 spin_unlock(&eint_lock);
746 if (soc_is_exynos5250())
747 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
749 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
754 static struct irq_chip exynos_irq_eint = {
755 .name = "exynos-eint",
756 .irq_mask = exynos_irq_eint_mask,
757 .irq_unmask = exynos_irq_eint_unmask,
758 .irq_mask_ack = exynos_irq_eint_maskack,
759 .irq_ack = exynos_irq_eint_ack,
760 .irq_set_type = exynos_irq_eint_set_type,
762 .irq_set_wake = s3c_irqext_wake,
767 * exynos4_irq_demux_eint
769 * This function demuxes the IRQ from from EINTs 16 to 31.
770 * It is designed to be inlined into the specific handler
771 * s5p_irq_demux_eintX_Y.
773 * Each EINT pend/mask registers handle eight of them.
775 static inline void exynos_irq_demux_eint(unsigned int start)
779 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
780 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
786 irq = fls(status) - 1;
787 generic_handle_irq(irq + start);
788 status &= ~(1 << irq);
792 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
794 struct irq_chip *chip = irq_get_chip(irq);
795 chained_irq_enter(chip, desc);
796 exynos_irq_demux_eint(IRQ_EINT(16));
797 exynos_irq_demux_eint(IRQ_EINT(24));
798 chained_irq_exit(chip, desc);
801 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
803 u32 *irq_data = irq_get_handler_data(irq);
804 struct irq_chip *chip = irq_get_chip(irq);
806 chained_irq_enter(chip, desc);
807 generic_handle_irq(*irq_data);
808 chained_irq_exit(chip, desc);
811 static int __init exynos_init_irq_eint(void)
815 #ifdef CONFIG_PINCTRL_SAMSUNG
817 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
818 * functionality along with support for external gpio and wakeup
819 * interrupts. If the samsung pinctrl driver is enabled and includes
820 * the wakeup interrupt support, then the setting up external wakeup
821 * interrupts here can be skipped. This check here is temporary to
822 * allow exynos4 platforms that do not use Samsung pinctrl driver to
823 * co-exist with platforms that do. When all of the Samsung Exynos4
824 * platforms switch over to using the pinctrl driver, the wakeup
825 * interrupt support code here can be completely removed.
827 static const struct of_device_id exynos_pinctrl_ids[] = {
828 { .compatible = "samsung,exynos4210-pinctrl", },
829 { .compatible = "samsung,exynos4x12-pinctrl", },
831 struct device_node *pctrl_np, *wkup_np;
832 const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
834 for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
835 if (of_device_is_available(pctrl_np)) {
836 wkup_np = of_find_compatible_node(pctrl_np, NULL,
843 if (soc_is_exynos5440())
846 if (soc_is_exynos5250())
847 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
849 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
851 if (exynos_eint_base == NULL) {
852 pr_err("unable to ioremap for EINT base address\n");
856 for (irq = 0 ; irq <= 31 ; irq++) {
857 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
859 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
862 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
864 for (irq = 0 ; irq <= 15 ; irq++) {
865 eint0_15_data[irq] = IRQ_EINT(irq);
867 if (soc_is_exynos5250()) {
868 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
869 &eint0_15_data[irq]);
870 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
871 exynos_irq_eint0_15);
873 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
874 &eint0_15_data[irq]);
875 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
876 exynos_irq_eint0_15);
882 arch_initcall(exynos_init_irq_eint);