2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
7 * Copyright (C) 2002 ARM Ltd.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/jiffies.h>
20 #include <linux/smp.h>
22 #include <linux/of_address.h>
24 #include <asm/cacheflush.h>
26 #include <asm/smp_plat.h>
27 #include <asm/smp_scu.h>
28 #include <asm/firmware.h>
35 extern void exynos4_secondary_startup(void);
37 #ifdef CONFIG_HOTPLUG_CPU
38 static inline void cpu_leave_lowpower(u32 core_id)
43 "mrc p15, 0, %0, c1, c0, 0\n"
45 " mcr p15, 0, %0, c1, c0, 0\n"
46 " mrc p15, 0, %0, c1, c0, 1\n"
48 " mcr p15, 0, %0, c1, c0, 1\n"
50 : "Ir" (CR_C), "Ir" (0x40)
54 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
56 u32 mpidr = cpu_logical_map(cpu);
57 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
61 /* Turn the CPU off on next WFI instruction. */
62 exynos_cpu_power_down(core_id);
66 if (pen_release == core_id) {
68 * OK, proper wakeup, we're done
74 * Getting here, means that we have come out of WFI without
75 * having been woken up - this shouldn't happen
77 * Just note it happening - when we're woken, we can report
83 #endif /* CONFIG_HOTPLUG_CPU */
86 * exynos_core_power_down : power down the specified cpu
87 * @cpu : the cpu to power down
89 * Power down the specified cpu. The sequence must be finished by a
90 * call to cpu_do_idle()
93 void exynos_cpu_power_down(int cpu)
97 if (cpu == 0 && (soc_is_exynos5420() || soc_is_exynos5800())) {
99 * Bypass power down for CPU0 during suspend. Check for
100 * the SYS_PWR_REG value to decide if we are suspending
103 int val = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
105 if (!(val & S5P_CORE_LOCAL_PWR_EN))
109 core_conf = pmu_raw_readl(EXYNOS_ARM_CORE_CONFIGURATION(cpu));
110 core_conf &= ~S5P_CORE_LOCAL_PWR_EN;
111 pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
115 * exynos_cpu_power_up : power up the specified cpu
116 * @cpu : the cpu to power up
118 * Power up the specified cpu
120 void exynos_cpu_power_up(int cpu)
122 u32 core_conf = S5P_CORE_LOCAL_PWR_EN;
124 if (soc_is_exynos3250())
125 core_conf |= S5P_CORE_AUTOWAKEUP_EN;
127 pmu_raw_writel(core_conf,
128 EXYNOS_ARM_CORE_CONFIGURATION(cpu));
132 * exynos_cpu_power_state : returns the power state of the cpu
133 * @cpu : the cpu to retrieve the power state from
136 int exynos_cpu_power_state(int cpu)
138 return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
139 S5P_CORE_LOCAL_PWR_EN);
143 * exynos_cluster_power_down : power down the specified cluster
144 * @cluster : the cluster to power down
146 void exynos_cluster_power_down(int cluster)
148 pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
152 * exynos_cluster_power_up : power up the specified cluster
153 * @cluster : the cluster to power up
155 void exynos_cluster_power_up(int cluster)
157 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
158 EXYNOS_COMMON_CONFIGURATION(cluster));
162 * exynos_cluster_power_state : returns the power state of the cluster
163 * @cluster : the cluster to retrieve the power state from
166 int exynos_cluster_power_state(int cluster)
168 return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
169 S5P_CORE_LOCAL_PWR_EN);
172 void __iomem *cpu_boot_reg_base(void)
174 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
175 return pmu_base_addr + S5P_INFORM5;
176 return sysram_base_addr;
179 static inline void __iomem *cpu_boot_reg(int cpu)
181 void __iomem *boot_reg;
183 boot_reg = cpu_boot_reg_base();
185 return ERR_PTR(-ENODEV);
186 if (soc_is_exynos4412())
188 else if (soc_is_exynos5420() || soc_is_exynos5800())
194 * Set wake up by local power mode and execute software reset for given core.
196 * Currently this is needed only when booting secondary CPU on Exynos3250.
198 static void exynos_core_restart(u32 core_id)
202 if (!of_machine_is_compatible("samsung,exynos3250"))
205 while (!pmu_raw_readl(S5P_PMU_SPARE2))
209 val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
210 val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
211 pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
213 pmu_raw_writel(EXYNOS_CORE_PO_RESET(core_id), EXYNOS_SWRESET);
217 * Write pen_release in a way that is guaranteed to be visible to all
218 * observers, irrespective of whether they're taking part in coherency
219 * or not. This is necessary for the hotplug code to work reliably.
221 static void write_pen_release(int val)
225 sync_cache_w(&pen_release);
228 static void __iomem *scu_base_addr(void)
230 return (void __iomem *)(S5P_VA_SCU);
233 static DEFINE_SPINLOCK(boot_lock);
235 static void exynos_secondary_init(unsigned int cpu)
238 * let the primary processor know we're out of the
239 * pen, then head off into the C entry point
241 write_pen_release(-1);
244 * Synchronise with the boot thread.
246 spin_lock(&boot_lock);
247 spin_unlock(&boot_lock);
250 static int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
255 * Try to set boot address using firmware first
256 * and fall back to boot register if it fails.
258 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
259 if (ret && ret != -ENOSYS)
261 if (ret == -ENOSYS) {
262 void __iomem *boot_reg = cpu_boot_reg(core_id);
264 if (IS_ERR(boot_reg)) {
265 ret = PTR_ERR(boot_reg);
268 __raw_writel(boot_addr, boot_reg);
275 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
277 unsigned long timeout;
278 u32 mpidr = cpu_logical_map(cpu);
279 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
283 * Set synchronisation state between this boot processor
284 * and the secondary one
286 spin_lock(&boot_lock);
289 * The secondary processor is waiting to be released from
290 * the holding pen - release it, then wait for it to flag
291 * that it has been released by resetting pen_release.
293 * Note that "pen_release" is the hardware CPU core ID, whereas
294 * "cpu" is Linux's internal ID.
296 write_pen_release(core_id);
298 if (!exynos_cpu_power_state(core_id)) {
299 exynos_cpu_power_up(core_id);
302 /* wait max 10 ms until cpu1 is on */
303 while (exynos_cpu_power_state(core_id)
304 != S5P_CORE_LOCAL_PWR_EN) {
312 printk(KERN_ERR "cpu1 power enable failed");
313 spin_unlock(&boot_lock);
318 exynos_core_restart(core_id);
321 * Send the secondary CPU a soft interrupt, thereby causing
322 * the boot monitor to read the system wide flags register,
323 * and branch to the address found there.
326 timeout = jiffies + (1 * HZ);
327 while (time_before(jiffies, timeout)) {
328 unsigned long boot_addr;
332 boot_addr = virt_to_phys(exynos4_secondary_startup);
334 ret = exynos_set_boot_addr(core_id, boot_addr);
338 call_firmware_op(cpu_boot, core_id);
340 if (soc_is_exynos3250())
343 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
345 if (pen_release == -1)
351 if (pen_release != -1)
355 * now the secondary core is starting up let it run its
356 * calibrations, then wait for it to finish
359 spin_unlock(&boot_lock);
361 return pen_release != -1 ? ret : 0;
365 * Initialise the CPU possible map early - this describes the CPUs
366 * which may be present or become present in the system.
369 static void __init exynos_smp_init_cpus(void)
371 void __iomem *scu_base = scu_base_addr();
372 unsigned int i, ncores;
374 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
375 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
378 * CPU Nodes are passed thru DT and set_cpu_possible
379 * is set by "arm_dt_init_cpu_maps".
384 if (ncores > nr_cpu_ids) {
385 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
390 for (i = 0; i < ncores; i++)
391 set_cpu_possible(i, true);
394 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
398 exynos_sysram_init();
400 exynos_set_delayed_reset_assertion(true);
402 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
403 scu_enable(scu_base_addr());
406 * Write the address of secondary startup into the
407 * system-wide flags register. The boot monitor waits
408 * until it receives a soft interrupt, and then the
409 * secondary CPU branches to this address.
411 * Try using firmware operation first and fall back to
412 * boot register if it fails.
414 for (i = 1; i < max_cpus; ++i) {
415 unsigned long boot_addr;
420 mpidr = cpu_logical_map(i);
421 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
422 boot_addr = virt_to_phys(exynos4_secondary_startup);
424 ret = exynos_set_boot_addr(core_id, boot_addr);
430 #ifdef CONFIG_HOTPLUG_CPU
432 * platform-specific code to shutdown a CPU
434 * Called with IRQs disabled
436 static void exynos_cpu_die(unsigned int cpu)
439 u32 mpidr = cpu_logical_map(cpu);
440 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
442 v7_exit_coherency_flush(louis);
444 platform_do_lowpower(cpu, &spurious);
447 * bring this CPU back into the world of cache
448 * coherency, and then restore interrupts
450 cpu_leave_lowpower(core_id);
453 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
455 #endif /* CONFIG_HOTPLUG_CPU */
457 struct smp_operations exynos_smp_ops __initdata = {
458 .smp_init_cpus = exynos_smp_init_cpus,
459 .smp_prepare_cpus = exynos_smp_prepare_cpus,
460 .smp_secondary_init = exynos_secondary_init,
461 .smp_boot_secondary = exynos_boot_secondary,
462 #ifdef CONFIG_HOTPLUG_CPU
463 .cpu_die = exynos_cpu_die,