arch/arm/mach-exynos/platsmp.c

   1 /* linux/arch/arm/mach-exynos4/platsmp.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
   7  *
   8  *  Copyright (C) 2002 ARM Ltd.
   9  *  All Rights Reserved
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/delay.h>
  19 #include <linux/device.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/smp.h>
  22 #include <linux/io.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/smp_plat.h>
  26 #include <asm/smp_scu.h>
  27 #include <asm/firmware.h>
  28
  29 #include "common.h"
  30 #include "regs-pmu.h"
  31
  32 extern void exynos4_secondary_startup(void);
  33
  34 static inline void __iomem *cpu_boot_reg_base(void)
  35 {
  36         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
  37                 return S5P_INFORM5;
  38         return S5P_VA_SYSRAM;
  39 }
  40
  41 static inline void __iomem *cpu_boot_reg(int cpu)
  42 {
  43         void __iomem *boot_reg;
  44
  45         boot_reg = cpu_boot_reg_base();
  46         if (soc_is_exynos4412())
  47                 boot_reg += 4*cpu;
  48         else if (soc_is_exynos5420())
  49                 boot_reg += 4;
  50         return boot_reg;
  51 }
  52
  53 /*
  54  * Write pen_release in a way that is guaranteed to be visible to all
  55  * observers, irrespective of whether they're taking part in coherency
  56  * or not.  This is necessary for the hotplug code to work reliably.
  57  */
  58 static void write_pen_release(int val)
  59 {
  60         pen_release = val;
  61         smp_wmb();
  62         sync_cache_w(&pen_release);
  63 }
  64
  65 static void __iomem *scu_base_addr(void)
  66 {
  67         return (void __iomem *)(S5P_VA_SCU);
  68 }
  69
  70 static DEFINE_SPINLOCK(boot_lock);
  71
  72 static void exynos_secondary_init(unsigned int cpu)
  73 {
  74         /*
  75          * let the primary processor know we're out of the
  76          * pen, then head off into the C entry point
  77          */
  78         write_pen_release(-1);
  79
  80         /*
  81          * Synchronise with the boot thread.
  82          */
  83         spin_lock(&boot_lock);
  84         spin_unlock(&boot_lock);
  85 }
  86
  87 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
  88 {
  89         unsigned long timeout;
  90         unsigned long phys_cpu = cpu_logical_map(cpu);
  91
  92         /*
  93          * Set synchronisation state between this boot processor
  94          * and the secondary one
  95          */
  96         spin_lock(&boot_lock);
  97
  98         /*
  99          * The secondary processor is waiting to be released from
 100          * the holding pen - release it, then wait for it to flag
 101          * that it has been released by resetting pen_release.
 102          *
 103          * Note that "pen_release" is the hardware CPU ID, whereas
 104          * "cpu" is Linux's internal ID.
 105          */
 106         write_pen_release(phys_cpu);
 107
 108         if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
 109                 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
 110                              S5P_ARM_CORE1_CONFIGURATION);
 111
 112                 timeout = 10;
 113
 114                 /* wait max 10 ms until cpu1 is on */
 115                 while ((__raw_readl(S5P_ARM_CORE1_STATUS)
 116                         & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
 117                         if (timeout-- == 0)
 118                                 break;
 119
 120                         mdelay(1);
 121                 }
 122
 123                 if (timeout == 0) {
 124                         printk(KERN_ERR "cpu1 power enable failed");
 125                         spin_unlock(&boot_lock);
 126                         return -ETIMEDOUT;
 127                 }
 128         }
 129         /*
 130          * Send the secondary CPU a soft interrupt, thereby causing
 131          * the boot monitor to read the system wide flags register,
 132          * and branch to the address found there.
 133          */
 134
 135         timeout = jiffies + (1 * HZ);
 136         while (time_before(jiffies, timeout)) {
 137                 unsigned long boot_addr;
 138
 139                 smp_rmb();
 140
 141                 boot_addr = virt_to_phys(exynos4_secondary_startup);
 142
 143                 /*
 144                  * Try to set boot address using firmware first
 145                  * and fall back to boot register if it fails.
 146                  */
 147                 if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
 148                         __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
 149
 150                 call_firmware_op(cpu_boot, phys_cpu);
 151
 152                 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 153
 154                 if (pen_release == -1)
 155                         break;
 156
 157                 udelay(10);
 158         }
 159
 160         /*
 161          * now the secondary core is starting up let it run its
 162          * calibrations, then wait for it to finish
 163          */
 164         spin_unlock(&boot_lock);
 165
 166         return pen_release != -1 ? -ENOSYS : 0;
 167 }
 168
 169 /*
 170  * Initialise the CPU possible map early - this describes the CPUs
 171  * which may be present or become present in the system.
 172  */
 173
 174 static void __init exynos_smp_init_cpus(void)
 175 {
 176         void __iomem *scu_base = scu_base_addr();
 177         unsigned int i, ncores;
 178
 179         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 180                 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 181         else
 182                 /*
 183                  * CPU Nodes are passed thru DT and set_cpu_possible
 184                  * is set by "arm_dt_init_cpu_maps".
 185                  */
 186                 return;
 187
 188         /* sanity check */
 189         if (ncores > nr_cpu_ids) {
 190                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 191                         ncores, nr_cpu_ids);
 192                 ncores = nr_cpu_ids;
 193         }
 194
 195         for (i = 0; i < ncores; i++)
 196                 set_cpu_possible(i, true);
 197 }
 198
 199 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 200 {
 201         int i;
 202
 203         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 204                 scu_enable(scu_base_addr());
 205
 206         /*
 207          * Write the address of secondary startup into the
 208          * system-wide flags register. The boot monitor waits
 209          * until it receives a soft interrupt, and then the
 210          * secondary CPU branches to this address.
 211          *
 212          * Try using firmware operation first and fall back to
 213          * boot register if it fails.
 214          */
 215         for (i = 1; i < max_cpus; ++i) {
 216                 unsigned long phys_cpu;
 217                 unsigned long boot_addr;
 218
 219                 phys_cpu = cpu_logical_map(i);
 220                 boot_addr = virt_to_phys(exynos4_secondary_startup);
 221
 222                 if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
 223                         __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
 224         }
 225 }
 226
 227 struct smp_operations exynos_smp_ops __initdata = {
 228         .smp_init_cpus          = exynos_smp_init_cpus,
 229         .smp_prepare_cpus       = exynos_smp_prepare_cpus,
 230         .smp_secondary_init     = exynos_secondary_init,
 231         .smp_boot_secondary     = exynos_boot_secondary,
 232 #ifdef CONFIG_HOTPLUG_CPU
 233         .cpu_die                = exynos_cpu_die,
 234 #endif
 235 };