2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS - Power Management support
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/cpu_pm.h>
20 #include <linux/err.h>
22 #include <asm/firmware.h>
23 #include <asm/smp_scu.h>
24 #include <asm/suspend.h>
26 #include <plat/pm-common.h>
32 static inline void __iomem *exynos_boot_vector_addr(void)
34 if (samsung_rev() == EXYNOS4210_REV_1_1)
35 return pmu_base_addr + S5P_INFORM7;
36 else if (samsung_rev() == EXYNOS4210_REV_1_0)
37 return sysram_base_addr + 0x24;
38 return pmu_base_addr + S5P_INFORM0;
41 static inline void __iomem *exynos_boot_vector_flag(void)
43 if (samsung_rev() == EXYNOS4210_REV_1_1)
44 return pmu_base_addr + S5P_INFORM6;
45 else if (samsung_rev() == EXYNOS4210_REV_1_0)
46 return sysram_base_addr + 0x20;
47 return pmu_base_addr + S5P_INFORM1;
50 #define S5P_CHECK_AFTR 0xFCBA0D10
52 /* For Cortex-A9 Diagnostic and Power control register */
53 static unsigned int save_arm_register[2];
55 void exynos_cpu_save_register(void)
59 /* Save Power control register */
60 asm ("mrc p15, 0, %0, c15, c0, 0"
61 : "=r" (tmp) : : "cc");
63 save_arm_register[0] = tmp;
65 /* Save Diagnostic register */
66 asm ("mrc p15, 0, %0, c15, c0, 1"
67 : "=r" (tmp) : : "cc");
69 save_arm_register[1] = tmp;
72 void exynos_cpu_restore_register(void)
76 /* Restore Power control register */
77 tmp = save_arm_register[0];
79 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
83 /* Restore Diagnostic register */
84 tmp = save_arm_register[1];
86 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
91 void exynos_pm_central_suspend(void)
95 /* Setting Central Sequence Register for power down mode */
96 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
97 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
98 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
100 /* Setting SEQ_OPTION register */
101 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
102 S5P_CENTRAL_SEQ_OPTION);
105 int exynos_pm_central_resume(void)
110 * If PMU failed while entering sleep mode, WFI will be
111 * ignored by PMU and then exiting cpu_do_idle().
112 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
115 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
116 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
117 tmp |= S5P_CENTRAL_LOWPWR_CFG;
118 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
119 /* clear the wakeup state register */
120 pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
121 /* No need to perform below restore code */
128 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
129 static void exynos_set_wakeupmask(long mask)
131 pmu_raw_writel(mask, S5P_WAKEUP_MASK);
134 static void exynos_cpu_set_boot_vector(long flags)
136 __raw_writel(virt_to_phys(exynos_cpu_resume),
137 exynos_boot_vector_addr());
138 __raw_writel(flags, exynos_boot_vector_flag());
141 static int exynos_aftr_finisher(unsigned long flags)
145 exynos_set_wakeupmask(0x0000ff3e);
146 /* Set value of power down register for aftr mode */
147 exynos_sys_powerdown_conf(SYS_AFTR);
149 ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR);
150 if (ret == -ENOSYS) {
151 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
152 exynos_cpu_save_register();
153 exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
160 void exynos_enter_aftr(void)
164 exynos_pm_central_suspend();
166 cpu_suspend(0, exynos_aftr_finisher);
168 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
169 scu_enable(S5P_VA_SCU);
170 if (call_firmware_op(resume) == -ENOSYS)
171 exynos_cpu_restore_register();
174 exynos_pm_central_resume();