2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clkdev.h>
16 #include <linux/clocksource.h>
17 #include <linux/cpu.h>
18 #include <linux/delay.h>
19 #include <linux/export.h>
20 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/irqchip.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_platform.h>
28 #include <linux/opp.h>
29 #include <linux/phy.h>
30 #include <linux/reboot.h>
31 #include <linux/regmap.h>
32 #include <linux/micrel_phy.h>
33 #include <linux/mfd/syscon.h>
34 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
35 #include <asm/mach/arch.h>
36 #include <asm/mach/map.h>
37 #include <asm/system_misc.h>
43 static u32 chip_revision;
45 int imx6q_revision(void)
50 static void __init imx6q_init_revision(void)
52 u32 rev = imx_anatop_get_digprog();
56 chip_revision = IMX_CHIP_REVISION_1_0;
59 chip_revision = IMX_CHIP_REVISION_1_1;
62 chip_revision = IMX_CHIP_REVISION_1_2;
65 chip_revision = IMX_CHIP_REVISION_UNKNOWN;
68 mxc_set_cpu_type(rev >> 16 & 0xff);
71 static void imx6q_restart(enum reboot_mode mode, const char *cmd)
73 struct device_node *np;
74 void __iomem *wdog_base;
76 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
77 wdog_base = of_iomap(np, 0);
81 imx_src_prepare_restart();
84 writew_relaxed(1 << 2, wdog_base);
85 /* write twice to ensure the request will not get ignored */
86 writew_relaxed(1 << 2, wdog_base);
88 /* wait for reset to assert ... */
91 pr_err("Watchdog reset failed to assert reset\n");
93 /* delay to allow the serial port to show the message */
97 /* we'll take a jump through zero as a poor second */
101 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
102 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
104 if (IS_BUILTIN(CONFIG_PHYLIB)) {
105 /* min rx data delay */
106 phy_write(phydev, 0x0b, 0x8105);
107 phy_write(phydev, 0x0c, 0x0000);
109 /* max rx/tx clock delay, min rx/tx control delay */
110 phy_write(phydev, 0x0b, 0x8104);
111 phy_write(phydev, 0x0c, 0xf0f0);
112 phy_write(phydev, 0x0b, 0x104);
118 static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
120 phy_write(dev, 0x0d, device);
121 phy_write(dev, 0x0e, reg);
122 phy_write(dev, 0x0d, (1 << 14) | device);
123 phy_write(dev, 0x0e, val);
126 static int ksz9031rn_phy_fixup(struct phy_device *dev)
129 * min rx data delay, max rx/tx clock delay,
130 * min rx/tx control delay
132 mmd_write_reg(dev, 2, 4, 0);
133 mmd_write_reg(dev, 2, 5, 0);
134 mmd_write_reg(dev, 2, 8, 0x003ff);
139 static int ar8031_phy_fixup(struct phy_device *dev)
143 /* To enable AR8031 output a 125MHz clk from CLK_25M */
144 phy_write(dev, 0xd, 0x7);
145 phy_write(dev, 0xe, 0x8016);
146 phy_write(dev, 0xd, 0x4007);
148 val = phy_read(dev, 0xe);
151 phy_write(dev, 0xe, val);
153 /* introduce tx clock delay */
154 phy_write(dev, 0x1d, 0x5);
155 val = phy_read(dev, 0x1e);
157 phy_write(dev, 0x1e, val);
162 static void __init imx6q_sabrelite_cko1_setup(void)
164 struct clk *cko1_sel, *ahb, *cko1;
167 cko1_sel = clk_get_sys(NULL, "cko1_sel");
168 ahb = clk_get_sys(NULL, "ahb");
169 cko1 = clk_get_sys(NULL, "cko1");
170 if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
171 pr_err("cko1 setup failed!\n");
174 clk_set_parent(cko1_sel, ahb);
175 rate = clk_round_rate(cko1, 16000000);
176 clk_set_rate(cko1, rate);
178 if (!IS_ERR(cko1_sel))
186 #define PHY_ID_AR8031 0x004dd074
188 static void __init imx6q_enet_phy_init(void)
190 if (IS_BUILTIN(CONFIG_PHYLIB)) {
191 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
192 ksz9021rn_phy_fixup);
193 phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
194 ksz9031rn_phy_fixup);
195 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
200 static void __init imx6q_sabresd_cko1_setup(void)
202 struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
205 cko1_sel = clk_get_sys(NULL, "cko1_sel");
206 pll4 = clk_get_sys(NULL, "pll4_audio");
207 pll4_post = clk_get_sys(NULL, "pll4_post_div");
208 cko1 = clk_get_sys(NULL, "cko1");
209 if (IS_ERR(cko1_sel) || IS_ERR(pll4)
210 || IS_ERR(pll4_post) || IS_ERR(cko1)) {
211 pr_err("cko1 setup failed!\n");
215 * Setting pll4 at 768MHz (24MHz * 32)
216 * So its child clock can get 24MHz easily
218 clk_set_rate(pll4, 768000000);
220 clk_set_parent(cko1_sel, pll4_post);
221 rate = clk_round_rate(cko1, 24000000);
222 clk_set_rate(cko1, rate);
224 if (!IS_ERR(cko1_sel))
226 if (!IS_ERR(pll4_post))
234 static void __init imx6q_sabresd_init(void)
236 imx6q_sabresd_cko1_setup();
239 static void __init imx6q_1588_init(void)
243 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
245 regmap_update_bits(gpr, IOMUXC_GPR1,
246 IMX6Q_GPR1_ENET_CLK_SEL_MASK,
247 IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
249 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
252 static void __init imx6q_usb_init(void)
254 imx_anatop_usb_chrg_detect_disable();
257 static void __init imx6q_init_machine(void)
259 if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
260 imx6q_sabrelite_cko1_setup();
261 else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
262 of_machine_is_compatible("fsl,imx6dl-sabresd"))
263 imx6q_sabresd_init();
265 imx6q_enet_phy_init();
267 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
275 #define OCOTP_CFG3 0x440
276 #define OCOTP_CFG3_SPEED_SHIFT 16
277 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3
279 static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
281 struct device_node *np;
285 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
287 pr_warn("failed to find ocotp node\n");
291 base = of_iomap(np, 0);
293 pr_warn("failed to map ocotp\n");
297 val = readl_relaxed(base + OCOTP_CFG3);
298 val >>= OCOTP_CFG3_SPEED_SHIFT;
299 if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
300 if (opp_disable(cpu_dev, 1200000000))
301 pr_warn("failed to disable 1.2 GHz OPP\n");
307 static void __init imx6q_opp_init(struct device *cpu_dev)
309 struct device_node *np;
311 np = of_find_node_by_path("/cpus/cpu@0");
313 pr_warn("failed to find cpu0 node\n");
317 cpu_dev->of_node = np;
318 if (of_init_opp_table(cpu_dev)) {
319 pr_warn("failed to init OPP table\n");
323 imx6q_opp_check_1p2ghz(cpu_dev);
329 static struct platform_device imx6q_cpufreq_pdev = {
330 .name = "imx6q-cpufreq",
333 static void __init imx6q_init_late(void)
336 * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
337 * to run cpuidle on them.
339 if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
340 imx6q_cpuidle_init();
342 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
343 imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
344 platform_device_register(&imx6q_cpufreq_pdev);
348 static void __init imx6q_map_io(void)
354 static void __init imx6q_init_irq(void)
356 imx6q_init_revision();
363 static void __init imx6q_timer_init(void)
366 clocksource_of_init();
367 imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
371 static const char *imx6q_dt_compat[] __initdata = {
377 DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
378 .smp = smp_ops(imx_smp_ops),
379 .map_io = imx6q_map_io,
380 .init_irq = imx6q_init_irq,
381 .init_time = imx6q_timer_init,
382 .init_machine = imx6q_init_machine,
383 .init_late = imx6q_init_late,
384 .dt_compat = imx6q_dt_compat,
385 .restart = imx6q_restart,