2 * linux/arch/arm/mach-integrator/integrator_ap.c
4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/kmi.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/interrupt.h>
34 #include <linux/irqchip/versatile-fpga.h>
35 #include <linux/mtd/physmap.h>
36 #include <linux/clk.h>
37 #include <linux/platform_data/clk-integrator.h>
38 #include <linux/of_irq.h>
39 #include <linux/of_address.h>
40 #include <linux/of_platform.h>
41 #include <linux/stat.h>
42 #include <linux/sys_soc.h>
43 #include <linux/termios.h>
44 #include <video/vga.h>
46 #include <mach/hardware.h>
47 #include <mach/platform.h>
48 #include <asm/hardware/arm_timer.h>
49 #include <asm/setup.h>
50 #include <asm/param.h> /* HZ */
51 #include <asm/mach-types.h>
52 #include <asm/sched_clock.h>
55 #include <mach/irqs.h>
57 #include <asm/mach/arch.h>
58 #include <asm/mach/irq.h>
59 #include <asm/mach/map.h>
60 #include <asm/mach/pci.h>
61 #include <asm/mach/time.h>
65 /* Base address to the AP system controller */
66 void __iomem *ap_syscon_base;
69 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
72 * Setup a VA for the Integrator interrupt controller (for header #0,
75 #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
76 #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
77 #define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
81 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
82 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
83 * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
84 * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
85 * ef000000 Cache flush
86 * f1000000 10000000 Core module registers
87 * f1100000 11000000 System controller registers
88 * f1200000 12000000 EBI registers
89 * f1300000 13000000 Counter/Timer
90 * f1400000 14000000 Interrupt controller
91 * f1600000 16000000 UART 0
92 * f1700000 17000000 UART 1
93 * f1a00000 1a000000 Debug LEDs
94 * f1b00000 1b000000 GPIO
97 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
99 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
100 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
104 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
105 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
109 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
110 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
114 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
115 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
119 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
120 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
124 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
125 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
129 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
130 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
134 .virtual = (unsigned long)PCI_MEMORY_VADDR,
135 .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
139 .virtual = (unsigned long)PCI_CONFIG_VADDR,
140 .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
144 .virtual = (unsigned long)PCI_V3_VADDR,
145 .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
151 static void __init ap_map_io(void)
153 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
154 vga_base = (unsigned long)PCI_MEMORY_VADDR;
155 pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
159 static unsigned long ic_irq_enable;
161 static int irq_suspend(void)
163 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
167 static void irq_resume(void)
169 /* disable all irq sources */
170 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
171 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
172 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
174 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
177 #define irq_suspend NULL
178 #define irq_resume NULL
181 static struct syscore_ops irq_syscore_ops = {
182 .suspend = irq_suspend,
183 .resume = irq_resume,
186 static int __init irq_syscore_init(void)
188 register_syscore_ops(&irq_syscore_ops);
193 device_initcall(irq_syscore_init);
198 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
199 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
201 static int ap_flash_init(struct platform_device *dev)
205 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
206 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
208 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
209 writel(tmp, EBI_CSR1);
211 if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
212 writel(0xa05f, EBI_LOCK);
213 writel(tmp, EBI_CSR1);
219 static void ap_flash_exit(struct platform_device *dev)
223 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
224 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
226 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
227 writel(tmp, EBI_CSR1);
229 if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
230 writel(0xa05f, EBI_LOCK);
231 writel(tmp, EBI_CSR1);
236 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
239 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
240 ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
242 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
243 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
246 static struct physmap_flash_data ap_flash_data = {
248 .init = ap_flash_init,
249 .exit = ap_flash_exit,
250 .set_vpp = ap_flash_set_vpp,
254 * For the PL010 found in the Integrator/AP some of the UART control is
255 * implemented in the system controller and accessed using a callback
258 static void integrator_uart_set_mctrl(struct amba_device *dev,
259 void __iomem *base, unsigned int mctrl)
261 unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
262 u32 phybase = dev->res.start;
264 if (phybase == INTEGRATOR_UART0_BASE) {
274 if (mctrl & TIOCM_RTS)
279 if (mctrl & TIOCM_DTR)
284 __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
285 __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
288 struct amba_pl010_data ap_uart_data = {
289 .set_mctrl = integrator_uart_set_mctrl,
293 * Where is the timer (VA)?
295 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
296 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
297 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
299 static unsigned long timer_reload;
301 static u32 notrace integrator_read_sched_clock(void)
303 return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
306 static void integrator_clocksource_init(unsigned long inrate,
309 u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
310 unsigned long rate = inrate;
312 if (rate >= 1500000) {
314 ctrl |= TIMER_CTRL_DIV16;
317 writel(0xffff, base + TIMER_LOAD);
318 writel(ctrl, base + TIMER_CTRL);
320 clocksource_mmio_init(base + TIMER_VALUE, "timer2",
321 rate, 200, 16, clocksource_mmio_readl_down);
322 setup_sched_clock(integrator_read_sched_clock, 16, rate);
325 static void __iomem * clkevt_base;
328 * IRQ handler for the timer
330 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
332 struct clock_event_device *evt = dev_id;
334 /* clear the interrupt */
335 writel(1, clkevt_base + TIMER_INTCLR);
337 evt->event_handler(evt);
342 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
344 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
347 writel(ctrl, clkevt_base + TIMER_CTRL);
350 case CLOCK_EVT_MODE_PERIODIC:
351 /* Enable the timer and start the periodic tick */
352 writel(timer_reload, clkevt_base + TIMER_LOAD);
353 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
354 writel(ctrl, clkevt_base + TIMER_CTRL);
356 case CLOCK_EVT_MODE_ONESHOT:
357 /* Leave the timer disabled, .set_next_event will enable it */
358 ctrl &= ~TIMER_CTRL_PERIODIC;
359 writel(ctrl, clkevt_base + TIMER_CTRL);
361 case CLOCK_EVT_MODE_UNUSED:
362 case CLOCK_EVT_MODE_SHUTDOWN:
363 case CLOCK_EVT_MODE_RESUME:
365 /* Just leave in disabled state */
371 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
373 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
375 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
376 writel(next, clkevt_base + TIMER_LOAD);
377 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
382 static struct clock_event_device integrator_clockevent = {
384 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
385 .set_mode = clkevt_set_mode,
386 .set_next_event = clkevt_set_next_event,
390 static struct irqaction integrator_timer_irq = {
392 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
393 .handler = integrator_timer_interrupt,
394 .dev_id = &integrator_clockevent,
397 static void integrator_clockevent_init(unsigned long inrate,
398 void __iomem *base, int irq)
400 unsigned long rate = inrate;
401 unsigned int ctrl = 0;
404 /* Calculate and program a divisor */
405 if (rate > 0x100000 * HZ) {
407 ctrl |= TIMER_CTRL_DIV256;
408 } else if (rate > 0x10000 * HZ) {
410 ctrl |= TIMER_CTRL_DIV16;
412 timer_reload = rate / HZ;
413 writel(ctrl, clkevt_base + TIMER_CTRL);
415 setup_irq(irq, &integrator_timer_irq);
416 clockevents_config_and_register(&integrator_clockevent,
422 void __init ap_init_early(void)
428 static void __init ap_of_timer_init(void)
430 struct device_node *node;
438 clk = clk_get_sys("ap_timer", NULL);
440 clk_prepare_enable(clk);
441 rate = clk_get_rate(clk);
443 err = of_property_read_string(of_aliases,
444 "arm,timer-primary", &path);
447 node = of_find_node_by_path(path);
448 base = of_iomap(node, 0);
451 writel(0, base + TIMER_CTRL);
452 integrator_clocksource_init(rate, base);
454 err = of_property_read_string(of_aliases,
455 "arm,timer-secondary", &path);
458 node = of_find_node_by_path(path);
459 base = of_iomap(node, 0);
462 irq = irq_of_parse_and_map(node, 0);
463 writel(0, base + TIMER_CTRL);
464 integrator_clockevent_init(rate, base, irq);
467 static const struct of_device_id fpga_irq_of_match[] __initconst = {
468 { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
472 static void __init ap_init_irq_of(void)
474 /* disable core module IRQs */
475 writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
476 of_irq_init(fpga_irq_of_match);
477 integrator_clk_init(false);
480 /* For the Device Tree, add in the UART callbacks as AUXDATA */
481 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
482 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
484 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
485 "uart0", &ap_uart_data),
486 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
487 "uart1", &ap_uart_data),
488 OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
490 OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
492 OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
493 "physmap-flash", &ap_flash_data),
497 static void __init ap_init_of(void)
499 unsigned long sc_dec;
500 struct device_node *root;
501 struct device_node *syscon;
502 struct device *parent;
503 struct soc_device *soc_dev;
504 struct soc_device_attribute *soc_dev_attr;
509 /* Here we create an SoC device for the root node */
510 root = of_find_node_by_path("/");
513 syscon = of_find_node_by_path("/syscon");
517 ap_syscon_base = of_iomap(syscon, 0);
521 ap_sc_id = readl(ap_syscon_base);
523 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
527 err = of_property_read_string(root, "compatible",
528 &soc_dev_attr->soc_id);
531 err = of_property_read_string(root, "model", &soc_dev_attr->machine);
534 soc_dev_attr->family = "Integrator";
535 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
536 'A' + (ap_sc_id & 0x0f));
538 soc_dev = soc_device_register(soc_dev_attr);
539 if (IS_ERR_OR_NULL(soc_dev)) {
540 kfree(soc_dev_attr->revision);
545 parent = soc_device_to_device(soc_dev);
547 if (!IS_ERR_OR_NULL(parent))
548 integrator_init_sysfs(parent, ap_sc_id);
550 of_platform_populate(root, of_default_bus_match_table,
551 ap_auxdata_lookup, parent);
553 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
554 for (i = 0; i < 4; i++) {
555 struct lm_device *lmdev;
557 if ((sc_dec & (16 << i)) == 0)
560 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
564 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
565 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
566 lmdev->resource.flags = IORESOURCE_MEM;
567 lmdev->irq = IRQ_AP_EXPINT0 + i;
570 lm_device_register(lmdev);
574 static const char * ap_dt_board_compat[] = {
579 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
580 .reserve = integrator_reserve,
582 .init_early = ap_init_early,
583 .init_irq = ap_init_irq_of,
584 .handle_irq = fpga_handle_irq,
585 .init_time = ap_of_timer_init,
586 .init_machine = ap_init_of,
587 .restart = integrator_restart,
588 .dt_compat = ap_dt_board_compat,
596 * For the ATAG boot some static mappings are needed. This will
597 * go away with the ATAG support down the road.
600 static struct map_desc ap_io_desc_atag[] __initdata = {
602 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
603 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
609 static void __init ap_map_io_atag(void)
611 iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
616 * This is where non-devicetree initialization code is collected and stashed
617 * for eventual deletion.
620 static struct resource cfi_flash_resource = {
621 .start = INTEGRATOR_FLASH_BASE,
622 .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
623 .flags = IORESOURCE_MEM,
626 static struct platform_device cfi_flash_device = {
627 .name = "physmap-flash",
630 .platform_data = &ap_flash_data,
633 .resource = &cfi_flash_resource,
636 static void __init ap_timer_init(void)
641 clk = clk_get_sys("ap_timer", NULL);
643 clk_prepare_enable(clk);
644 rate = clk_get_rate(clk);
646 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
647 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
648 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
650 integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
651 integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
655 #define INTEGRATOR_SC_VALID_INT 0x003fffff
657 static void __init ap_init_irq(void)
659 /* Disable all interrupts initially. */
660 /* Do the core module ones */
661 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
663 /* do the header card stuff next */
664 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
665 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
667 fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
668 -1, INTEGRATOR_SC_VALID_INT, NULL);
669 integrator_clk_init(false);
672 static void __init ap_init(void)
674 unsigned long sc_dec;
677 platform_device_register(&cfi_flash_device);
679 ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
680 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
681 for (i = 0; i < 4; i++) {
682 struct lm_device *lmdev;
684 if ((sc_dec & (16 << i)) == 0)
687 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
691 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
692 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
693 lmdev->resource.flags = IORESOURCE_MEM;
694 lmdev->irq = IRQ_AP_EXPINT0 + i;
697 lm_device_register(lmdev);
700 integrator_init(false);
703 MACHINE_START(INTEGRATOR, "ARM-Integrator")
704 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
705 .atag_offset = 0x100,
706 .reserve = integrator_reserve,
707 .map_io = ap_map_io_atag,
708 .init_early = ap_init_early,
709 .init_irq = ap_init_irq,
710 .handle_irq = fpga_handle_irq,
711 .init_time = ap_timer_init,
712 .init_machine = ap_init,
713 .restart = integrator_restart,