3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/clocksource.h>
18 #include <linux/clockchips.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <asm/mach/time.h>
28 #include <asm/localtimer.h>
29 #include <asm/sched_clock.h>
33 #define TIMER_MATCH_VAL 0x0000
34 #define TIMER_COUNT_VAL 0x0004
35 #define TIMER_ENABLE 0x0008
36 #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
37 #define TIMER_ENABLE_EN BIT(0)
38 #define TIMER_CLEAR 0x000C
39 #define DGT_CLK_CTL 0x10
40 #define DGT_CLK_CTL_DIV_4 0x3
41 #define TIMER_STS_GPT0_CLR_PEND BIT(10)
45 #define MSM_DGT_SHIFT 5
47 static void __iomem *event_base;
48 static void __iomem *sts_base;
50 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
52 struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
53 /* Stop the timer tick */
54 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
55 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
56 ctrl &= ~TIMER_ENABLE_EN;
57 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
59 evt->event_handler(evt);
63 static int msm_timer_set_next_event(unsigned long cycles,
64 struct clock_event_device *evt)
66 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
68 ctrl &= ~TIMER_ENABLE_EN;
69 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
71 writel_relaxed(ctrl, event_base + TIMER_CLEAR);
72 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
75 while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
78 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
82 static void msm_timer_set_mode(enum clock_event_mode mode,
83 struct clock_event_device *evt)
87 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
88 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
91 case CLOCK_EVT_MODE_RESUME:
92 case CLOCK_EVT_MODE_PERIODIC:
94 case CLOCK_EVT_MODE_ONESHOT:
95 /* Timer is enabled in set_next_event */
97 case CLOCK_EVT_MODE_UNUSED:
98 case CLOCK_EVT_MODE_SHUTDOWN:
101 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
104 static struct clock_event_device msm_clockevent = {
106 .features = CLOCK_EVT_FEAT_ONESHOT,
108 .set_next_event = msm_timer_set_next_event,
109 .set_mode = msm_timer_set_mode,
113 struct clock_event_device *evt;
114 struct clock_event_device * __percpu *percpu_evt;
117 static void __iomem *source_base;
119 static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
121 return readl_relaxed(source_base + TIMER_COUNT_VAL);
124 static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
127 * Shift timer count down by a constant due to unreliable lower bits
130 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
133 static struct clocksource msm_clocksource = {
136 .read = msm_read_timer_count,
137 .mask = CLOCKSOURCE_MASK(32),
138 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
141 #ifdef CONFIG_LOCAL_TIMERS
142 static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
144 /* Use existing clock_event for cpu 0 */
145 if (!smp_processor_id())
148 evt->irq = msm_clockevent.irq;
149 evt->name = "local_timer";
150 evt->features = msm_clockevent.features;
151 evt->rating = msm_clockevent.rating;
152 evt->set_mode = msm_timer_set_mode;
153 evt->set_next_event = msm_timer_set_next_event;
155 *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
156 clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
157 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
161 static void msm_local_timer_stop(struct clock_event_device *evt)
163 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
164 disable_percpu_irq(evt->irq);
167 static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
168 .setup = msm_local_timer_setup,
169 .stop = msm_local_timer_stop,
171 #endif /* CONFIG_LOCAL_TIMERS */
173 static notrace u32 msm_sched_clock_read(void)
175 return msm_clocksource.read(&msm_clocksource);
178 static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
181 struct clock_event_device *ce = &msm_clockevent;
182 struct clocksource *cs = &msm_clocksource;
185 ce->cpumask = cpumask_of(0);
188 clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
190 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
191 if (!msm_evt.percpu_evt) {
192 pr_err("memory allocation failed for %s\n", ce->name);
195 *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
196 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
197 ce->name, msm_evt.percpu_evt);
199 enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
200 #ifdef CONFIG_LOCAL_TIMERS
201 local_timer_register(&msm_local_timer_ops);
206 res = request_irq(ce->irq, msm_timer_interrupt,
207 IRQF_TIMER | IRQF_NOBALANCING |
208 IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
212 pr_err("request_irq failed for %s\n", ce->name);
214 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
215 res = clocksource_register_hz(cs, dgt_hz);
217 pr_err("clocksource_register failed\n");
218 setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
222 static const struct of_device_id msm_timer_match[] __initconst = {
223 { .compatible = "qcom,kpss-timer" },
224 { .compatible = "qcom,scss-timer" },
228 void __init msm_dt_timer_init(void)
230 struct device_node *np;
236 void __iomem *cpu0_base;
238 np = of_find_matching_node(NULL, msm_timer_match);
240 pr_err("Can't find msm timer DT node\n");
244 base = of_iomap(np, 0);
246 pr_err("Failed to map event base\n");
250 /* We use GPT0 for the clockevent */
251 irq = irq_of_parse_and_map(np, 1);
253 pr_err("Can't get irq\n");
257 /* We use CPU0's DGT for the clocksource */
258 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
261 if (of_address_to_resource(np, 0, &res)) {
262 pr_err("Failed to parse DGT resource\n");
266 cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
268 pr_err("Failed to map source base\n");
272 if (of_property_read_u32(np, "clock-frequency", &freq)) {
273 pr_err("Unknown frequency\n");
278 event_base = base + 0x4;
279 sts_base = base + 0x88;
280 source_base = cpu0_base + 0x24;
282 writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
284 msm_timer_init(freq, 32, irq, !!percpu_offset);
288 static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
293 base = ioremap(addr, SZ_256);
295 pr_err("Failed to map timer base\n");
298 event_base = base + event;
299 source_base = base + source;
301 sts_base = base + sts;
306 void __init msm7x01_timer_init(void)
308 struct clocksource *cs = &msm_clocksource;
310 if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
312 cs->read = msm_read_timer_count_shift;
313 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
315 msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
319 void __init msm7x30_timer_init(void)
321 if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
323 msm_timer_init(24576000 / 4, 32, 1, false);
326 void __init qsd8x50_timer_init(void)
328 if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
330 msm_timer_init(19200000 / 4, 32, 7, false);