3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/clocksource.h>
18 #include <linux/clockchips.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <asm/mach/time.h>
28 #include <asm/localtimer.h>
29 #include <asm/sched_clock.h>
33 #define TIMER_MATCH_VAL 0x0000
34 #define TIMER_COUNT_VAL 0x0004
35 #define TIMER_ENABLE 0x0008
36 #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
37 #define TIMER_ENABLE_EN BIT(0)
38 #define TIMER_CLEAR 0x000C
39 #define DGT_CLK_CTL_DIV_4 0x3
43 #define MSM_DGT_SHIFT 5
45 static void __iomem *event_base;
47 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
49 struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
50 /* Stop the timer tick */
51 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
52 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
53 ctrl &= ~TIMER_ENABLE_EN;
54 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
56 evt->event_handler(evt);
60 static int msm_timer_set_next_event(unsigned long cycles,
61 struct clock_event_device *evt)
63 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
65 ctrl &= ~TIMER_ENABLE_EN;
66 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
68 writel_relaxed(ctrl, event_base + TIMER_CLEAR);
69 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
70 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
74 static void msm_timer_set_mode(enum clock_event_mode mode,
75 struct clock_event_device *evt)
79 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
80 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
83 case CLOCK_EVT_MODE_RESUME:
84 case CLOCK_EVT_MODE_PERIODIC:
86 case CLOCK_EVT_MODE_ONESHOT:
87 /* Timer is enabled in set_next_event */
89 case CLOCK_EVT_MODE_UNUSED:
90 case CLOCK_EVT_MODE_SHUTDOWN:
93 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
96 static struct clock_event_device msm_clockevent = {
98 .features = CLOCK_EVT_FEAT_ONESHOT,
100 .set_next_event = msm_timer_set_next_event,
101 .set_mode = msm_timer_set_mode,
105 struct clock_event_device *evt;
106 struct clock_event_device * __percpu *percpu_evt;
109 static void __iomem *source_base;
111 static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
113 return readl_relaxed(source_base + TIMER_COUNT_VAL);
116 static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
119 * Shift timer count down by a constant due to unreliable lower bits
122 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
125 static struct clocksource msm_clocksource = {
128 .read = msm_read_timer_count,
129 .mask = CLOCKSOURCE_MASK(32),
130 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
133 #ifdef CONFIG_LOCAL_TIMERS
134 static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
136 /* Use existing clock_event for cpu 0 */
137 if (!smp_processor_id())
140 writel_relaxed(0, event_base + TIMER_ENABLE);
141 writel_relaxed(0, event_base + TIMER_CLEAR);
142 writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
143 evt->irq = msm_clockevent.irq;
144 evt->name = "local_timer";
145 evt->features = msm_clockevent.features;
146 evt->rating = msm_clockevent.rating;
147 evt->set_mode = msm_timer_set_mode;
148 evt->set_next_event = msm_timer_set_next_event;
150 *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
151 clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
152 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
156 static void msm_local_timer_stop(struct clock_event_device *evt)
158 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
159 disable_percpu_irq(evt->irq);
162 static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
163 .setup = msm_local_timer_setup,
164 .stop = msm_local_timer_stop,
166 #endif /* CONFIG_LOCAL_TIMERS */
168 static notrace u32 msm_sched_clock_read(void)
170 return msm_clocksource.read(&msm_clocksource);
173 static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
176 struct clock_event_device *ce = &msm_clockevent;
177 struct clocksource *cs = &msm_clocksource;
180 writel_relaxed(0, event_base + TIMER_ENABLE);
181 writel_relaxed(0, event_base + TIMER_CLEAR);
182 writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
183 ce->cpumask = cpumask_of(0);
186 clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
188 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
189 if (!msm_evt.percpu_evt) {
190 pr_err("memory allocation failed for %s\n", ce->name);
193 *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
194 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
195 ce->name, msm_evt.percpu_evt);
197 enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
198 #ifdef CONFIG_LOCAL_TIMERS
199 local_timer_register(&msm_local_timer_ops);
204 res = request_irq(ce->irq, msm_timer_interrupt,
205 IRQF_TIMER | IRQF_NOBALANCING |
206 IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
210 pr_err("request_irq failed for %s\n", ce->name);
212 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
213 res = clocksource_register_hz(cs, dgt_hz);
215 pr_err("clocksource_register failed\n");
216 setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
220 static const struct of_device_id msm_dgt_match[] __initconst = {
221 { .compatible = "qcom,msm-dgt" },
225 static const struct of_device_id msm_gpt_match[] __initconst = {
226 { .compatible = "qcom,msm-gpt" },
230 void __init msm_dt_timer_init(void)
232 struct device_node *np;
237 void __iomem *dgt_clk_ctl;
239 np = of_find_matching_node(NULL, msm_gpt_match);
241 pr_err("Can't find GPT DT node\n");
245 event_base = of_iomap(np, 0);
247 pr_err("Failed to map event base\n");
251 irq = irq_of_parse_and_map(np, 0);
253 pr_err("Can't get irq\n");
258 np = of_find_matching_node(NULL, msm_dgt_match);
260 pr_err("Can't find DGT DT node\n");
264 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
267 if (of_address_to_resource(np, 0, &res)) {
268 pr_err("Failed to parse DGT resource\n");
272 source_base = ioremap(res.start + percpu_offset, resource_size(&res));
274 pr_err("Failed to map source base\n");
278 if (!of_address_to_resource(np, 1, &res)) {
279 dgt_clk_ctl = ioremap(res.start + percpu_offset,
280 resource_size(&res));
282 pr_err("Failed to map DGT control base\n");
285 writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
286 iounmap(dgt_clk_ctl);
289 if (of_property_read_u32(np, "clock-frequency", &freq)) {
290 pr_err("Unknown frequency\n");
295 msm_timer_init(freq, 32, irq, !!percpu_offset);
299 static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
301 event_base = ioremap(event, SZ_64);
303 pr_err("Failed to map event base\n");
306 source_base = ioremap(source, SZ_64);
308 pr_err("Failed to map source base\n");
314 void __init msm7x01_timer_init(void)
316 struct clocksource *cs = &msm_clocksource;
318 if (msm_timer_map(0xc0100000, 0xc0100010))
320 cs->read = msm_read_timer_count_shift;
321 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
323 msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
327 void __init msm7x30_timer_init(void)
329 if (msm_timer_map(0xc0100004, 0xc0100024))
331 msm_timer_init(24576000 / 4, 32, 1, false);
334 void __init qsd8x50_timer_init(void)
336 if (msm_timer_map(0xAC100000, 0xAC100010))
338 msm_timer_init(19200000 / 4, 32, 7, false);