2 * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
5 * Copyright (C) 2012 Marvell
7 * Yehuda Yitschak <yehuday@marvell.com>
8 * Gregory Clement <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
16 * responsible for ensuring hardware coherency between all CPUs and between
17 * CPUs and I/O masters. This file initializes the coherency fabric and
18 * supplies basic routines for configuring and controlling hardware coherency
21 #define pr_fmt(fmt) "mvebu-coherency: " fmt
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/of_address.h>
27 #include <linux/smp.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
31 #include <linux/mbus.h>
32 #include <linux/pci.h>
33 #include <asm/smp_plat.h>
34 #include <asm/cacheflush.h>
35 #include <asm/mach/map.h>
36 #include <asm/dma-mapping.h>
37 #include "coherency.h"
38 #include "mvebu-soc-id.h"
40 unsigned long coherency_phys_base;
41 void __iomem *coherency_base;
42 static void __iomem *coherency_cpu_base;
44 /* Coherency fabric registers */
45 #define IO_SYNC_BARRIER_CTL_OFFSET 0x0
48 COHERENCY_FABRIC_TYPE_NONE,
49 COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
50 COHERENCY_FABRIC_TYPE_ARMADA_375,
51 COHERENCY_FABRIC_TYPE_ARMADA_380,
54 static const struct of_device_id of_coherency_table[] = {
55 {.compatible = "marvell,coherency-fabric",
56 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
57 {.compatible = "marvell,armada-375-coherency-fabric",
58 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
59 {.compatible = "marvell,armada-380-coherency-fabric",
60 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
61 { /* end of list */ },
64 /* Functions defined in coherency_ll.S */
65 int ll_enable_coherency(void);
66 void ll_add_cpu_to_smp_group(void);
68 static int mvebu_hwcc_notifier(struct notifier_block *nb,
69 unsigned long event, void *__dev)
71 struct device *dev = __dev;
73 if (event != BUS_NOTIFY_ADD_DEVICE)
75 set_dma_ops(dev, &arm_coherent_dma_ops);
80 static struct notifier_block mvebu_hwcc_nb = {
81 .notifier_call = mvebu_hwcc_notifier,
84 static struct notifier_block mvebu_hwcc_pci_nb = {
85 .notifier_call = mvebu_hwcc_notifier,
88 static void __init armada_370_coherency_init(struct device_node *np)
92 of_address_to_resource(np, 0, &res);
93 coherency_phys_base = res.start;
95 * Ensure secondary CPUs will see the updated value,
96 * which they read before they join the coherency
97 * fabric, and therefore before they are coherent with
100 sync_cache_w(&coherency_phys_base);
101 coherency_base = of_iomap(np, 0);
102 coherency_cpu_base = of_iomap(np, 1);
107 * This ioremap hook is used on Armada 375/38x to ensure that PCIe
108 * memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
109 * is needed as a workaround for a deadlock issue between the PCIe
110 * interface and the cache controller.
112 static void __iomem *
113 armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
114 unsigned int mtype, void *caller)
116 struct resource pcie_mem;
118 mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
120 if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
123 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
126 static void __init armada_375_380_coherency_init(struct device_node *np)
128 struct device_node *cache_dn;
130 coherency_cpu_base = of_iomap(np, 0);
131 arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
134 * We should switch the PL310 to I/O coherency mode only if
135 * I/O coherency is actually enabled.
137 if (!coherency_available())
141 * Add the PL310 property "arm,io-coherent". This makes sure the
142 * outer sync operation is not used, which allows to
143 * workaround the system erratum that causes deadlocks when
144 * doing PCIe in an SMP situation on Armada 375 and Armada
147 for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
150 p = kzalloc(sizeof(*p), GFP_KERNEL);
151 p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
152 of_add_property(cache_dn, p);
156 static int coherency_type(void)
158 struct device_node *np;
159 const struct of_device_id *match;
163 * The coherency fabric is needed:
164 * - For coherency between processors on Armada XP, so only
165 * when SMP is enabled.
166 * - For coherency between the processor and I/O devices, but
167 * this coherency requires many pre-requisites (write
168 * allocate cache policy, shareable pages, SMP bit set) that
169 * are only meant in SMP situations.
171 * Note that this means that on Armada 370, there is currently
172 * no way to use hardware I/O coherency, because even when
173 * CONFIG_SMP is enabled, is_smp() returns false due to the
174 * Armada 370 being a single-core processor. To lift this
175 * limitation, we would have to find a way to make the cache
176 * policy set to write-allocate (on all Armada SoCs), and to
177 * set the shareable attribute in page tables (on all Armada
178 * SoCs except the Armada 370). Unfortunately, such decisions
179 * are taken very early in the kernel boot process, at a point
180 * where we don't know yet on which SoC we are running.
184 return COHERENCY_FABRIC_TYPE_NONE;
186 np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
188 return COHERENCY_FABRIC_TYPE_NONE;
190 type = (int) match->data;
197 int set_cpu_coherent(void)
199 int type = coherency_type();
201 if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) {
202 if (!coherency_base) {
203 pr_warn("Can't make current CPU cache coherent.\n");
204 pr_warn("Coherency fabric is not initialized\n");
207 ll_add_cpu_to_smp_group();
208 return ll_enable_coherency();
214 int coherency_available(void)
216 return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
219 int __init coherency_init(void)
221 int type = coherency_type();
222 struct device_node *np;
224 np = of_find_matching_node(NULL, of_coherency_table);
226 if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
227 armada_370_coherency_init(np);
228 else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 ||
229 type == COHERENCY_FABRIC_TYPE_ARMADA_380)
230 armada_375_380_coherency_init(np);
237 static int __init coherency_late_init(void)
239 if (coherency_available())
240 bus_register_notifier(&platform_bus_type,
245 postcore_initcall(coherency_late_init);
247 #if IS_ENABLED(CONFIG_PCI)
248 static int __init coherency_pci_init(void)
250 if (coherency_available())
251 bus_register_notifier(&pci_bus_type,
256 arch_initcall(coherency_pci_init);