arch/arm/mach-mvebu/irq-armada-370-xp.c

   1 /*
   2  * Marvell Armada 370 and Armada XP SoC IRQ handling
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  * Ben Dooks <ben.dooks@codethink.co.uk>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/irq.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/irqdomain.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/exception.h>
  27 #include <asm/smp_plat.h>
  28
  29 /* Interrupt Controller Registers Map */
  30 #define ARMADA_370_XP_INT_SET_MASK_OFFS         (0x48)
  31 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS       (0x4C)
  32
  33 #define ARMADA_370_XP_INT_CONTROL               (0x00)
  34 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS       (0x30)
  35 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS     (0x34)
  36
  37 #define ARMADA_370_XP_CPU_INTACK_OFFS           (0x44)
  38
  39 #define ARMADA_370_XP_SW_TRIG_INT_OFFS           (0x4)
  40 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
  41 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)
  42
  43 #define ACTIVE_DOORBELLS                        (8)
  44
  45 static void __iomem *per_cpu_int_base;
  46 static void __iomem *main_int_base;
  47 static struct irq_domain *armada_370_xp_mpic_domain;
  48
  49 static void armada_370_xp_irq_mask(struct irq_data *d)
  50 {
  51         writel(irqd_to_hwirq(d),
  52                per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
  53 }
  54
  55 static void armada_370_xp_irq_unmask(struct irq_data *d)
  56 {
  57         writel(irqd_to_hwirq(d),
  58                per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
  59 }
  60
  61 #ifdef CONFIG_SMP
  62 static int armada_xp_set_affinity(struct irq_data *d,
  63                                   const struct cpumask *mask_val, bool force)
  64 {
  65         return 0;
  66 }
  67 #endif
  68
  69 static struct irq_chip armada_370_xp_irq_chip = {
  70         .name           = "armada_370_xp_irq",
  71         .irq_mask       = armada_370_xp_irq_mask,
  72         .irq_mask_ack   = armada_370_xp_irq_mask,
  73         .irq_unmask     = armada_370_xp_irq_unmask,
  74 #ifdef CONFIG_SMP
  75         .irq_set_affinity = armada_xp_set_affinity,
  76 #endif
  77 };
  78
  79 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
  80                                       unsigned int virq, irq_hw_number_t hw)
  81 {
  82         armada_370_xp_irq_mask(irq_get_irq_data(virq));
  83         writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
  84
  85         irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
  86                                  handle_level_irq);
  87         irq_set_status_flags(virq, IRQ_LEVEL);
  88         set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
  89
  90         return 0;
  91 }
  92
  93 #ifdef CONFIG_SMP
  94 void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
  95 {
  96         int cpu;
  97         unsigned long map = 0;
  98
  99         /* Convert our logical CPU mask into a physical one. */
 100         for_each_cpu(cpu, mask)
 101                 map |= 1 << cpu_logical_map(cpu);
 102
 103         /*
 104          * Ensure that stores to Normal memory are visible to the
 105          * other CPUs before issuing the IPI.
 106          */
 107         dsb();
 108
 109         /* submit softirq */
 110         writel((map << 8) | irq, main_int_base +
 111                 ARMADA_370_XP_SW_TRIG_INT_OFFS);
 112 }
 113
 114 void armada_xp_mpic_smp_cpu_init(void)
 115 {
 116         /* Clear pending IPIs */
 117         writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 118
 119         /* Enable first 8 IPIs */
 120         writel((1 << ACTIVE_DOORBELLS) - 1, per_cpu_int_base +
 121                 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 122
 123         /* Unmask IPI interrupt */
 124         writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 125 }
 126 #endif /* CONFIG_SMP */
 127
 128 static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
 129         .map = armada_370_xp_mpic_irq_map,
 130         .xlate = irq_domain_xlate_onecell,
 131 };
 132
 133 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 134                                              struct device_node *parent)
 135 {
 136         u32 control;
 137
 138         main_int_base = of_iomap(node, 0);
 139         per_cpu_int_base = of_iomap(node, 1);
 140
 141         BUG_ON(!main_int_base);
 142         BUG_ON(!per_cpu_int_base);
 143
 144         control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
 145
 146         armada_370_xp_mpic_domain =
 147                 irq_domain_add_linear(node, (control >> 2) & 0x3ff,
 148                                 &armada_370_xp_mpic_irq_ops, NULL);
 149
 150         if (!armada_370_xp_mpic_domain)
 151                 panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
 152
 153         irq_set_default_host(armada_370_xp_mpic_domain);
 154
 155 #ifdef CONFIG_SMP
 156         armada_xp_mpic_smp_cpu_init();
 157 #endif
 158
 159         return 0;
 160 }
 161
 162 asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
 163                                                                *regs)
 164 {
 165         u32 irqstat, irqnr;
 166
 167         do {
 168                 irqstat = readl_relaxed(per_cpu_int_base +
 169                                         ARMADA_370_XP_CPU_INTACK_OFFS);
 170                 irqnr = irqstat & 0x3FF;
 171
 172                 if (irqnr > 1022)
 173                         break;
 174
 175                 if (irqnr >= 8) {
 176                         irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
 177                                         irqnr);
 178                         handle_IRQ(irqnr, regs);
 179                         continue;
 180                 }
 181 #ifdef CONFIG_SMP
 182                 /* IPI Handling */
 183                 if (irqnr == 0) {
 184                         u32 ipimask, ipinr;
 185
 186                         ipimask = readl_relaxed(per_cpu_int_base +
 187                                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
 188                                 & 0xFF;
 189
 190                         writel(0x0, per_cpu_int_base +
 191                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 192
 193                         /* Handle all pending doorbells */
 194                         for (ipinr = 0; ipinr < ACTIVE_DOORBELLS; ipinr++) {
 195                                 if (ipimask & (0x1 << ipinr))
 196                                         handle_IPI(ipinr, regs);
 197                         }
 198                         continue;
 199                 }
 200 #endif
 201
 202         } while (1);
 203 }
 204
 205 static const struct of_device_id mpic_of_match[] __initconst = {
 206         {.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
 207         {},
 208 };
 209
 210 void __init armada_370_xp_init_irq(void)
 211 {
 212         of_irq_init(mpic_of_match);
 213 }