2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
11 * This file contains the CPU initialization code.
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <mach/hardware.h>
21 static int cpu_silicon_rev = -1;
25 static void query_silicon_parameter(void)
27 void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
31 cpu_silicon_rev = -EINVAL;
35 rev = readl(rom + SI_REV);
38 cpu_silicon_rev = MX51_CHIP_REV_1_0;
41 cpu_silicon_rev = MX51_CHIP_REV_1_1;
44 cpu_silicon_rev = MX51_CHIP_REV_2_0;
47 cpu_silicon_rev = MX51_CHIP_REV_3_0;
58 * the silicon revision of the cpu
59 * -EINVAL - not a mx51
61 int mx51_revision(void)
66 if (cpu_silicon_rev == -1)
67 query_silicon_parameter();
69 return cpu_silicon_rev;
71 EXPORT_SYMBOL(mx51_revision);
76 * All versions of the silicon before Rev. 3 have broken NEON implementations.
77 * Dependent on link order - so the assumption is that vfp_init is called
80 static int __init mx51_neon_fixup(void)
85 if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) {
86 elf_hwcap &= ~HWCAP_NEON;
87 pr_info("Turning off NEON support, detected broken NEON implementation\n");
92 late_initcall(mx51_neon_fixup);
95 static int __init post_cpu_init(void)
100 if (cpu_is_mx51() || cpu_is_mx53()) {
102 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
104 base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
106 __raw_writel(0x0, base + 0x40);
107 __raw_writel(0x0, base + 0x44);
108 __raw_writel(0x0, base + 0x48);
109 __raw_writel(0x0, base + 0x4C);
110 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
111 __raw_writel(reg, base + 0x50);
114 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
116 base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
118 __raw_writel(0x0, base + 0x40);
119 __raw_writel(0x0, base + 0x44);
120 __raw_writel(0x0, base + 0x48);
121 __raw_writel(0x0, base + 0x4C);
122 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
123 __raw_writel(reg, base + 0x50);
129 postcore_initcall(post_cpu_init);