2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/delay.h>
21 #include <linux/clk.h>
23 #include <linux/jiffies.h>
24 #include <linux/clkdev.h>
26 #include <asm/clkdev.h>
27 #include <asm/div64.h>
29 #include <mach/mx28.h>
30 #include <mach/common.h>
31 #include <mach/clock.h>
33 #include "regs-clkctrl-mx28.h"
35 #define CLKCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
36 #define DIGCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
38 #define PARENT_RATE_SHIFT 8
40 static struct clk pll2_clk;
41 static struct clk cpu_clk;
42 static struct clk emi_clk;
43 static struct clk saif0_clk;
44 static struct clk saif1_clk;
45 static struct clk clk32k_clk;
47 static int _raw_clk_enable(struct clk *clk)
51 if (clk->enable_reg) {
52 reg = __raw_readl(clk->enable_reg);
53 reg &= ~(1 << clk->enable_shift);
54 __raw_writel(reg, clk->enable_reg);
60 static void _raw_clk_disable(struct clk *clk)
64 if (clk->enable_reg) {
65 reg = __raw_readl(clk->enable_reg);
66 reg |= 1 << clk->enable_shift;
67 __raw_writel(reg, clk->enable_reg);
74 static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
79 static struct clk ref_xtal_clk = {
80 .get_rate = ref_xtal_clk_get_rate,
86 static unsigned long pll0_clk_get_rate(struct clk *clk)
91 static unsigned long pll1_clk_get_rate(struct clk *clk)
96 static unsigned long pll2_clk_get_rate(struct clk *clk)
101 #define _CLK_ENABLE_PLL(name, r, g) \
102 static int name##_enable(struct clk *clk) \
104 __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
105 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
108 if (clk == &pll2_clk) \
109 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
110 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
112 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
113 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
118 _CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
119 _CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
120 _CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
122 #define _CLK_DISABLE_PLL(name, r, g) \
123 static void name##_disable(struct clk *clk) \
125 __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
126 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
128 if (clk == &pll2_clk) \
129 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
130 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
132 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
133 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
137 _CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
138 _CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
139 _CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
141 #define _DEFINE_CLOCK_PLL(name) \
142 static struct clk name = { \
143 .get_rate = name##_get_rate, \
144 .enable = name##_enable, \
145 .disable = name##_disable, \
146 .parent = &ref_xtal_clk, \
149 _DEFINE_CLOCK_PLL(pll0_clk);
150 _DEFINE_CLOCK_PLL(pll1_clk);
151 _DEFINE_CLOCK_PLL(pll2_clk);
156 #define _CLK_GET_RATE_REF(name, sr, ss) \
157 static unsigned long name##_get_rate(struct clk *clk) \
159 unsigned long parent_rate; \
162 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
163 div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
164 parent_rate = clk_get_rate(clk->parent); \
166 return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
167 div, PARENT_RATE_SHIFT); \
170 _CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
171 _CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
172 _CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
173 _CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
174 _CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
175 _CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
177 #define _DEFINE_CLOCK_REF(name, er, es) \
178 static struct clk name = { \
179 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
180 .enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
181 .get_rate = name##_get_rate, \
182 .enable = _raw_clk_enable, \
183 .disable = _raw_clk_disable, \
184 .parent = &pll0_clk, \
187 _DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
188 _DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
189 _DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
190 _DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
191 _DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
192 _DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
199 static unsigned long lradc_clk_get_rate(struct clk *clk)
201 return clk_get_rate(clk->parent) / 16;
204 static unsigned long rtc_clk_get_rate(struct clk *clk)
206 /* ref_xtal_clk is implemented as the only parent */
207 return clk_get_rate(clk->parent) / 768;
210 static unsigned long clk32k_clk_get_rate(struct clk *clk)
212 return clk->parent->get_rate(clk->parent) / 750;
215 static unsigned long spdif_clk_get_rate(struct clk *clk)
217 return clk_get_rate(clk->parent) / 4;
220 #define _CLK_GET_RATE(name, rs) \
221 static unsigned long name##_get_rate(struct clk *clk) \
225 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
227 if (clk->parent == &ref_xtal_clk) \
228 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
229 BP_CLKCTRL_##rs##_DIV_XTAL; \
231 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
232 BP_CLKCTRL_##rs##_DIV_##rs; \
237 return clk_get_rate(clk->parent) / div; \
240 _CLK_GET_RATE(cpu_clk, CPU)
241 _CLK_GET_RATE(emi_clk, EMI)
243 #define _CLK_GET_RATE1(name, rs) \
244 static unsigned long name##_get_rate(struct clk *clk) \
248 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
249 div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
254 if (clk == &saif0_clk || clk == &saif1_clk) \
255 return clk_get_rate(clk->parent) >> 16 * div; \
257 return clk_get_rate(clk->parent) / div; \
260 _CLK_GET_RATE1(hbus_clk, HBUS)
261 _CLK_GET_RATE1(xbus_clk, XBUS)
262 _CLK_GET_RATE1(ssp0_clk, SSP0)
263 _CLK_GET_RATE1(ssp1_clk, SSP1)
264 _CLK_GET_RATE1(ssp2_clk, SSP2)
265 _CLK_GET_RATE1(ssp3_clk, SSP3)
266 _CLK_GET_RATE1(gpmi_clk, GPMI)
267 _CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
268 _CLK_GET_RATE1(saif0_clk, SAIF0)
269 _CLK_GET_RATE1(saif1_clk, SAIF1)
271 #define _CLK_GET_RATE_STUB(name) \
272 static unsigned long name##_get_rate(struct clk *clk) \
274 return clk_get_rate(clk->parent); \
277 _CLK_GET_RATE_STUB(uart_clk)
278 _CLK_GET_RATE_STUB(pwm_clk)
279 _CLK_GET_RATE_STUB(can0_clk)
280 _CLK_GET_RATE_STUB(can1_clk)
281 _CLK_GET_RATE_STUB(fec_clk)
287 #define BM_CLKCTRL_CPU_DIV 0
288 #define BP_CLKCTRL_CPU_DIV 0
289 #define BM_CLKCTRL_CPU_BUSY 0
291 #define _CLK_SET_RATE(name, dr, fr, fs) \
292 static int name##_set_rate(struct clk *clk, unsigned long rate) \
294 u32 reg, bm_busy, div_max, d, f, div, frac; \
295 unsigned long diff, parent_rate, calc_rate; \
298 parent_rate = clk_get_rate(clk->parent); \
299 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
300 bm_busy = BM_CLKCTRL_##dr##_BUSY; \
302 if (clk->parent == &ref_xtal_clk) { \
303 div = DIV_ROUND_UP(parent_rate, rate); \
304 if (clk == &cpu_clk) { \
305 div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \
306 BP_CLKCTRL_CPU_DIV_XTAL; \
307 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL; \
309 if (div == 0 || div > div_max) \
312 rate >>= PARENT_RATE_SHIFT; \
313 parent_rate >>= PARENT_RATE_SHIFT; \
314 diff = parent_rate; \
316 if (clk == &cpu_clk) { \
317 div_max = BM_CLKCTRL_CPU_DIV_CPU >> \
318 BP_CLKCTRL_CPU_DIV_CPU; \
319 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU; \
321 for (d = 1; d <= div_max; d++) { \
322 f = parent_rate * 18 / d / rate; \
323 if ((parent_rate * 18 / d) % rate) \
325 if (f < 18 || f > 35) \
328 calc_rate = parent_rate * 18 / f / d; \
329 if (calc_rate > rate) \
332 if (rate - calc_rate < diff) { \
335 diff = rate - calc_rate; \
342 if (diff == parent_rate) \
345 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
346 reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \
348 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
351 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
352 if (clk == &cpu_clk) { \
353 reg &= ~BM_CLKCTRL_CPU_DIV_CPU; \
354 reg |= div << BP_CLKCTRL_CPU_DIV_CPU; \
356 reg &= ~BM_CLKCTRL_##dr##_DIV; \
357 reg |= div << BP_CLKCTRL_##dr##_DIV; \
358 if (reg & (1 << clk->enable_shift)) { \
359 pr_err("%s: clock is gated\n", __func__); \
363 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
365 for (i = 10000; i; i--) \
366 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
367 HW_CLKCTRL_##dr) & bm_busy)) \
370 pr_err("%s: divider writing timeout\n", __func__); \
377 _CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
378 _CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
379 _CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
380 _CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
381 _CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
382 _CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
383 _CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
385 #define _CLK_SET_RATE1(name, dr) \
386 static int name##_set_rate(struct clk *clk, unsigned long rate) \
388 u32 reg, div_max, div; \
389 unsigned long parent_rate; \
392 parent_rate = clk_get_rate(clk->parent); \
393 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
395 div = DIV_ROUND_UP(parent_rate, rate); \
396 if (div == 0 || div > div_max) \
399 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
400 reg &= ~BM_CLKCTRL_##dr##_DIV; \
401 reg |= div << BP_CLKCTRL_##dr##_DIV; \
402 if (reg | (1 << clk->enable_shift)) { \
403 pr_err("%s: clock is gated\n", __func__); \
406 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
408 for (i = 10000; i; i--) \
409 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
410 HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \
413 pr_err("%s: divider writing timeout\n", __func__); \
420 _CLK_SET_RATE1(xbus_clk, XBUS)
422 /* saif clock uses 16 bits frac div */
423 #define _CLK_SET_RATE_SAIF(name, rs) \
424 static int name##_set_rate(struct clk *clk, unsigned long rate) \
429 unsigned long parent_rate; \
432 parent_rate = clk_get_rate(clk->parent); \
433 if (rate > parent_rate) \
436 lrate = (u64)rate << 16; \
437 do_div(lrate, parent_rate); \
443 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
444 reg &= ~BM_CLKCTRL_##rs##_DIV; \
445 reg |= div << BP_CLKCTRL_##rs##_DIV; \
446 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
448 for (i = 10000; i; i--) \
449 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
450 HW_CLKCTRL_##rs) & BM_CLKCTRL_##rs##_BUSY)) \
453 pr_err("%s: divider writing timeout\n", __func__); \
460 _CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
461 _CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
463 #define _CLK_SET_RATE_STUB(name) \
464 static int name##_set_rate(struct clk *clk, unsigned long rate) \
469 _CLK_SET_RATE_STUB(emi_clk)
470 _CLK_SET_RATE_STUB(uart_clk)
471 _CLK_SET_RATE_STUB(pwm_clk)
472 _CLK_SET_RATE_STUB(spdif_clk)
473 _CLK_SET_RATE_STUB(clk32k_clk)
474 _CLK_SET_RATE_STUB(can0_clk)
475 _CLK_SET_RATE_STUB(can1_clk)
476 _CLK_SET_RATE_STUB(fec_clk)
481 #define _CLK_SET_PARENT(name, bit) \
482 static int name##_set_parent(struct clk *clk, struct clk *parent) \
484 if (parent != clk->parent) { \
485 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
486 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG); \
487 clk->parent = parent; \
493 _CLK_SET_PARENT(cpu_clk, CPU)
494 _CLK_SET_PARENT(emi_clk, EMI)
495 _CLK_SET_PARENT(ssp0_clk, SSP0)
496 _CLK_SET_PARENT(ssp1_clk, SSP1)
497 _CLK_SET_PARENT(ssp2_clk, SSP2)
498 _CLK_SET_PARENT(ssp3_clk, SSP3)
499 _CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
500 _CLK_SET_PARENT(gpmi_clk, GPMI)
501 _CLK_SET_PARENT(saif0_clk, SAIF0)
502 _CLK_SET_PARENT(saif1_clk, SAIF1)
504 #define _CLK_SET_PARENT_STUB(name) \
505 static int name##_set_parent(struct clk *clk, struct clk *parent) \
507 if (parent != clk->parent) \
513 _CLK_SET_PARENT_STUB(pwm_clk)
514 _CLK_SET_PARENT_STUB(uart_clk)
515 _CLK_SET_PARENT_STUB(clk32k_clk)
516 _CLK_SET_PARENT_STUB(spdif_clk)
517 _CLK_SET_PARENT_STUB(fec_clk)
518 _CLK_SET_PARENT_STUB(can0_clk)
519 _CLK_SET_PARENT_STUB(can1_clk)
524 static struct clk cpu_clk = {
525 .get_rate = cpu_clk_get_rate,
526 .set_rate = cpu_clk_set_rate,
527 .set_parent = cpu_clk_set_parent,
528 .parent = &ref_cpu_clk,
531 static struct clk hbus_clk = {
532 .get_rate = hbus_clk_get_rate,
536 static struct clk xbus_clk = {
537 .get_rate = xbus_clk_get_rate,
538 .set_rate = xbus_clk_set_rate,
539 .parent = &ref_xtal_clk,
542 static struct clk lradc_clk = {
543 .get_rate = lradc_clk_get_rate,
544 .parent = &clk32k_clk,
547 static struct clk rtc_clk = {
548 .get_rate = rtc_clk_get_rate,
549 .parent = &ref_xtal_clk,
552 /* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
553 static struct clk usb0_clk = {
554 .enable_reg = DIGCTRL_BASE_ADDR,
556 .enable = _raw_clk_enable,
557 .disable = _raw_clk_disable,
561 static struct clk usb1_clk = {
562 .enable_reg = DIGCTRL_BASE_ADDR,
564 .enable = _raw_clk_enable,
565 .disable = _raw_clk_disable,
569 #define _DEFINE_CLOCK(name, er, es, p) \
570 static struct clk name = { \
571 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
572 .enable_shift = BP_CLKCTRL_##er##_##es, \
573 .get_rate = name##_get_rate, \
574 .set_rate = name##_set_rate, \
575 .set_parent = name##_set_parent, \
576 .enable = _raw_clk_enable, \
577 .disable = _raw_clk_disable, \
581 _DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
582 _DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
583 _DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
584 _DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
585 _DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
586 _DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
587 _DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
588 _DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
589 _DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
590 _DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
591 _DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
592 _DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
593 _DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
594 _DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
595 _DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
596 _DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
598 #define _REGISTER_CLOCK(d, n, c) \
605 static struct clk_lookup lookups[] = {
606 /* for amba bus driver */
607 _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
608 /* for amba-pl011 driver */
609 _REGISTER_CLOCK("duart", NULL, uart_clk)
610 _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
611 _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
612 _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
613 _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
614 _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
615 _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
616 _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
617 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
618 _REGISTER_CLOCK("pll2", NULL, pll2_clk)
619 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
620 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
621 _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
622 _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk)
623 _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
624 _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
625 _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
626 _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
627 _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
628 _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
629 _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
630 _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
631 _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
632 _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
633 _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
634 _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
635 _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
636 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
637 _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
640 static int clk_misc_init(void)
645 /* Fix up parent per register setting */
646 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
647 cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
648 &ref_xtal_clk : &ref_cpu_clk;
649 emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
650 &ref_xtal_clk : &ref_emi_clk;
651 ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
652 &ref_xtal_clk : &ref_io0_clk;
653 ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
654 &ref_xtal_clk : &ref_io0_clk;
655 ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
656 &ref_xtal_clk : &ref_io1_clk;
657 ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
658 &ref_xtal_clk : &ref_io1_clk;
659 lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
660 &ref_xtal_clk : &ref_pix_clk;
661 gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
662 &ref_xtal_clk : &ref_gpmi_clk;
663 saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
664 &ref_xtal_clk : &pll0_clk;
665 saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
666 &ref_xtal_clk : &pll0_clk;
668 /* Use int div over frac when both are available */
669 __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
670 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
671 __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
672 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
673 __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
674 CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
676 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
677 reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
678 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
680 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
681 reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
682 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
684 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
685 reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
686 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
688 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
689 reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
690 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
692 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
693 reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
694 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
696 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
697 reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
698 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
700 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
701 reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
702 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
704 /* SAIF has to use frac div for functional operation */
705 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
706 reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
707 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
709 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
710 reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
711 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
714 * Set safe hbus clock divider. A divider of 3 ensure that
715 * the Vddd voltage required for the cpu clock is sufficiently
716 * high for the hbus clock.
718 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
719 reg &= BM_CLKCTRL_HBUS_DIV;
720 reg |= 3 << BP_CLKCTRL_HBUS_DIV;
721 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
723 for (i = 10000; i; i--)
724 if (!(__raw_readl(CLKCTRL_BASE_ADDR +
725 HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_ASM_BUSY))
728 pr_err("%s: divider writing timeout\n", __func__);
732 /* Gate off cpu clock in WFI for power saving */
733 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
734 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
736 /* Extra fec clock setting */
737 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
738 reg &= ~BM_CLKCTRL_ENET_SLEEP;
739 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
740 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
743 * 480 MHz seems too high to be ssp clock source directly,
744 * so set frac0 to get a 288 MHz ref_io0.
746 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
747 reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC;
748 reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC;
749 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
754 int __init mx28_clocks_init(void)
759 * source ssp clock from ref_io0 than ref_xtal,
760 * as ref_xtal only provides 24 MHz as maximum.
762 clk_set_parent(&ssp0_clk, &ref_io0_clk);
763 clk_set_parent(&ssp1_clk, &ref_io0_clk);
765 clk_enable(&cpu_clk);
766 clk_enable(&hbus_clk);
767 clk_enable(&xbus_clk);
768 clk_enable(&emi_clk);
769 clk_enable(&uart_clk);
771 clk_set_parent(&lcdif_clk, &ref_pix_clk);
773 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
775 mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);