2 * Copyright (C) 2000-2001 Deep Blue Solutions
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 #include <linux/err.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/clockchips.h>
27 #include <linux/clk.h>
29 #include <linux/of_irq.h>
31 #include <asm/mach/time.h>
32 #include <asm/sched_clock.h>
34 #include <mach/common.h>
37 * There are 2 versions of the timrot on Freescale MXS-based SoCs.
38 * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
39 * extends the counter to 32 bits.
41 * The implementation uses two timers, one for clock_event and
42 * another for clocksource. MX28 uses timrot 0 and 1, while MX23
46 #define MX23_TIMROT_VERSION_OFFSET 0x0a0
47 #define MX28_TIMROT_VERSION_OFFSET 0x120
48 #define BP_TIMROT_MAJOR_VERSION 24
49 #define BV_TIMROT_VERSION_1 0x01
50 #define BV_TIMROT_VERSION_2 0x02
51 #define timrot_is_v1() (timrot_major_version == BV_TIMROT_VERSION_1)
54 * There are 4 registers for each timrotv2 instance, and 2 registers
55 * for each timrotv1. So address step 0x40 in macros below strides
56 * one instance of timrotv2 while two instances of timrotv1.
58 * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
59 * on MX28 while timrot2 on MX23.
61 /* common between v1 and v2 */
62 #define HW_TIMROT_ROTCTRL 0x00
63 #define HW_TIMROT_TIMCTRLn(n) (0x20 + (n) * 0x40)
65 #define HW_TIMROT_TIMCOUNTn(n) (0x30 + (n) * 0x40)
67 #define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40)
68 #define HW_TIMROT_FIXED_COUNTn(n) (0x40 + (n) * 0x40)
70 #define BM_TIMROT_TIMCTRLn_RELOAD (1 << 6)
71 #define BM_TIMROT_TIMCTRLn_UPDATE (1 << 7)
72 #define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
73 #define BM_TIMROT_TIMCTRLn_IRQ (1 << 15)
74 #define BP_TIMROT_TIMCTRLn_SELECT 0
75 #define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
76 #define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
78 static struct clock_event_device mxs_clockevent_device;
79 static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
81 static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
82 static u32 timrot_major_version;
84 static inline void timrot_irq_disable(void)
86 __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
87 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
90 static inline void timrot_irq_enable(void)
92 __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
93 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
96 static void timrot_irq_acknowledge(void)
98 __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
99 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
102 static cycle_t timrotv1_get_cycles(struct clocksource *cs)
104 return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
105 & 0xffff0000) >> 16);
108 static int timrotv1_set_next_event(unsigned long evt,
109 struct clock_event_device *dev)
111 /* timrot decrements the count */
112 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
117 static int timrotv2_set_next_event(unsigned long evt,
118 struct clock_event_device *dev)
120 /* timrot decrements the count */
121 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
126 static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
128 struct clock_event_device *evt = dev_id;
130 timrot_irq_acknowledge();
131 evt->event_handler(evt);
136 static struct irqaction mxs_timer_irq = {
137 .name = "MXS Timer Tick",
138 .dev_id = &mxs_clockevent_device,
139 .flags = IRQF_TIMER | IRQF_IRQPOLL,
140 .handler = mxs_timer_interrupt,
144 static const char *clock_event_mode_label[] const = {
145 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
146 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
147 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
148 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
152 static void mxs_set_mode(enum clock_event_mode mode,
153 struct clock_event_device *evt)
155 /* Disable interrupt in timer module */
156 timrot_irq_disable();
158 if (mode != mxs_clockevent_mode) {
159 /* Set event time into the furthest future */
162 mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
164 __raw_writel(0xffffffff,
165 mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
167 /* Clear pending interrupt */
168 timrot_irq_acknowledge();
172 pr_info("%s: changing mode from %s to %s\n", __func__,
173 clock_event_mode_label[mxs_clockevent_mode],
174 clock_event_mode_label[mode]);
177 /* Remember timer mode */
178 mxs_clockevent_mode = mode;
181 case CLOCK_EVT_MODE_PERIODIC:
182 pr_err("%s: Periodic mode is not implemented\n", __func__);
184 case CLOCK_EVT_MODE_ONESHOT:
187 case CLOCK_EVT_MODE_SHUTDOWN:
188 case CLOCK_EVT_MODE_UNUSED:
189 case CLOCK_EVT_MODE_RESUME:
190 /* Left event sources disabled, no more interrupts appear */
195 static struct clock_event_device mxs_clockevent_device = {
196 .name = "mxs_timrot",
197 .features = CLOCK_EVT_FEAT_ONESHOT,
199 .set_mode = mxs_set_mode,
200 .set_next_event = timrotv2_set_next_event,
204 static int __init mxs_clockevent_init(struct clk *timer_clk)
206 unsigned int c = clk_get_rate(timer_clk);
208 mxs_clockevent_device.mult =
209 div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift);
210 mxs_clockevent_device.cpumask = cpumask_of(0);
211 if (timrot_is_v1()) {
212 mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
213 mxs_clockevent_device.max_delta_ns =
214 clockevent_delta2ns(0xfffe, &mxs_clockevent_device);
215 mxs_clockevent_device.min_delta_ns =
216 clockevent_delta2ns(0xf, &mxs_clockevent_device);
218 mxs_clockevent_device.max_delta_ns =
219 clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device);
220 mxs_clockevent_device.min_delta_ns =
221 clockevent_delta2ns(0xf, &mxs_clockevent_device);
224 clockevents_register_device(&mxs_clockevent_device);
229 static struct clocksource clocksource_mxs = {
232 .read = timrotv1_get_cycles,
233 .mask = CLOCKSOURCE_MASK(16),
234 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
237 static u32 notrace mxs_read_sched_clock_v2(void)
239 return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
242 static int __init mxs_clocksource_init(struct clk *timer_clk)
244 unsigned int c = clk_get_rate(timer_clk);
247 clocksource_register_hz(&clocksource_mxs, c);
249 clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
250 "mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
251 setup_sched_clock(mxs_read_sched_clock_v2, 32, c);
257 void __init mxs_timer_init(void)
259 struct device_node *np;
260 struct clk *timer_clk;
263 np = of_find_compatible_node(NULL, NULL, "fsl,timrot");
265 pr_err("%s: failed find timrot node\n", __func__);
269 timer_clk = clk_get_sys("timrot", NULL);
270 if (IS_ERR(timer_clk)) {
271 pr_err("%s: failed to get clk\n", __func__);
275 clk_prepare_enable(timer_clk);
278 * Initialize timers to a known state
280 mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
282 /* get timrot version */
283 timrot_major_version = __raw_readl(mxs_timrot_base +
284 (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
285 MX28_TIMROT_VERSION_OFFSET));
286 timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
288 /* one for clock_event */
289 __raw_writel((timrot_is_v1() ?
290 BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
291 BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
292 BM_TIMROT_TIMCTRLn_UPDATE |
293 BM_TIMROT_TIMCTRLn_IRQ_EN,
294 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
296 /* another for clocksource */
297 __raw_writel((timrot_is_v1() ?
298 BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
299 BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
300 BM_TIMROT_TIMCTRLn_RELOAD,
301 mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
303 /* set clocksource timer fixed count to the maximum */
306 mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
308 __raw_writel(0xffffffff,
309 mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
311 /* init and register the timer to the framework */
312 mxs_clocksource_init(timer_clk);
313 mxs_clockevent_init(timer_clk);
315 /* Make irqs happen */
316 irq = irq_of_parse_and_map(np, 0);
317 setup_irq(irq, &mxs_timer_irq);