2 * linux/arch/arm/mach-omap1/clock.c
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Modified to use omap shared clock framework by
8 * Tony Lindgren <tony@atomide.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/export.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/clkdev.h>
23 #include <asm/mach-types.h>
25 #include <mach/hardware.h>
27 #include "../plat-omap/sram.h"
34 __u32 arm_idlect1_mask;
35 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
37 static LIST_HEAD(clocks);
38 static DEFINE_MUTEX(clocks_mutex);
39 static DEFINE_SPINLOCK(clockfw_lock);
42 * Omap1 specific clock functions
45 unsigned long omap1_uart_recalc(struct clk *clk)
47 unsigned int val = __raw_readl(clk->enable_reg);
48 return val & clk->enable_bit ? 48000000 : 12000000;
51 unsigned long omap1_sossi_recalc(struct clk *clk)
53 u32 div = omap_readl(MOD_CONF_CTRL_1);
55 div = (div >> 17) & 0x7;
58 return clk->parent->rate / div;
61 static void omap1_clk_allow_idle(struct clk *clk)
63 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
65 if (!(clk->flags & CLOCK_IDLE_CONTROL))
68 if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
69 arm_idlect1_mask |= 1 << iclk->idlect_shift;
72 static void omap1_clk_deny_idle(struct clk *clk)
74 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
76 if (!(clk->flags & CLOCK_IDLE_CONTROL))
79 if (iclk->no_idle_count++ == 0)
80 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
83 static __u16 verify_ckctl_value(__u16 newval)
85 /* This function checks for following limitations set
86 * by the hardware (all conditions must be true):
87 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
92 * In addition following rules are enforced:
96 * However, maximum frequencies are not checked for!
105 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
106 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
107 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
108 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
109 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
110 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
112 if (dspmmu_exp < dsp_exp)
113 dspmmu_exp = dsp_exp;
114 if (dspmmu_exp > dsp_exp+1)
115 dspmmu_exp = dsp_exp+1;
116 if (tc_exp < arm_exp)
118 if (tc_exp < dspmmu_exp)
120 if (tc_exp > lcd_exp)
122 if (tc_exp > per_exp)
126 newval |= per_exp << CKCTL_PERDIV_OFFSET;
127 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
128 newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
129 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
130 newval |= tc_exp << CKCTL_TCDIV_OFFSET;
131 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
136 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
138 /* Note: If target frequency is too low, this function will return 4,
139 * which is invalid value. Caller must check for this value and act
142 * Note: This function does not check for following limitations set
143 * by the hardware (all conditions must be true):
144 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
149 unsigned long realrate;
153 parent = clk->parent;
154 if (unlikely(parent == NULL))
157 realrate = parent->rate;
158 for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
159 if (realrate <= rate)
168 unsigned long omap1_ckctl_recalc(struct clk *clk)
170 /* Calculate divisor encoded as 2-bit exponent */
171 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
173 return clk->parent->rate / dsor;
176 unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
180 /* Calculate divisor encoded as 2-bit exponent
182 * The clock control bits are in DSP domain,
183 * so api_ck is needed for access.
184 * Note that DSP_CKCTL virt addr = phys addr, so
185 * we must use __raw_readw() instead of omap_readw().
187 omap1_clk_enable(api_ck_p);
188 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
189 omap1_clk_disable(api_ck_p);
191 return clk->parent->rate / dsor;
194 /* MPU virtual clock functions */
195 int omap1_select_table_rate(struct clk *clk, unsigned long rate)
197 /* Find the highest supported frequency <= rate and switch to it */
198 struct mpu_rate * ptr;
199 unsigned long ref_rate;
201 ref_rate = ck_ref_p->rate;
203 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
204 if (!(ptr->flags & cpu_mask))
207 if (ptr->xtal != ref_rate)
210 /* Can check only after xtal frequency check */
211 if (ptr->rate <= rate)
219 * In most cases we should not need to reprogram DPLL.
220 * Reprogramming the DPLL is tricky, it must be done from SRAM.
222 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
224 /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
225 ck_dpll1_p->rate = ptr->pll_rate;
230 int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
235 dsor_exp = calc_dsor_exp(clk, rate);
241 regval = __raw_readw(DSP_CKCTL);
242 regval &= ~(3 << clk->rate_offset);
243 regval |= dsor_exp << clk->rate_offset;
244 __raw_writew(regval, DSP_CKCTL);
245 clk->rate = clk->parent->rate / (1 << dsor_exp);
250 long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
252 int dsor_exp = calc_dsor_exp(clk, rate);
257 return clk->parent->rate / (1 << dsor_exp);
260 int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
265 dsor_exp = calc_dsor_exp(clk, rate);
271 regval = omap_readw(ARM_CKCTL);
272 regval &= ~(3 << clk->rate_offset);
273 regval |= dsor_exp << clk->rate_offset;
274 regval = verify_ckctl_value(regval);
275 omap_writew(regval, ARM_CKCTL);
276 clk->rate = clk->parent->rate / (1 << dsor_exp);
280 long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
282 /* Find the highest supported frequency <= rate */
283 struct mpu_rate * ptr;
285 unsigned long ref_rate;
287 ref_rate = ck_ref_p->rate;
289 highest_rate = -EINVAL;
291 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
292 if (!(ptr->flags & cpu_mask))
295 if (ptr->xtal != ref_rate)
298 highest_rate = ptr->rate;
300 /* Can check only after xtal frequency check */
301 if (ptr->rate <= rate)
308 static unsigned calc_ext_dsor(unsigned long rate)
312 /* MCLK and BCLK divisor selection is not linear:
313 * freq = 96MHz / dsor
315 * RATIO_SEL range: dsor <-> RATIO_SEL
316 * 0..6: (RATIO_SEL+2) <-> (dsor-2)
317 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
318 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
321 for (dsor = 2; dsor < 96; ++dsor) {
322 if ((dsor & 1) && dsor > 8)
324 if (rate >= 96000000 / dsor)
330 /* XXX Only needed on 1510 */
331 int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
335 val = __raw_readl(clk->enable_reg);
336 if (rate == 12000000)
337 val &= ~(1 << clk->enable_bit);
338 else if (rate == 48000000)
339 val |= (1 << clk->enable_bit);
342 __raw_writel(val, clk->enable_reg);
348 /* External clock (MCLK & BCLK) functions */
349 int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
354 dsor = calc_ext_dsor(rate);
355 clk->rate = 96000000 / dsor;
357 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
359 ratio_bits = (dsor - 2) << 2;
361 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
362 __raw_writew(ratio_bits, clk->enable_reg);
367 int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
371 unsigned long p_rate;
373 p_rate = clk->parent->rate;
374 /* Round towards slower frequency */
375 div = (p_rate + rate - 1) / rate;
377 if (div < 0 || div > 7)
380 l = omap_readl(MOD_CONF_CTRL_1);
383 omap_writel(l, MOD_CONF_CTRL_1);
385 clk->rate = p_rate / (div + 1);
390 long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
392 return 96000000 / calc_ext_dsor(rate);
395 void omap1_init_ext_clk(struct clk *clk)
400 /* Determine current rate and ensure clock is based on 96MHz APLL */
401 ratio_bits = __raw_readw(clk->enable_reg) & ~1;
402 __raw_writew(ratio_bits, clk->enable_reg);
404 ratio_bits = (ratio_bits & 0xfc) >> 2;
406 dsor = (ratio_bits - 6) * 2 + 8;
408 dsor = ratio_bits + 2;
410 clk-> rate = 96000000 / dsor;
413 int omap1_clk_enable(struct clk *clk)
417 if (clk->usecount++ == 0) {
419 ret = omap1_clk_enable(clk->parent);
423 if (clk->flags & CLOCK_NO_IDLE_PARENT)
424 omap1_clk_deny_idle(clk->parent);
427 ret = clk->ops->enable(clk);
430 omap1_clk_disable(clk->parent);
441 void omap1_clk_disable(struct clk *clk)
443 if (clk->usecount > 0 && !(--clk->usecount)) {
444 clk->ops->disable(clk);
445 if (likely(clk->parent)) {
446 omap1_clk_disable(clk->parent);
447 if (clk->flags & CLOCK_NO_IDLE_PARENT)
448 omap1_clk_allow_idle(clk->parent);
453 static int omap1_clk_enable_generic(struct clk *clk)
458 if (unlikely(clk->enable_reg == NULL)) {
459 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
464 if (clk->flags & ENABLE_REG_32BIT) {
465 regval32 = __raw_readl(clk->enable_reg);
466 regval32 |= (1 << clk->enable_bit);
467 __raw_writel(regval32, clk->enable_reg);
469 regval16 = __raw_readw(clk->enable_reg);
470 regval16 |= (1 << clk->enable_bit);
471 __raw_writew(regval16, clk->enable_reg);
477 static void omap1_clk_disable_generic(struct clk *clk)
482 if (clk->enable_reg == NULL)
485 if (clk->flags & ENABLE_REG_32BIT) {
486 regval32 = __raw_readl(clk->enable_reg);
487 regval32 &= ~(1 << clk->enable_bit);
488 __raw_writel(regval32, clk->enable_reg);
490 regval16 = __raw_readw(clk->enable_reg);
491 regval16 &= ~(1 << clk->enable_bit);
492 __raw_writew(regval16, clk->enable_reg);
496 const struct clkops clkops_generic = {
497 .enable = omap1_clk_enable_generic,
498 .disable = omap1_clk_disable_generic,
501 static int omap1_clk_enable_dsp_domain(struct clk *clk)
505 retval = omap1_clk_enable(api_ck_p);
507 retval = omap1_clk_enable_generic(clk);
508 omap1_clk_disable(api_ck_p);
514 static void omap1_clk_disable_dsp_domain(struct clk *clk)
516 if (omap1_clk_enable(api_ck_p) == 0) {
517 omap1_clk_disable_generic(clk);
518 omap1_clk_disable(api_ck_p);
522 const struct clkops clkops_dspck = {
523 .enable = omap1_clk_enable_dsp_domain,
524 .disable = omap1_clk_disable_dsp_domain,
527 /* XXX SYSC register handling does not belong in the clock framework */
528 static int omap1_clk_enable_uart_functional_16xx(struct clk *clk)
531 struct uart_clk *uclk;
533 ret = omap1_clk_enable_generic(clk);
535 /* Set smart idle acknowledgement mode */
536 uclk = (struct uart_clk *)clk;
537 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
544 /* XXX SYSC register handling does not belong in the clock framework */
545 static void omap1_clk_disable_uart_functional_16xx(struct clk *clk)
547 struct uart_clk *uclk;
549 /* Set force idle acknowledgement mode */
550 uclk = (struct uart_clk *)clk;
551 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
553 omap1_clk_disable_generic(clk);
556 /* XXX SYSC register handling does not belong in the clock framework */
557 const struct clkops clkops_uart_16xx = {
558 .enable = omap1_clk_enable_uart_functional_16xx,
559 .disable = omap1_clk_disable_uart_functional_16xx,
562 long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
564 if (clk->round_rate != NULL)
565 return clk->round_rate(clk, rate);
570 int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
575 ret = clk->set_rate(clk, rate);
580 * Omap1 clock reset and init functions
583 #ifdef CONFIG_OMAP_RESET_CLOCKS
585 void omap1_clk_disable_unused(struct clk *clk)
589 /* Clocks in the DSP domain need api_ck. Just assume bootloader
590 * has not enabled any DSP clocks */
591 if (clk->enable_reg == DSP_IDLECT2) {
592 pr_info("Skipping reset check for DSP domain clock \"%s\"\n",
597 /* Is the clock already disabled? */
598 if (clk->flags & ENABLE_REG_32BIT)
599 regval32 = __raw_readl(clk->enable_reg);
601 regval32 = __raw_readw(clk->enable_reg);
603 if ((regval32 & (1 << clk->enable_bit)) == 0)
606 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
607 clk->ops->disable(clk);
614 int clk_enable(struct clk *clk)
619 if (clk == NULL || IS_ERR(clk))
622 spin_lock_irqsave(&clockfw_lock, flags);
623 ret = omap1_clk_enable(clk);
624 spin_unlock_irqrestore(&clockfw_lock, flags);
628 EXPORT_SYMBOL(clk_enable);
630 void clk_disable(struct clk *clk)
634 if (clk == NULL || IS_ERR(clk))
637 spin_lock_irqsave(&clockfw_lock, flags);
638 if (clk->usecount == 0) {
639 pr_err("Trying disable clock %s with 0 usecount\n",
645 omap1_clk_disable(clk);
648 spin_unlock_irqrestore(&clockfw_lock, flags);
650 EXPORT_SYMBOL(clk_disable);
652 unsigned long clk_get_rate(struct clk *clk)
657 if (clk == NULL || IS_ERR(clk))
660 spin_lock_irqsave(&clockfw_lock, flags);
662 spin_unlock_irqrestore(&clockfw_lock, flags);
666 EXPORT_SYMBOL(clk_get_rate);
669 * Optional clock functions defined in include/linux/clk.h
672 long clk_round_rate(struct clk *clk, unsigned long rate)
677 if (clk == NULL || IS_ERR(clk))
680 spin_lock_irqsave(&clockfw_lock, flags);
681 ret = omap1_clk_round_rate(clk, rate);
682 spin_unlock_irqrestore(&clockfw_lock, flags);
686 EXPORT_SYMBOL(clk_round_rate);
688 int clk_set_rate(struct clk *clk, unsigned long rate)
693 if (clk == NULL || IS_ERR(clk))
696 spin_lock_irqsave(&clockfw_lock, flags);
697 ret = omap1_clk_set_rate(clk, rate);
700 spin_unlock_irqrestore(&clockfw_lock, flags);
704 EXPORT_SYMBOL(clk_set_rate);
706 int clk_set_parent(struct clk *clk, struct clk *parent)
708 WARN_ONCE(1, "clk_set_parent() not implemented for OMAP1\n");
712 EXPORT_SYMBOL(clk_set_parent);
714 struct clk *clk_get_parent(struct clk *clk)
718 EXPORT_SYMBOL(clk_get_parent);
721 * OMAP specific clock functions shared between omap1 and omap2
724 int __initdata mpurate;
727 * By default we use the rate set by the bootloader.
728 * You can override this with mpurate= cmdline option.
730 static int __init omap_clk_setup(char *str)
732 get_option(&str, &mpurate);
742 __setup("mpurate=", omap_clk_setup);
744 /* Used for clocks that always have same value as the parent clock */
745 unsigned long followparent_recalc(struct clk *clk)
747 return clk->parent->rate;
751 * Used for clocks that have the same value as the parent clock,
752 * divided by some factor
754 unsigned long omap_fixed_divisor_recalc(struct clk *clk)
756 WARN_ON(!clk->fixed_div);
758 return clk->parent->rate / clk->fixed_div;
761 void clk_reparent(struct clk *child, struct clk *parent)
763 list_del_init(&child->sibling);
765 list_add(&child->sibling, &parent->children);
766 child->parent = parent;
768 /* now do the debugfs renaming to reattach the child
769 to the proper parent */
772 /* Propagate rate to children */
773 void propagate_rate(struct clk *tclk)
777 list_for_each_entry(clkp, &tclk->children, sibling) {
779 clkp->rate = clkp->recalc(clkp);
780 propagate_rate(clkp);
784 static LIST_HEAD(root_clks);
787 * recalculate_root_clocks - recalculate and propagate all root clocks
789 * Recalculates all root clocks (clocks with no parent), which if the
790 * clock's .recalc is set correctly, should also propagate their rates.
793 void recalculate_root_clocks(void)
797 list_for_each_entry(clkp, &root_clks, sibling) {
799 clkp->rate = clkp->recalc(clkp);
800 propagate_rate(clkp);
805 * clk_preinit - initialize any fields in the struct clk before clk init
806 * @clk: struct clk * to initialize
808 * Initialize any struct clk fields needed before normal clk initialization
809 * can run. No return value.
811 void clk_preinit(struct clk *clk)
813 INIT_LIST_HEAD(&clk->children);
816 int clk_register(struct clk *clk)
818 if (clk == NULL || IS_ERR(clk))
822 * trap out already registered clocks
824 if (clk->node.next || clk->node.prev)
827 mutex_lock(&clocks_mutex);
829 list_add(&clk->sibling, &clk->parent->children);
831 list_add(&clk->sibling, &root_clks);
833 list_add(&clk->node, &clocks);
836 mutex_unlock(&clocks_mutex);
840 EXPORT_SYMBOL(clk_register);
842 void clk_unregister(struct clk *clk)
844 if (clk == NULL || IS_ERR(clk))
847 mutex_lock(&clocks_mutex);
848 list_del(&clk->sibling);
849 list_del(&clk->node);
850 mutex_unlock(&clocks_mutex);
852 EXPORT_SYMBOL(clk_unregister);
854 void clk_enable_init_clocks(void)
858 list_for_each_entry(clkp, &clocks, node)
859 if (clkp->flags & ENABLE_ON_INIT)
864 * omap_clk_get_by_name - locate OMAP struct clk by its name
865 * @name: name of the struct clk to locate
867 * Locate an OMAP struct clk by its name. Assumes that struct clk
868 * names are unique. Returns NULL if not found or a pointer to the
869 * struct clk if found.
871 struct clk *omap_clk_get_by_name(const char *name)
874 struct clk *ret = NULL;
876 mutex_lock(&clocks_mutex);
878 list_for_each_entry(c, &clocks, node) {
879 if (!strcmp(c->name, name)) {
885 mutex_unlock(&clocks_mutex);
890 int omap_clk_enable_autoidle_all(void)
895 spin_lock_irqsave(&clockfw_lock, flags);
897 list_for_each_entry(c, &clocks, node)
898 if (c->ops->allow_idle)
899 c->ops->allow_idle(c);
901 spin_unlock_irqrestore(&clockfw_lock, flags);
906 int omap_clk_disable_autoidle_all(void)
911 spin_lock_irqsave(&clockfw_lock, flags);
913 list_for_each_entry(c, &clocks, node)
914 if (c->ops->deny_idle)
915 c->ops->deny_idle(c);
917 spin_unlock_irqrestore(&clockfw_lock, flags);
925 static int clkll_enable_null(struct clk *clk)
930 static void clkll_disable_null(struct clk *clk)
934 const struct clkops clkops_null = {
935 .enable = clkll_enable_null,
936 .disable = clkll_disable_null,
942 * Used for clock aliases that are needed on some OMAPs, but not others
944 struct clk dummy_ck = {
953 #ifdef CONFIG_OMAP_RESET_CLOCKS
955 * Disable any unused clocks left on by the bootloader
957 static int __init clk_disable_unused(void)
962 pr_info("clock: disabling unused clocks to save power\n");
964 spin_lock_irqsave(&clockfw_lock, flags);
965 list_for_each_entry(ck, &clocks, node) {
966 if (ck->ops == &clkops_null)
969 if (ck->usecount > 0 || !ck->enable_reg)
972 omap1_clk_disable_unused(ck);
974 spin_unlock_irqrestore(&clockfw_lock, flags);
978 late_initcall(clk_disable_unused);
979 late_initcall(omap_clk_enable_autoidle_all);
982 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
984 * debugfs support to trace clock tree hierarchy and attributes
987 #include <linux/debugfs.h>
988 #include <linux/seq_file.h>
990 static struct dentry *clk_debugfs_root;
992 static int clk_dbg_show_summary(struct seq_file *s, void *unused)
997 mutex_lock(&clocks_mutex);
998 seq_printf(s, "%-30s %-30s %-10s %s\n",
999 "clock-name", "parent-name", "rate", "use-count");
1001 list_for_each_entry(c, &clocks, node) {
1003 seq_printf(s, "%-30s %-30s %-10lu %d\n",
1004 c->name, pa ? pa->name : "none", c->rate,
1007 mutex_unlock(&clocks_mutex);
1012 static int clk_dbg_open(struct inode *inode, struct file *file)
1014 return single_open(file, clk_dbg_show_summary, inode->i_private);
1017 static const struct file_operations debug_clock_fops = {
1018 .open = clk_dbg_open,
1020 .llseek = seq_lseek,
1021 .release = single_release,
1024 static int clk_debugfs_register_one(struct clk *c)
1028 struct clk *pa = c->parent;
1030 d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
1035 d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
1040 d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
1045 d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
1053 debugfs_remove_recursive(c->dent);
1057 static int clk_debugfs_register(struct clk *c)
1060 struct clk *pa = c->parent;
1062 if (pa && !pa->dent) {
1063 err = clk_debugfs_register(pa);
1069 err = clk_debugfs_register_one(c);
1076 static int __init clk_debugfs_init(void)
1082 d = debugfs_create_dir("clock", NULL);
1085 clk_debugfs_root = d;
1087 list_for_each_entry(c, &clocks, node) {
1088 err = clk_debugfs_register(c);
1093 d = debugfs_create_file("summary", S_IRUGO,
1094 d, NULL, &debug_clock_fops);
1100 debugfs_remove_recursive(clk_debugfs_root);
1103 late_initcall(clk_debugfs_init);
1105 #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */