2 * OMAP1/OMAP7xx - specific DMA driver
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
13 * Converted DMA library into platform driver
14 * - G, Manjunath Kondaiah <manjugk@ti.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/err.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/device.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/omap-dma.h>
31 #include <mach/irqs.h>
35 #define OMAP1_DMA_BASE (0xfffed800)
36 #define OMAP1_LOGICAL_DMA_CH_COUNT 17
37 #define OMAP1_DMA_STRIDE 0x40
40 static u32 enable_1510_mode;
42 static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
44 static u16 reg_map[] = {
64 /* Common Registers */
73 [CPC] = 0x18, /* 15xx only */
80 /* Channel specific register offsets */
88 static struct resource res[] __initdata = {
90 .start = OMAP1_DMA_BASE,
91 .end = OMAP1_DMA_BASE + SZ_2K - 1,
92 .flags = IORESOURCE_MEM,
96 .start = INT_DMA_CH0_6,
97 .flags = IORESOURCE_IRQ,
101 .start = INT_DMA_CH1_7,
102 .flags = IORESOURCE_IRQ,
106 .start = INT_DMA_CH2_8,
107 .flags = IORESOURCE_IRQ,
111 .start = INT_DMA_CH3,
112 .flags = IORESOURCE_IRQ,
116 .start = INT_DMA_CH4,
117 .flags = IORESOURCE_IRQ,
121 .start = INT_DMA_CH5,
122 .flags = IORESOURCE_IRQ,
124 /* Handled in lcd_dma.c */
127 .start = INT_1610_DMA_CH6,
128 .flags = IORESOURCE_IRQ,
130 /* irq's for omap16xx and omap7xx */
133 .start = INT_1610_DMA_CH7,
134 .flags = IORESOURCE_IRQ,
138 .start = INT_1610_DMA_CH8,
139 .flags = IORESOURCE_IRQ,
143 .start = INT_1610_DMA_CH9,
144 .flags = IORESOURCE_IRQ,
148 .start = INT_1610_DMA_CH10,
149 .flags = IORESOURCE_IRQ,
153 .start = INT_1610_DMA_CH11,
154 .flags = IORESOURCE_IRQ,
158 .start = INT_1610_DMA_CH12,
159 .flags = IORESOURCE_IRQ,
163 .start = INT_1610_DMA_CH13,
164 .flags = IORESOURCE_IRQ,
168 .start = INT_1610_DMA_CH14,
169 .flags = IORESOURCE_IRQ,
173 .start = INT_1610_DMA_CH15,
174 .flags = IORESOURCE_IRQ,
178 .start = INT_DMA_LCD,
179 .flags = IORESOURCE_IRQ,
183 static void __iomem *dma_base;
184 static inline void dma_write(u32 val, int reg, int lch)
189 stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
190 offset = reg_map[reg] + (stride * lch);
192 __raw_writew(val, dma_base + offset);
193 if ((reg > CLNK_CTRL && reg < CCEN) ||
194 (reg > PCHD_ID && reg < CAPS_2)) {
195 u32 offset2 = reg_map[reg] + 2 + (stride * lch);
196 __raw_writew(val >> 16, dma_base + offset2);
200 static inline u32 dma_read(int reg, int lch)
205 stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
206 offset = reg_map[reg] + (stride * lch);
208 val = __raw_readw(dma_base + offset);
209 if ((reg > CLNK_CTRL && reg < CCEN) ||
210 (reg > PCHD_ID && reg < CAPS_2)) {
212 u32 offset2 = reg_map[reg] + 2 + (stride * lch);
213 upper = __raw_readw(dma_base + offset2);
214 val |= (upper << 16);
219 static void omap1_clear_lch_regs(int lch)
221 int i = dma_common_ch_start;
223 for (; i <= dma_common_ch_end; i += 1)
224 dma_write(0, i, lch);
227 static void omap1_clear_dma(int lch)
231 l = dma_read(CCR, lch);
232 l &= ~OMAP_DMA_CCR_EN;
233 dma_write(l, CCR, lch);
235 /* Clear pending interrupts */
236 l = dma_read(CSR, lch);
239 static void omap1_show_dma_caps(void)
241 if (enable_1510_mode) {
242 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
245 printk(KERN_INFO "OMAP DMA hardware version %d\n",
247 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
248 dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
249 dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
250 dma_read(CAPS_4, 0));
252 /* Disable OMAP 3.0/3.1 compatibility mode. */
253 w = dma_read(GSCR, 0);
255 dma_write(w, GSCR, 0);
260 static u32 configure_dma_errata(void)
264 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
265 * read before the DMA controller finished disabling the channel.
267 if (!cpu_is_omap15xx())
268 SET_DMA_ERRATA(DMA_ERRATA_3_3);
273 static const struct platform_device_info omap_dma_dev_info = {
274 .name = "omap-dma-engine",
276 .dma_mask = DMA_BIT_MASK(32),
279 static int __init omap1_system_dma_init(void)
281 struct omap_system_dma_plat_info *p;
282 struct omap_dma_dev_attr *d;
283 struct platform_device *pdev, *dma_pdev;
286 pdev = platform_device_alloc("omap_dma_system", 0);
288 pr_err("%s: Unable to device alloc for dma\n",
293 dma_base = ioremap(res[0].start, resource_size(&res[0]));
295 pr_err("%s: Unable to ioremap\n", __func__);
297 goto exit_device_put;
300 ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
302 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
303 __func__, pdev->name, pdev->id);
304 goto exit_device_put;
307 p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
309 dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
310 __func__, pdev->name);
312 goto exit_device_del;
315 d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
317 dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
318 __func__, pdev->name);
323 d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
325 /* Valid attributes for omap1 plus processors */
326 if (cpu_is_omap15xx())
327 d->dev_caps = ENABLE_1510_MODE;
328 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
330 if (cpu_is_omap16xx())
331 d->dev_caps = ENABLE_16XX_MODE;
333 d->dev_caps |= SRC_PORT;
334 d->dev_caps |= DST_PORT;
335 d->dev_caps |= SRC_INDEX;
336 d->dev_caps |= DST_INDEX;
337 d->dev_caps |= IS_BURST_ONLY4;
338 d->dev_caps |= CLEAR_CSR_ON_READ;
339 d->dev_caps |= IS_WORD_16;
342 d->chan = kzalloc(sizeof(struct omap_dma_lch) *
343 (d->lch_count), GFP_KERNEL);
346 "%s: Memory allocation failed for d->chan!\n",
351 if (cpu_is_omap15xx())
353 else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
354 if (!(d->dev_caps & ENABLE_1510_MODE))
362 p->show_dma_caps = omap1_show_dma_caps;
363 p->clear_lch_regs = omap1_clear_lch_regs;
364 p->clear_dma = omap1_clear_dma;
365 p->dma_write = dma_write;
366 p->dma_read = dma_read;
367 p->disable_irq_lch = NULL;
369 p->errata = configure_dma_errata();
371 ret = platform_device_add_data(pdev, p, sizeof(*p));
373 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
374 __func__, pdev->name, pdev->id);
375 goto exit_release_chan;
378 ret = platform_device_add(pdev);
380 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
381 __func__, pdev->name, pdev->id);
382 goto exit_release_chan;
385 dma_stride = OMAP1_DMA_STRIDE;
386 dma_common_ch_start = CPC;
387 dma_common_ch_end = COLOR;
389 dma_pdev = platform_device_register_full(&omap_dma_dev_info);
390 if (IS_ERR(dma_pdev)) {
391 ret = PTR_ERR(dma_pdev);
392 goto exit_release_pdev;
398 platform_device_del(pdev);
406 platform_device_del(pdev);
408 platform_device_put(pdev);
412 arch_initcall(omap1_system_dma_init);