2 * linux/arch/arm/mach-omap1/pm.c
4 * OMAP Power Management Routines
6 * Original code for the SA11x0:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
9 * Modified for the PXA250 by Nicolas Pitre:
10 * Copyright (c) 2002 Monta Vista Software, Inc.
12 * Modified for the OMAP1510 by David Singleton:
13 * Copyright (c) 2002 Monta Vista Software, Inc.
15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 #include <linux/suspend.h>
39 #include <linux/sched.h>
40 #include <linux/debugfs.h>
41 #include <linux/seq_file.h>
42 #include <linux/interrupt.h>
43 #include <linux/sysfs.h>
44 #include <linux/module.h>
46 #include <linux/atomic.h>
47 #include <linux/cpu.h>
49 #include <asm/fncpy.h>
50 #include <asm/system_misc.h>
52 #include <asm/mach/time.h>
53 #include <asm/mach/irq.h>
57 #include <linux/omap-dma.h>
58 #include <plat/dmtimer.h>
60 #include <mach/irqs.h>
67 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
68 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
69 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
70 static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
71 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
72 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
74 #ifndef CONFIG_OMAP_32K_TIMER
76 static unsigned short enable_dyn_sleep = 0;
80 static unsigned short enable_dyn_sleep = 1;
82 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
85 return sprintf(buf, "%hu\n", enable_dyn_sleep);
88 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
89 const char * buf, size_t n)
92 if (sscanf(buf, "%hu", &value) != 1 ||
93 (value != 0 && value != 1)) {
94 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
97 enable_dyn_sleep = value;
101 static struct kobj_attribute sleep_while_idle_attr =
102 __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
106 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
109 * Let's power down on idle, but only if we are really
110 * idle, because once we start down the path of
111 * going idle we continue to do idle even if we get
112 * a clock tick interrupt . .
114 void omap1_pm_idle(void)
116 extern __u32 arm_idlect1_mask;
117 __u32 use_idlect1 = arm_idlect1_mask;
122 #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
123 #warning Enable 32kHz OS timer in order to allow sleep states in idle
124 use_idlect1 = use_idlect1 & ~(1 << 9);
127 while (enable_dyn_sleep) {
129 #ifdef CONFIG_CBUS_TAHVO_USB
130 extern int vbus_active;
131 /* Clock requirements? */
141 #ifdef CONFIG_OMAP_DM_TIMER
142 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
145 if (omap_dma_running())
146 use_idlect1 &= ~(1 << 6);
148 /* We should be able to remove the do_sleep variable and multiple
149 * tests above as soon as drivers, timer and DMA code have been fixed.
150 * Even the sleep block count should become obsolete. */
151 if ((use_idlect1 != ~0) || !do_sleep) {
153 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
154 if (cpu_is_omap15xx())
155 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
157 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
158 omap_writel(use_idlect1, ARM_IDLECT1);
159 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
160 omap_writel(saved_idlect1, ARM_IDLECT1);
165 omap_sram_suspend(omap_readl(ARM_IDLECT1),
166 omap_readl(ARM_IDLECT2));
172 * Configuration of the wakeup event is board specific. For the
173 * moment we put it into this helper function. Later it may move
174 * to board specific files.
176 static void omap_pm_wakeup_setup(void)
179 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
182 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
183 * and the L2 wakeup interrupts: keypad and UART2. Note that the
184 * drivers must still separately call omap_set_gpio_wakeup() to
185 * wake up to a GPIO interrupt.
187 if (cpu_is_omap7xx())
188 level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
189 OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
190 else if (cpu_is_omap15xx())
191 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
192 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
193 else if (cpu_is_omap16xx())
194 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
195 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
197 omap_writel(~level1_wake, OMAP_IH1_MIR);
199 if (cpu_is_omap7xx()) {
200 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
201 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
202 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
204 } else if (cpu_is_omap15xx()) {
205 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
206 omap_writel(~level2_wake, OMAP_IH2_MIR);
207 } else if (cpu_is_omap16xx()) {
208 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
209 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
211 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
212 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
214 omap_writel(~0x0, OMAP_IH2_2_MIR);
215 omap_writel(~0x0, OMAP_IH2_3_MIR);
218 /* New IRQ agreement, recalculate in cascade order */
219 omap_writel(1, OMAP_IH2_CONTROL);
220 omap_writel(1, OMAP_IH1_CONTROL);
223 #define EN_DSPCK 13 /* ARM_CKCTL */
224 #define EN_APICK 6 /* ARM_IDLECT2 */
225 #define DSP_EN 1 /* ARM_RSTCT1 */
227 void omap1_pm_suspend(void)
229 unsigned long arg0 = 0, arg1 = 0;
231 printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
234 omap_serial_wake_trigger(1);
236 if (!cpu_is_omap15xx())
237 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
240 * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
247 * Step 2: save registers
249 * The omap is a strange/beautiful device. The caches, memory
250 * and register state are preserved across power saves.
251 * We have to save and restore very little register state to
254 * Save interrupt, MPUI, ARM and UPLD control registers.
257 if (cpu_is_omap7xx()) {
258 MPUI7XX_SAVE(OMAP_IH1_MIR);
259 MPUI7XX_SAVE(OMAP_IH2_0_MIR);
260 MPUI7XX_SAVE(OMAP_IH2_1_MIR);
261 MPUI7XX_SAVE(MPUI_CTRL);
262 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
263 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
264 MPUI7XX_SAVE(EMIFS_CONFIG);
265 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
267 } else if (cpu_is_omap15xx()) {
268 MPUI1510_SAVE(OMAP_IH1_MIR);
269 MPUI1510_SAVE(OMAP_IH2_MIR);
270 MPUI1510_SAVE(MPUI_CTRL);
271 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
272 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
273 MPUI1510_SAVE(EMIFS_CONFIG);
274 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
275 } else if (cpu_is_omap16xx()) {
276 MPUI1610_SAVE(OMAP_IH1_MIR);
277 MPUI1610_SAVE(OMAP_IH2_0_MIR);
278 MPUI1610_SAVE(OMAP_IH2_1_MIR);
279 MPUI1610_SAVE(OMAP_IH2_2_MIR);
280 MPUI1610_SAVE(OMAP_IH2_3_MIR);
281 MPUI1610_SAVE(MPUI_CTRL);
282 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
283 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
284 MPUI1610_SAVE(EMIFS_CONFIG);
285 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
289 ARM_SAVE(ARM_IDLECT1);
290 ARM_SAVE(ARM_IDLECT2);
291 if (!(cpu_is_omap15xx()))
292 ARM_SAVE(ARM_IDLECT3);
293 ARM_SAVE(ARM_EWUPCT);
294 ARM_SAVE(ARM_RSTCT1);
295 ARM_SAVE(ARM_RSTCT2);
297 ULPD_SAVE(ULPD_CLOCK_CTRL);
298 ULPD_SAVE(ULPD_STATUS_REQ);
300 /* (Step 3 removed - we now allow deep sleep by default) */
303 * Step 4: OMAP DSP Shutdown
307 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
309 /* shut down dsp_ck */
310 if (!cpu_is_omap7xx())
311 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
313 /* temporarily enabling api_ck to access DSP registers */
314 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
316 /* save DSP registers */
317 DSP_SAVE(DSP_IDLECT2);
319 /* Stop all DSP domain clocks */
320 __raw_writew(0, DSP_IDLECT2);
323 * Step 5: Wakeup Event Setup
326 omap_pm_wakeup_setup();
329 * Step 6: ARM and Traffic controller shutdown
332 /* disable ARM watchdog */
333 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
334 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
337 * Step 6b: ARM and Traffic controller shutdown
339 * Step 6 continues here. Prepare jump to power management
340 * assembly code in internal SRAM.
342 * Since the omap_cpu_suspend routine has been copied to
343 * SRAM, we'll do an indirect procedure call to it and pass the
344 * contents of arm_idlect1 and arm_idlect2 so it can restore
345 * them when it wakes up and it will return.
348 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
349 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
352 * Step 6c: ARM and Traffic controller shutdown
354 * Jump to assembly code. The processor will stay there
357 omap_sram_suspend(arg0, arg1);
360 * If we are here, processor is woken up!
367 /* again temporarily enabling api_ck to access DSP registers */
368 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
370 /* Restore DSP domain clocks */
371 DSP_RESTORE(DSP_IDLECT2);
374 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
377 if (!(cpu_is_omap15xx()))
378 ARM_RESTORE(ARM_IDLECT3);
379 ARM_RESTORE(ARM_CKCTL);
380 ARM_RESTORE(ARM_EWUPCT);
381 ARM_RESTORE(ARM_RSTCT1);
382 ARM_RESTORE(ARM_RSTCT2);
383 ARM_RESTORE(ARM_SYSST);
384 ULPD_RESTORE(ULPD_CLOCK_CTRL);
385 ULPD_RESTORE(ULPD_STATUS_REQ);
387 if (cpu_is_omap7xx()) {
388 MPUI7XX_RESTORE(EMIFS_CONFIG);
389 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
390 MPUI7XX_RESTORE(OMAP_IH1_MIR);
391 MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
392 MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
393 } else if (cpu_is_omap15xx()) {
394 MPUI1510_RESTORE(MPUI_CTRL);
395 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
396 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
397 MPUI1510_RESTORE(EMIFS_CONFIG);
398 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
399 MPUI1510_RESTORE(OMAP_IH1_MIR);
400 MPUI1510_RESTORE(OMAP_IH2_MIR);
401 } else if (cpu_is_omap16xx()) {
402 MPUI1610_RESTORE(MPUI_CTRL);
403 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
404 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
405 MPUI1610_RESTORE(EMIFS_CONFIG);
406 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
408 MPUI1610_RESTORE(OMAP_IH1_MIR);
409 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
410 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
411 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
412 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
415 if (!cpu_is_omap15xx())
416 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
419 * Re-enable interrupts
425 omap_serial_wake_trigger(0);
427 printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
431 #ifdef CONFIG_DEBUG_FS
433 * Read system PM registers for debugging
435 static int omap_pm_debug_show(struct seq_file *m, void *v)
438 ARM_SAVE(ARM_IDLECT1);
439 ARM_SAVE(ARM_IDLECT2);
440 if (!(cpu_is_omap15xx()))
441 ARM_SAVE(ARM_IDLECT3);
442 ARM_SAVE(ARM_EWUPCT);
443 ARM_SAVE(ARM_RSTCT1);
444 ARM_SAVE(ARM_RSTCT2);
447 ULPD_SAVE(ULPD_IT_STATUS);
448 ULPD_SAVE(ULPD_CLOCK_CTRL);
449 ULPD_SAVE(ULPD_SOFT_REQ);
450 ULPD_SAVE(ULPD_STATUS_REQ);
451 ULPD_SAVE(ULPD_DPLL_CTRL);
452 ULPD_SAVE(ULPD_POWER_CTRL);
454 if (cpu_is_omap7xx()) {
455 MPUI7XX_SAVE(MPUI_CTRL);
456 MPUI7XX_SAVE(MPUI_DSP_STATUS);
457 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
458 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
459 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
460 MPUI7XX_SAVE(EMIFS_CONFIG);
461 } else if (cpu_is_omap15xx()) {
462 MPUI1510_SAVE(MPUI_CTRL);
463 MPUI1510_SAVE(MPUI_DSP_STATUS);
464 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
465 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
466 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
467 MPUI1510_SAVE(EMIFS_CONFIG);
468 } else if (cpu_is_omap16xx()) {
469 MPUI1610_SAVE(MPUI_CTRL);
470 MPUI1610_SAVE(MPUI_DSP_STATUS);
471 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
472 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
473 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
474 MPUI1610_SAVE(EMIFS_CONFIG);
478 "ARM_CKCTL_REG: 0x%-8x \n"
479 "ARM_IDLECT1_REG: 0x%-8x \n"
480 "ARM_IDLECT2_REG: 0x%-8x \n"
481 "ARM_IDLECT3_REG: 0x%-8x \n"
482 "ARM_EWUPCT_REG: 0x%-8x \n"
483 "ARM_RSTCT1_REG: 0x%-8x \n"
484 "ARM_RSTCT2_REG: 0x%-8x \n"
485 "ARM_SYSST_REG: 0x%-8x \n"
486 "ULPD_IT_STATUS_REG: 0x%-4x \n"
487 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
488 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
489 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
490 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
491 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
493 ARM_SHOW(ARM_IDLECT1),
494 ARM_SHOW(ARM_IDLECT2),
495 ARM_SHOW(ARM_IDLECT3),
496 ARM_SHOW(ARM_EWUPCT),
497 ARM_SHOW(ARM_RSTCT1),
498 ARM_SHOW(ARM_RSTCT2),
500 ULPD_SHOW(ULPD_IT_STATUS),
501 ULPD_SHOW(ULPD_CLOCK_CTRL),
502 ULPD_SHOW(ULPD_SOFT_REQ),
503 ULPD_SHOW(ULPD_DPLL_CTRL),
504 ULPD_SHOW(ULPD_STATUS_REQ),
505 ULPD_SHOW(ULPD_POWER_CTRL));
507 if (cpu_is_omap7xx()) {
509 "MPUI7XX_CTRL_REG 0x%-8x \n"
510 "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
511 "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
512 "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
513 "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
514 "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
515 MPUI7XX_SHOW(MPUI_CTRL),
516 MPUI7XX_SHOW(MPUI_DSP_STATUS),
517 MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
518 MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
519 MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
520 MPUI7XX_SHOW(EMIFS_CONFIG));
521 } else if (cpu_is_omap15xx()) {
523 "MPUI1510_CTRL_REG 0x%-8x \n"
524 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
525 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
526 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
527 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
528 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
529 MPUI1510_SHOW(MPUI_CTRL),
530 MPUI1510_SHOW(MPUI_DSP_STATUS),
531 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
532 MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
533 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
534 MPUI1510_SHOW(EMIFS_CONFIG));
535 } else if (cpu_is_omap16xx()) {
537 "MPUI1610_CTRL_REG 0x%-8x \n"
538 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
539 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
540 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
541 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
542 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
543 MPUI1610_SHOW(MPUI_CTRL),
544 MPUI1610_SHOW(MPUI_DSP_STATUS),
545 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
546 MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
547 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
548 MPUI1610_SHOW(EMIFS_CONFIG));
554 static int omap_pm_debug_open(struct inode *inode, struct file *file)
556 return single_open(file, omap_pm_debug_show,
560 static const struct file_operations omap_pm_debug_fops = {
561 .open = omap_pm_debug_open,
564 .release = single_release,
567 static void omap_pm_init_debugfs(void)
571 d = debugfs_create_dir("pm_debug", NULL);
575 (void) debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO,
576 d, NULL, &omap_pm_debug_fops);
579 #endif /* CONFIG_DEBUG_FS */
582 * omap_pm_prepare - Do preliminary suspend work.
585 static int omap_pm_prepare(void)
587 /* We cannot sleep in idle until we have resumed */
588 cpu_idle_poll_ctrl(true);
594 * omap_pm_enter - Actually enter a sleep state.
595 * @state: State we're entering.
599 static int omap_pm_enter(suspend_state_t state)
603 case PM_SUSPEND_STANDBY:
616 * omap_pm_finish - Finish up suspend sequence.
618 * This is called after we wake back up (or if entering the sleep state
622 static void omap_pm_finish(void)
624 cpu_idle_poll_ctrl(false);
628 static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
633 static struct irqaction omap_wakeup_irq = {
634 .name = "peripheral wakeup",
635 .handler = omap_wakeup_interrupt
640 static const struct platform_suspend_ops omap_pm_ops = {
641 .prepare = omap_pm_prepare,
642 .enter = omap_pm_enter,
643 .finish = omap_pm_finish,
644 .valid = suspend_valid_only_mem,
647 static int __init omap_pm_init(void)
650 #ifdef CONFIG_OMAP_32K_TIMER
654 if (!cpu_class_is_omap1())
657 printk("Power Management for TI OMAP.\n");
660 * We copy the assembler sleep/wakeup routines to SRAM.
661 * These routines need to be in SRAM as that's the only
662 * memory the MPU can see when it wakes up.
664 if (cpu_is_omap7xx()) {
665 omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
666 omap7xx_cpu_suspend_sz);
667 } else if (cpu_is_omap15xx()) {
668 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
669 omap1510_cpu_suspend_sz);
670 } else if (cpu_is_omap16xx()) {
671 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
672 omap1610_cpu_suspend_sz);
675 if (omap_sram_suspend == NULL) {
676 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
680 arm_pm_idle = omap1_pm_idle;
682 if (cpu_is_omap7xx())
683 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
684 else if (cpu_is_omap16xx())
685 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
687 /* Program new power ramp-up time
688 * (0 for most boards since we don't lower voltage when in deep sleep)
690 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
692 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
693 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
695 /* Configure IDLECT3 */
696 if (cpu_is_omap7xx())
697 omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
698 else if (cpu_is_omap16xx())
699 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
701 suspend_set_ops(&omap_pm_ops);
703 #ifdef CONFIG_DEBUG_FS
704 omap_pm_init_debugfs();
707 #ifdef CONFIG_OMAP_32K_TIMER
708 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
710 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
713 if (cpu_is_omap16xx()) {
714 /* configure LOW_PWR pin */
715 omap_cfg_reg(T20_1610_LOW_PWR);
720 __initcall(omap_pm_init);