4 * Copyright (C) 2005-2012 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
10 * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
19 #include <linux/clk.h>
20 #include <linux/clk-private.h>
21 #include <linux/list.h>
26 #include "clock2xxx.h"
30 #include "prm-regbits-24xx.h"
31 #include "cm-regbits-24xx.h"
35 #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
40 * NOTE:In many cases here we are assigning a 'default' parent. In
41 * many cases the parent is selectable. The set parent calls will
42 * also switch sources.
44 * Several sources are given initial rates which may be wrong, this will
45 * be fixed up in the init func.
47 * Things are broadly separated below by clock domains. It is
48 * noteworthy that most peripherals have dependencies on multiple clock
49 * domains. Many get their interface clocks from the L4 domain, but get
50 * functional clocks from fixed sources or other core domain derived
54 DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
56 DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
58 DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
60 static struct clk osc_ck;
62 static const struct clk_ops osc_ck_ops = {
63 .recalc_rate = &omap2_osc_clk_recalc,
66 static struct clk_hw_omap osc_ck_hw = {
72 static struct clk osc_ck = {
79 DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
81 static struct clk sys_ck;
83 static const char *sys_ck_parent_names[] = {
87 static const struct clk_ops sys_ck_ops = {
88 .init = &omap2_init_clk_clkdm,
89 .recalc_rate = &omap2xxx_sys_clk_recalc,
92 DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
93 DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
95 static struct dpll_data dpll_dd = {
96 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
97 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
98 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
99 .clk_bypass = &sys_ck,
101 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
102 .enable_mask = OMAP24XX_EN_DPLL_MASK,
103 .max_multiplier = 1023,
108 static struct clk dpll_ck;
110 static const char *dpll_ck_parent_names[] = {
114 static const struct clk_ops dpll_ck_ops = {
115 .init = &omap2_init_clk_clkdm,
116 .get_parent = &omap2_init_dpll_parent,
117 .recalc_rate = &omap2_dpllcore_recalc,
118 .round_rate = &omap2_dpll_round_rate,
119 .set_rate = &omap2_reprogram_dpllcore,
122 static struct clk_hw_omap dpll_ck_hw = {
126 .ops = &clkhwops_omap2xxx_dpll,
127 .dpll_data = &dpll_dd,
128 .clkdm_name = "wkup_clkdm",
131 DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
133 static struct clk core_ck;
135 static const char *core_ck_parent_names[] = {
139 static const struct clk_ops core_ck_ops = {
140 .init = &omap2_init_clk_clkdm,
143 DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
144 DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
146 DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
147 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
148 OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
149 CLK_DIVIDER_ONE_BASED, NULL);
151 DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
152 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
153 OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
154 CLK_DIVIDER_ONE_BASED, NULL);
156 static struct clk aes_ick;
158 static const char *aes_ick_parent_names[] = {
162 static const struct clk_ops aes_ick_ops = {
163 .init = &omap2_init_clk_clkdm,
164 .enable = &omap2_dflt_clk_enable,
165 .disable = &omap2_dflt_clk_disable,
166 .is_enabled = &omap2_dflt_clk_is_enabled,
169 static struct clk_hw_omap aes_ick_hw = {
173 .ops = &clkhwops_iclk_wait,
174 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
175 .enable_bit = OMAP24XX_EN_AES_SHIFT,
176 .clkdm_name = "core_l4_clkdm",
179 DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
181 static struct clk apll54_ck;
183 static const struct clk_ops apll54_ck_ops = {
184 .init = &omap2_init_clk_clkdm,
185 .enable = &omap2_clk_apll54_enable,
186 .disable = &omap2_clk_apll54_disable,
187 .recalc_rate = &omap2_clk_apll54_recalc,
190 static struct clk_hw_omap apll54_ck_hw = {
194 .ops = &clkhwops_apll54,
195 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
196 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
197 .flags = ENABLE_ON_INIT,
198 .clkdm_name = "wkup_clkdm",
201 DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
203 static struct clk apll96_ck;
205 static const struct clk_ops apll96_ck_ops = {
206 .init = &omap2_init_clk_clkdm,
207 .enable = &omap2_clk_apll96_enable,
208 .disable = &omap2_clk_apll96_disable,
209 .recalc_rate = &omap2_clk_apll96_recalc,
212 static struct clk_hw_omap apll96_ck_hw = {
216 .ops = &clkhwops_apll96,
217 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
218 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
219 .flags = ENABLE_ON_INIT,
220 .clkdm_name = "wkup_clkdm",
223 DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
225 static struct clk func_96m_ck;
227 static const char *func_96m_ck_parent_names[] = {
231 DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm");
232 DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops);
234 static struct clk cam_fck;
236 static const char *cam_fck_parent_names[] = {
240 static struct clk_hw_omap cam_fck_hw = {
244 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
245 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
246 .clkdm_name = "core_l3_clkdm",
249 DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
251 static struct clk cam_ick;
253 static struct clk_hw_omap cam_ick_hw = {
257 .ops = &clkhwops_iclk,
258 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
259 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
260 .clkdm_name = "core_l4_clkdm",
263 DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
265 static struct clk des_ick;
267 static struct clk_hw_omap des_ick_hw = {
271 .ops = &clkhwops_iclk_wait,
272 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
273 .enable_bit = OMAP24XX_EN_DES_SHIFT,
274 .clkdm_name = "core_l4_clkdm",
277 DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
279 static const struct clksel_rate dsp_fck_core_rates[] = {
280 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
281 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
282 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
283 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
284 { .div = 6, .val = 6, .flags = RATE_IN_242X },
285 { .div = 8, .val = 8, .flags = RATE_IN_242X },
286 { .div = 12, .val = 12, .flags = RATE_IN_242X },
290 static const struct clksel dsp_fck_clksel[] = {
291 { .parent = &core_ck, .rates = dsp_fck_core_rates },
295 static const char *dsp_fck_parent_names[] = {
299 static const struct clk_ops dsp_fck_ops = {
300 .init = &omap2_init_clk_clkdm,
301 .enable = &omap2_dflt_clk_enable,
302 .disable = &omap2_dflt_clk_disable,
303 .is_enabled = &omap2_dflt_clk_is_enabled,
304 .recalc_rate = &omap2_clksel_recalc,
305 .set_rate = &omap2_clksel_set_rate,
306 .round_rate = &omap2_clksel_round_rate,
309 DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
310 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
311 OMAP24XX_CLKSEL_DSP_MASK,
312 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
313 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
314 dsp_fck_parent_names, dsp_fck_ops);
316 static const struct clksel dsp_ick_clksel[] = {
317 { .parent = &dsp_fck, .rates = dsp_ick_rates },
321 static const char *dsp_ick_parent_names[] = {
325 DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel,
326 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
327 OMAP24XX_CLKSEL_DSP_IF_MASK,
328 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
329 OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait,
330 dsp_ick_parent_names, dsp_fck_ops);
332 static const struct clksel_rate dss1_fck_sys_rates[] = {
333 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
337 static const struct clksel_rate dss1_fck_core_rates[] = {
338 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
339 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
340 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
341 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
342 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
343 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
344 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
345 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
346 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
347 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
351 static const struct clksel dss1_fck_clksel[] = {
352 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
353 { .parent = &core_ck, .rates = dss1_fck_core_rates },
357 static const char *dss1_fck_parent_names[] = {
361 static struct clk dss1_fck;
363 static const struct clk_ops dss1_fck_ops = {
364 .init = &omap2_init_clk_clkdm,
365 .enable = &omap2_dflt_clk_enable,
366 .disable = &omap2_dflt_clk_disable,
367 .is_enabled = &omap2_dflt_clk_is_enabled,
368 .recalc_rate = &omap2_clksel_recalc,
369 .get_parent = &omap2_clksel_find_parent_index,
370 .set_parent = &omap2_clksel_set_parent,
373 DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
374 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
375 OMAP24XX_CLKSEL_DSS1_MASK,
376 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
377 OMAP24XX_EN_DSS1_SHIFT, NULL,
378 dss1_fck_parent_names, dss1_fck_ops);
380 static const struct clksel_rate dss2_fck_sys_rates[] = {
381 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
385 static const struct clksel_rate dss2_fck_48m_rates[] = {
386 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
390 static const struct clksel_rate func_48m_apll96_rates[] = {
391 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
395 static const struct clksel_rate func_48m_alt_rates[] = {
396 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
400 static const struct clksel func_48m_clksel[] = {
401 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
402 { .parent = &alt_ck, .rates = func_48m_alt_rates },
406 static const char *func_48m_ck_parent_names[] = {
407 "apll96_ck", "alt_ck",
410 static struct clk func_48m_ck;
412 static const struct clk_ops func_48m_ck_ops = {
413 .init = &omap2_init_clk_clkdm,
414 .recalc_rate = &omap2_clksel_recalc,
415 .set_rate = &omap2_clksel_set_rate,
416 .round_rate = &omap2_clksel_round_rate,
417 .get_parent = &omap2_clksel_find_parent_index,
418 .set_parent = &omap2_clksel_set_parent,
421 static struct clk_hw_omap func_48m_ck_hw = {
425 .clksel = func_48m_clksel,
426 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
427 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
428 .clkdm_name = "wkup_clkdm",
431 DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
433 static const struct clksel dss2_fck_clksel[] = {
434 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
435 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
439 static const char *dss2_fck_parent_names[] = {
440 "sys_ck", "func_48m_ck",
443 DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
444 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
445 OMAP24XX_CLKSEL_DSS2_MASK,
446 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
447 OMAP24XX_EN_DSS2_SHIFT, NULL,
448 dss2_fck_parent_names, dss1_fck_ops);
450 static const char *func_54m_ck_parent_names[] = {
451 "apll54_ck", "alt_ck",
454 DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
455 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
456 OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH,
459 static struct clk dss_54m_fck;
461 static const char *dss_54m_fck_parent_names[] = {
465 static struct clk_hw_omap dss_54m_fck_hw = {
469 .ops = &clkhwops_wait,
470 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
471 .enable_bit = OMAP24XX_EN_TV_SHIFT,
472 .clkdm_name = "dss_clkdm",
475 DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
477 static struct clk dss_ick;
479 static struct clk_hw_omap dss_ick_hw = {
483 .ops = &clkhwops_iclk,
484 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
485 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
486 .clkdm_name = "dss_clkdm",
489 DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
491 static struct clk eac_fck;
493 static struct clk_hw_omap eac_fck_hw = {
497 .ops = &clkhwops_wait,
498 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
499 .enable_bit = OMAP2420_EN_EAC_SHIFT,
500 .clkdm_name = "core_l4_clkdm",
503 DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops);
505 static struct clk eac_ick;
507 static struct clk_hw_omap eac_ick_hw = {
511 .ops = &clkhwops_iclk_wait,
512 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
513 .enable_bit = OMAP2420_EN_EAC_SHIFT,
514 .clkdm_name = "core_l4_clkdm",
517 DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops);
519 static struct clk emul_ck;
521 static struct clk_hw_omap emul_ck_hw = {
525 .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
526 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
527 .clkdm_name = "wkup_clkdm",
530 DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
532 DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
534 static struct clk fac_fck;
536 static const char *fac_fck_parent_names[] = {
540 static struct clk_hw_omap fac_fck_hw = {
544 .ops = &clkhwops_wait,
545 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
546 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
547 .clkdm_name = "core_l4_clkdm",
550 DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
552 static struct clk fac_ick;
554 static struct clk_hw_omap fac_ick_hw = {
558 .ops = &clkhwops_iclk_wait,
559 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
560 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
561 .clkdm_name = "core_l4_clkdm",
564 DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
566 static const struct clksel gfx_fck_clksel[] = {
567 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
571 static const char *gfx_2d_fck_parent_names[] = {
575 DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
576 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
577 OMAP_CLKSEL_GFX_MASK,
578 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
579 OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
580 gfx_2d_fck_parent_names, dsp_fck_ops);
582 DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
583 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
584 OMAP_CLKSEL_GFX_MASK,
585 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
586 OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
587 gfx_2d_fck_parent_names, dsp_fck_ops);
589 static struct clk gfx_ick;
591 static const char *gfx_ick_parent_names[] = {
595 static struct clk_hw_omap gfx_ick_hw = {
599 .ops = &clkhwops_wait,
600 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
601 .enable_bit = OMAP_EN_GFX_SHIFT,
602 .clkdm_name = "gfx_clkdm",
605 DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
607 static struct clk gpios_fck;
609 static const char *gpios_fck_parent_names[] = {
613 static struct clk_hw_omap gpios_fck_hw = {
617 .ops = &clkhwops_wait,
618 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
619 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
620 .clkdm_name = "wkup_clkdm",
623 DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
625 static struct clk wu_l4_ick;
627 DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
628 DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
630 static struct clk gpios_ick;
632 static const char *gpios_ick_parent_names[] = {
636 static struct clk_hw_omap gpios_ick_hw = {
640 .ops = &clkhwops_iclk_wait,
641 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
642 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
643 .clkdm_name = "wkup_clkdm",
646 DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
648 static struct clk gpmc_fck;
650 static struct clk_hw_omap gpmc_fck_hw = {
654 .ops = &clkhwops_iclk,
655 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
656 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
657 .flags = ENABLE_ON_INIT,
658 .clkdm_name = "core_l3_clkdm",
661 DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
663 static const struct clksel_rate gpt_alt_rates[] = {
664 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
668 static const struct clksel omap24xx_gpt_clksel[] = {
669 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
670 { .parent = &sys_ck, .rates = gpt_sys_rates },
671 { .parent = &alt_ck, .rates = gpt_alt_rates },
675 static const char *gpt10_fck_parent_names[] = {
676 "func_32k_ck", "sys_ck", "alt_ck",
679 DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
680 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
681 OMAP24XX_CLKSEL_GPT10_MASK,
682 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
683 OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
684 gpt10_fck_parent_names, dss1_fck_ops);
686 static struct clk gpt10_ick;
688 static struct clk_hw_omap gpt10_ick_hw = {
692 .ops = &clkhwops_iclk_wait,
693 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
694 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
695 .clkdm_name = "core_l4_clkdm",
698 DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
700 DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
701 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
702 OMAP24XX_CLKSEL_GPT11_MASK,
703 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
704 OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
705 gpt10_fck_parent_names, dss1_fck_ops);
707 static struct clk gpt11_ick;
709 static struct clk_hw_omap gpt11_ick_hw = {
713 .ops = &clkhwops_iclk_wait,
714 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
715 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
716 .clkdm_name = "core_l4_clkdm",
719 DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
721 DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
722 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
723 OMAP24XX_CLKSEL_GPT12_MASK,
724 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
725 OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
726 gpt10_fck_parent_names, dss1_fck_ops);
728 static struct clk gpt12_ick;
730 static struct clk_hw_omap gpt12_ick_hw = {
734 .ops = &clkhwops_iclk_wait,
735 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
736 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
737 .clkdm_name = "core_l4_clkdm",
740 DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
742 static const struct clk_ops gpt1_fck_ops = {
743 .init = &omap2_init_clk_clkdm,
744 .enable = &omap2_dflt_clk_enable,
745 .disable = &omap2_dflt_clk_disable,
746 .is_enabled = &omap2_dflt_clk_is_enabled,
747 .recalc_rate = &omap2_clksel_recalc,
748 .set_rate = &omap2_clksel_set_rate,
749 .round_rate = &omap2_clksel_round_rate,
750 .get_parent = &omap2_clksel_find_parent_index,
751 .set_parent = &omap2_clksel_set_parent,
754 DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
755 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
756 OMAP24XX_CLKSEL_GPT1_MASK,
757 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
758 OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
759 gpt10_fck_parent_names, gpt1_fck_ops);
761 static struct clk gpt1_ick;
763 static struct clk_hw_omap gpt1_ick_hw = {
767 .ops = &clkhwops_iclk_wait,
768 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
769 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
770 .clkdm_name = "wkup_clkdm",
773 DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
775 DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
776 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
777 OMAP24XX_CLKSEL_GPT2_MASK,
778 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
779 OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
780 gpt10_fck_parent_names, dss1_fck_ops);
782 static struct clk gpt2_ick;
784 static struct clk_hw_omap gpt2_ick_hw = {
788 .ops = &clkhwops_iclk_wait,
789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
790 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
791 .clkdm_name = "core_l4_clkdm",
794 DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
796 DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
797 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
798 OMAP24XX_CLKSEL_GPT3_MASK,
799 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
800 OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
801 gpt10_fck_parent_names, dss1_fck_ops);
803 static struct clk gpt3_ick;
805 static struct clk_hw_omap gpt3_ick_hw = {
809 .ops = &clkhwops_iclk_wait,
810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
811 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
812 .clkdm_name = "core_l4_clkdm",
815 DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
817 DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
818 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
819 OMAP24XX_CLKSEL_GPT4_MASK,
820 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
821 OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
822 gpt10_fck_parent_names, dss1_fck_ops);
824 static struct clk gpt4_ick;
826 static struct clk_hw_omap gpt4_ick_hw = {
830 .ops = &clkhwops_iclk_wait,
831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
832 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
833 .clkdm_name = "core_l4_clkdm",
836 DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
838 DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
839 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
840 OMAP24XX_CLKSEL_GPT5_MASK,
841 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
842 OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
843 gpt10_fck_parent_names, dss1_fck_ops);
845 static struct clk gpt5_ick;
847 static struct clk_hw_omap gpt5_ick_hw = {
851 .ops = &clkhwops_iclk_wait,
852 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
853 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
854 .clkdm_name = "core_l4_clkdm",
857 DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
859 DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
860 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
861 OMAP24XX_CLKSEL_GPT6_MASK,
862 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
863 OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
864 gpt10_fck_parent_names, dss1_fck_ops);
866 static struct clk gpt6_ick;
868 static struct clk_hw_omap gpt6_ick_hw = {
872 .ops = &clkhwops_iclk_wait,
873 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
874 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
875 .clkdm_name = "core_l4_clkdm",
878 DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
880 DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
881 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
882 OMAP24XX_CLKSEL_GPT7_MASK,
883 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
884 OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
885 gpt10_fck_parent_names, dss1_fck_ops);
887 static struct clk gpt7_ick;
889 static struct clk_hw_omap gpt7_ick_hw = {
893 .ops = &clkhwops_iclk_wait,
894 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
895 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
896 .clkdm_name = "core_l4_clkdm",
899 DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
901 DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
902 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
903 OMAP24XX_CLKSEL_GPT8_MASK,
904 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
905 OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
906 gpt10_fck_parent_names, dss1_fck_ops);
908 static struct clk gpt8_ick;
910 static struct clk_hw_omap gpt8_ick_hw = {
914 .ops = &clkhwops_iclk_wait,
915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
916 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
917 .clkdm_name = "core_l4_clkdm",
920 DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
922 DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
923 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
924 OMAP24XX_CLKSEL_GPT9_MASK,
925 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
926 OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
927 gpt10_fck_parent_names, dss1_fck_ops);
929 static struct clk gpt9_ick;
931 static struct clk_hw_omap gpt9_ick_hw = {
935 .ops = &clkhwops_iclk_wait,
936 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
937 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
938 .clkdm_name = "core_l4_clkdm",
941 DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
943 static struct clk hdq_fck;
945 static struct clk_hw_omap hdq_fck_hw = {
949 .ops = &clkhwops_wait,
950 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
951 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
952 .clkdm_name = "core_l4_clkdm",
955 DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
957 static struct clk hdq_ick;
959 static struct clk_hw_omap hdq_ick_hw = {
963 .ops = &clkhwops_iclk_wait,
964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
965 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
966 .clkdm_name = "core_l4_clkdm",
969 DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
971 static struct clk i2c1_fck;
973 static struct clk_hw_omap i2c1_fck_hw = {
977 .ops = &clkhwops_wait,
978 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
979 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
980 .clkdm_name = "core_l4_clkdm",
983 DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops);
985 static struct clk i2c1_ick;
987 static struct clk_hw_omap i2c1_ick_hw = {
991 .ops = &clkhwops_iclk_wait,
992 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
993 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
994 .clkdm_name = "core_l4_clkdm",
997 DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
999 static struct clk i2c2_fck;
1001 static struct clk_hw_omap i2c2_fck_hw = {
1005 .ops = &clkhwops_wait,
1006 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1007 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1008 .clkdm_name = "core_l4_clkdm",
1011 DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops);
1013 static struct clk i2c2_ick;
1015 static struct clk_hw_omap i2c2_ick_hw = {
1019 .ops = &clkhwops_iclk_wait,
1020 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1021 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1022 .clkdm_name = "core_l4_clkdm",
1025 DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
1027 DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel,
1028 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1029 OMAP2420_CLKSEL_IVA_MASK,
1030 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1031 OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait,
1032 dsp_fck_parent_names, dsp_fck_ops);
1034 static struct clk iva1_mpu_int_ifck;
1036 static const char *iva1_mpu_int_ifck_parent_names[] = {
1040 static const struct clk_ops iva1_mpu_int_ifck_ops = {
1041 .init = &omap2_init_clk_clkdm,
1042 .enable = &omap2_dflt_clk_enable,
1043 .disable = &omap2_dflt_clk_disable,
1044 .is_enabled = &omap2_dflt_clk_is_enabled,
1045 .recalc_rate = &omap_fixed_divisor_recalc,
1048 static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
1050 .clk = &iva1_mpu_int_ifck,
1052 .ops = &clkhwops_wait,
1053 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1054 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1055 .clkdm_name = "iva1_clkdm",
1059 DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names,
1060 iva1_mpu_int_ifck_ops);
1062 static struct clk mailboxes_ick;
1064 static struct clk_hw_omap mailboxes_ick_hw = {
1066 .clk = &mailboxes_ick,
1068 .ops = &clkhwops_iclk_wait,
1069 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1070 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1071 .clkdm_name = "core_l4_clkdm",
1074 DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
1076 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1077 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1081 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1082 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1086 static const struct clksel mcbsp_fck_clksel[] = {
1087 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1088 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1092 static const char *mcbsp1_fck_parent_names[] = {
1093 "func_96m_ck", "mcbsp_clks",
1096 DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1097 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1098 OMAP2_MCBSP1_CLKS_MASK,
1099 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1100 OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
1101 mcbsp1_fck_parent_names, dss1_fck_ops);
1103 static struct clk mcbsp1_ick;
1105 static struct clk_hw_omap mcbsp1_ick_hw = {
1109 .ops = &clkhwops_iclk_wait,
1110 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1111 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1112 .clkdm_name = "core_l4_clkdm",
1115 DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
1117 DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1118 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1119 OMAP2_MCBSP2_CLKS_MASK,
1120 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1121 OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
1122 mcbsp1_fck_parent_names, dss1_fck_ops);
1124 static struct clk mcbsp2_ick;
1126 static struct clk_hw_omap mcbsp2_ick_hw = {
1130 .ops = &clkhwops_iclk_wait,
1131 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1132 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1133 .clkdm_name = "core_l4_clkdm",
1136 DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
1138 static struct clk mcspi1_fck;
1140 static const char *mcspi1_fck_parent_names[] = {
1144 static struct clk_hw_omap mcspi1_fck_hw = {
1148 .ops = &clkhwops_wait,
1149 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1150 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1151 .clkdm_name = "core_l4_clkdm",
1154 DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1156 static struct clk mcspi1_ick;
1158 static struct clk_hw_omap mcspi1_ick_hw = {
1162 .ops = &clkhwops_iclk_wait,
1163 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1164 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1165 .clkdm_name = "core_l4_clkdm",
1168 DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
1170 static struct clk mcspi2_fck;
1172 static struct clk_hw_omap mcspi2_fck_hw = {
1176 .ops = &clkhwops_wait,
1177 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1178 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1179 .clkdm_name = "core_l4_clkdm",
1182 DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1184 static struct clk mcspi2_ick;
1186 static struct clk_hw_omap mcspi2_ick_hw = {
1190 .ops = &clkhwops_iclk_wait,
1191 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1192 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1193 .clkdm_name = "core_l4_clkdm",
1196 DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
1198 static struct clk mmc_fck;
1200 static struct clk_hw_omap mmc_fck_hw = {
1204 .ops = &clkhwops_wait,
1205 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1206 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1207 .clkdm_name = "core_l4_clkdm",
1210 DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops);
1212 static struct clk mmc_ick;
1214 static struct clk_hw_omap mmc_ick_hw = {
1218 .ops = &clkhwops_iclk_wait,
1219 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1220 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1221 .clkdm_name = "core_l4_clkdm",
1224 DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops);
1226 DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
1227 OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1228 OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
1229 CLK_DIVIDER_ONE_BASED, NULL);
1231 static struct clk mpu_wdt_fck;
1233 static struct clk_hw_omap mpu_wdt_fck_hw = {
1235 .clk = &mpu_wdt_fck,
1237 .ops = &clkhwops_wait,
1238 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1239 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1240 .clkdm_name = "wkup_clkdm",
1243 DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops);
1245 static struct clk mpu_wdt_ick;
1247 static struct clk_hw_omap mpu_wdt_ick_hw = {
1249 .clk = &mpu_wdt_ick,
1251 .ops = &clkhwops_iclk_wait,
1252 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1253 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1254 .clkdm_name = "wkup_clkdm",
1257 DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
1259 static struct clk mspro_fck;
1261 static struct clk_hw_omap mspro_fck_hw = {
1265 .ops = &clkhwops_wait,
1266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1267 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1268 .clkdm_name = "core_l4_clkdm",
1271 DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
1273 static struct clk mspro_ick;
1275 static struct clk_hw_omap mspro_ick_hw = {
1279 .ops = &clkhwops_iclk_wait,
1280 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1281 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1282 .clkdm_name = "core_l4_clkdm",
1285 DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
1287 static struct clk omapctrl_ick;
1289 static struct clk_hw_omap omapctrl_ick_hw = {
1291 .clk = &omapctrl_ick,
1293 .ops = &clkhwops_iclk_wait,
1294 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1295 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1296 .flags = ENABLE_ON_INIT,
1297 .clkdm_name = "wkup_clkdm",
1300 DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
1302 static struct clk pka_ick;
1304 static struct clk_hw_omap pka_ick_hw = {
1308 .ops = &clkhwops_iclk_wait,
1309 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1310 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1311 .clkdm_name = "core_l4_clkdm",
1314 DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
1316 static struct clk rng_ick;
1318 static struct clk_hw_omap rng_ick_hw = {
1322 .ops = &clkhwops_iclk_wait,
1323 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1324 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1325 .clkdm_name = "core_l4_clkdm",
1328 DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
1330 static struct clk sdma_fck;
1332 DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
1333 DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
1335 static struct clk sdma_ick;
1337 static struct clk_hw_omap sdma_ick_hw = {
1341 .ops = &clkhwops_iclk,
1342 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1343 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1344 .clkdm_name = "core_l3_clkdm",
1347 DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
1349 static struct clk sdrc_ick;
1351 static struct clk_hw_omap sdrc_ick_hw = {
1355 .ops = &clkhwops_iclk,
1356 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1357 .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
1358 .flags = ENABLE_ON_INIT,
1359 .clkdm_name = "core_l3_clkdm",
1362 DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
1364 static struct clk sha_ick;
1366 static struct clk_hw_omap sha_ick_hw = {
1370 .ops = &clkhwops_iclk_wait,
1371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1372 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1373 .clkdm_name = "core_l4_clkdm",
1376 DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
1378 static struct clk ssi_l4_ick;
1380 static struct clk_hw_omap ssi_l4_ick_hw = {
1384 .ops = &clkhwops_iclk_wait,
1385 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1386 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1387 .clkdm_name = "core_l4_clkdm",
1390 DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
1392 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1393 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1394 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1395 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1396 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1397 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1398 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1402 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1403 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1407 static const char *ssi_ssr_sst_fck_parent_names[] = {
1411 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
1412 ssi_ssr_sst_fck_clksel,
1413 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1414 OMAP24XX_CLKSEL_SSI_MASK,
1415 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1416 OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
1417 ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
1419 static struct clk sync_32k_ick;
1421 static struct clk_hw_omap sync_32k_ick_hw = {
1423 .clk = &sync_32k_ick,
1425 .ops = &clkhwops_iclk_wait,
1426 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1427 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1428 .flags = ENABLE_ON_INIT,
1429 .clkdm_name = "wkup_clkdm",
1432 DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
1434 static const struct clksel_rate common_clkout_src_core_rates[] = {
1435 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1439 static const struct clksel_rate common_clkout_src_sys_rates[] = {
1440 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1444 static const struct clksel_rate common_clkout_src_96m_rates[] = {
1445 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
1449 static const struct clksel_rate common_clkout_src_54m_rates[] = {
1450 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
1454 static const struct clksel common_clkout_src_clksel[] = {
1455 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
1456 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
1457 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
1458 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
1462 static const char *sys_clkout_src_parent_names[] = {
1463 "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
1466 DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
1467 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
1468 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
1469 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1471 DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
1472 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
1473 OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1475 DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm",
1476 common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL,
1477 OMAP2420_CLKOUT2_SOURCE_MASK,
1478 OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT,
1479 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1481 DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0,
1482 OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT,
1483 OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1485 static struct clk uart1_fck;
1487 static struct clk_hw_omap uart1_fck_hw = {
1491 .ops = &clkhwops_wait,
1492 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1493 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1494 .clkdm_name = "core_l4_clkdm",
1497 DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1499 static struct clk uart1_ick;
1501 static struct clk_hw_omap uart1_ick_hw = {
1505 .ops = &clkhwops_iclk_wait,
1506 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1507 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1508 .clkdm_name = "core_l4_clkdm",
1511 DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
1513 static struct clk uart2_fck;
1515 static struct clk_hw_omap uart2_fck_hw = {
1519 .ops = &clkhwops_wait,
1520 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1521 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1522 .clkdm_name = "core_l4_clkdm",
1525 DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1527 static struct clk uart2_ick;
1529 static struct clk_hw_omap uart2_ick_hw = {
1533 .ops = &clkhwops_iclk_wait,
1534 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1535 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1536 .clkdm_name = "core_l4_clkdm",
1539 DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
1541 static struct clk uart3_fck;
1543 static struct clk_hw_omap uart3_fck_hw = {
1547 .ops = &clkhwops_wait,
1548 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1549 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1550 .clkdm_name = "core_l4_clkdm",
1553 DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
1555 static struct clk uart3_ick;
1557 static struct clk_hw_omap uart3_ick_hw = {
1561 .ops = &clkhwops_iclk_wait,
1562 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1563 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1564 .clkdm_name = "core_l4_clkdm",
1567 DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
1569 static struct clk usb_fck;
1571 static struct clk_hw_omap usb_fck_hw = {
1575 .ops = &clkhwops_wait,
1576 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1577 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1578 .clkdm_name = "core_l3_clkdm",
1581 DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
1583 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1584 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1585 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1586 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1590 static const struct clksel usb_l4_ick_clksel[] = {
1591 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1595 static const char *usb_l4_ick_parent_names[] = {
1599 DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
1600 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1601 OMAP24XX_CLKSEL_USB_MASK,
1602 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1603 OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
1604 usb_l4_ick_parent_names, dsp_fck_ops);
1606 static struct clk virt_prcm_set;
1608 static const char *virt_prcm_set_parent_names[] = {
1612 static const struct clk_ops virt_prcm_set_ops = {
1613 .recalc_rate = &omap2_table_mpu_recalc,
1614 .set_rate = &omap2_select_table_rate,
1615 .round_rate = &omap2_round_to_table_rate,
1618 DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
1619 DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
1621 static const struct clksel_rate vlynq_fck_96m_rates[] = {
1622 { .div = 1, .val = 0, .flags = RATE_IN_242X },
1626 static const struct clksel_rate vlynq_fck_core_rates[] = {
1627 { .div = 1, .val = 1, .flags = RATE_IN_242X },
1628 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1629 { .div = 3, .val = 3, .flags = RATE_IN_242X },
1630 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1631 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1632 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1633 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1634 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1635 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1636 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1640 static const struct clksel vlynq_fck_clksel[] = {
1641 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1642 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
1646 static const char *vlynq_fck_parent_names[] = {
1647 "func_96m_ck", "core_ck",
1650 DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel,
1651 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1652 OMAP2420_CLKSEL_VLYNQ_MASK,
1653 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1654 OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait,
1655 vlynq_fck_parent_names, dss1_fck_ops);
1657 static struct clk vlynq_ick;
1659 static struct clk_hw_omap vlynq_ick_hw = {
1663 .ops = &clkhwops_iclk_wait,
1664 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1665 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1666 .clkdm_name = "core_l3_clkdm",
1669 DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops);
1671 static struct clk wdt1_ick;
1673 static struct clk_hw_omap wdt1_ick_hw = {
1677 .ops = &clkhwops_iclk_wait,
1678 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1679 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1680 .clkdm_name = "wkup_clkdm",
1683 DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
1685 static struct clk wdt1_osc_ck;
1687 static const struct clk_ops wdt1_osc_ck_ops = {};
1689 DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
1690 DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
1692 static struct clk wdt3_fck;
1694 static struct clk_hw_omap wdt3_fck_hw = {
1698 .ops = &clkhwops_wait,
1699 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1700 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1701 .clkdm_name = "core_l4_clkdm",
1704 DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops);
1706 static struct clk wdt3_ick;
1708 static struct clk_hw_omap wdt3_ick_hw = {
1712 .ops = &clkhwops_iclk_wait,
1713 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1714 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1715 .clkdm_name = "core_l4_clkdm",
1718 DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops);
1720 static struct clk wdt4_fck;
1722 static struct clk_hw_omap wdt4_fck_hw = {
1726 .ops = &clkhwops_wait,
1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1728 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1729 .clkdm_name = "core_l4_clkdm",
1732 DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops);
1734 static struct clk wdt4_ick;
1736 static struct clk_hw_omap wdt4_ick_hw = {
1740 .ops = &clkhwops_iclk_wait,
1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1743 .clkdm_name = "core_l4_clkdm",
1746 DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
1749 * clkdev integration
1752 static struct omap_clk omap2420_clks[] = {
1753 /* external root sources */
1754 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
1755 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
1756 CLK(NULL, "osc_ck", &osc_ck, CK_242X),
1757 CLK(NULL, "sys_ck", &sys_ck, CK_242X),
1758 CLK(NULL, "alt_ck", &alt_ck, CK_242X),
1759 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
1760 /* internal analog sources */
1761 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
1762 CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
1763 CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
1764 /* internal prcm root sources */
1765 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
1766 CLK(NULL, "core_ck", &core_ck, CK_242X),
1767 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
1768 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
1769 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
1770 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
1771 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
1772 CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
1773 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
1774 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
1775 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
1776 /* mpu domain clocks */
1777 CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
1778 /* dsp domain clocks */
1779 CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
1780 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
1781 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
1782 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
1783 /* GFX domain clocks */
1784 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
1785 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
1786 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
1787 /* DSS domain clocks */
1788 CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
1789 CLK(NULL, "dss_ick", &dss_ick, CK_242X),
1790 CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
1791 CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
1792 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
1793 /* L3 domain clocks */
1794 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
1795 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
1796 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
1797 /* L4 domain clocks */
1798 CLK(NULL, "l4_ck", &l4_ck, CK_242X),
1799 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
1800 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
1801 /* virtual meta-group clock */
1802 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
1803 /* general l4 interface ck, multi-parent functional clk */
1804 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
1805 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
1806 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
1807 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
1808 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
1809 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
1810 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
1811 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
1812 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
1813 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
1814 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
1815 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
1816 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
1817 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
1818 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
1819 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
1820 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
1821 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
1822 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
1823 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
1824 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
1825 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
1826 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
1827 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
1828 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
1829 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X),
1830 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
1831 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
1832 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X),
1833 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
1834 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
1835 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X),
1836 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
1837 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
1838 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X),
1839 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
1840 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
1841 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
1842 CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
1843 CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
1844 CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
1845 CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
1846 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
1847 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
1848 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
1849 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X),
1850 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
1851 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
1852 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
1853 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
1854 CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
1855 CLK(NULL, "cam_fck", &cam_fck, CK_242X),
1856 CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
1857 CLK(NULL, "cam_ick", &cam_ick, CK_242X),
1858 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
1859 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
1860 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
1861 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
1862 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
1863 CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
1864 CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
1865 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
1866 CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
1867 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
1868 CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
1869 CLK(NULL, "fac_ick", &fac_ick, CK_242X),
1870 CLK(NULL, "fac_fck", &fac_fck, CK_242X),
1871 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
1872 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
1873 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
1874 CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
1875 CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
1876 CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
1877 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
1878 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
1879 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
1880 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
1881 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
1882 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
1883 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
1884 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
1885 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
1886 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
1887 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
1888 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
1889 CLK(NULL, "des_ick", &des_ick, CK_242X),
1890 CLK("omap-sham", "ick", &sha_ick, CK_242X),
1891 CLK(NULL, "sha_ick", &sha_ick, CK_242X),
1892 CLK("omap_rng", "ick", &rng_ick, CK_242X),
1893 CLK(NULL, "rng_ick", &rng_ick, CK_242X),
1894 CLK("omap-aes", "ick", &aes_ick, CK_242X),
1895 CLK(NULL, "aes_ick", &aes_ick, CK_242X),
1896 CLK(NULL, "pka_ick", &pka_ick, CK_242X),
1897 CLK(NULL, "usb_fck", &usb_fck, CK_242X),
1898 CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
1899 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X),
1900 CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X),
1901 CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X),
1902 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X),
1906 static const char *enable_init_clks[] = {
1919 int __init omap2420_clk_init(void)
1923 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1924 cpu_mask = RATE_IN_242X;
1925 rate_table = omap2420_rate_table;
1927 omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw);
1929 omap2xxx_clkt_vps_check_bootloader_rates();
1931 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1934 if (!__clk_init(NULL, c->lk.clk))
1935 omap2_init_clk_hw_omap_clocks(c->lk.clk);
1938 omap2_clk_disable_autoidle_all();
1940 omap2_clk_enable_init_clocks(enable_init_clks,
1941 ARRAY_SIZE(enable_init_clks));
1943 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1944 (clk_get_rate(&sys_ck) / 1000000),
1945 (clk_get_rate(&sys_ck) / 100000) % 10,
1946 (clk_get_rate(&dpll_ck) / 1000000),
1947 (clk_get_rate(&mpu_ck) / 1000000));