2 * linux/arch/arm/mach-omap2/clock.h
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
19 #include <linux/kernel.h>
20 #include <linux/list.h>
22 #include <linux/clkdev.h>
23 #include <linux/clk-provider.h>
24 #include <linux/clk/ti.h>
31 #define CLK(dev, con, ck) \
42 #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
43 static struct clk _name = { \
45 .hw = &_name##_hw.hw, \
46 .parent_names = _parent_array_name, \
47 .num_parents = ARRAY_SIZE(_parent_array_name), \
48 .ops = &_clkops_name, \
51 #define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
52 _clkops_name, _flags) \
53 static struct clk _name = { \
55 .hw = &_name##_hw.hw, \
56 .parent_names = _parent_array_name, \
57 .num_parents = ARRAY_SIZE(_parent_array_name), \
58 .ops = &_clkops_name, \
62 #define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
63 static struct clk_hw_omap _name##_hw = { \
67 .clkdm_name = _clkdm_name, \
70 #define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \
71 _clksel_reg, _clksel_mask, \
72 _parent_names, _ops) \
73 static struct clk _name; \
74 static struct clk_hw_omap _name##_hw = { \
79 .clksel_reg = _clksel_reg, \
80 .clksel_mask = _clksel_mask, \
81 .clkdm_name = _clkdm_name, \
83 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
85 #define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \
86 _clksel_reg, _clksel_mask, \
87 _enable_reg, _enable_bit, \
88 _hwops, _parent_names, _ops) \
89 static struct clk _name; \
90 static struct clk_hw_omap _name##_hw = { \
95 .enable_reg = _enable_reg, \
96 .enable_bit = _enable_bit, \
98 .clksel_reg = _clksel_reg, \
99 .clksel_mask = _clksel_mask, \
100 .clkdm_name = _clkdm_name, \
102 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
104 #define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
105 _parent_ptr, _flags, \
106 _clksel_reg, _clksel_mask) \
107 static const struct clksel _name##_div[] = { \
109 .parent = _parent_ptr, \
110 .rates = div31_1to31_rates \
112 { .parent = NULL }, \
114 static struct clk _name; \
115 static const char *_name##_parent_names[] = { \
118 static struct clk_hw_omap _name##_hw = { \
122 .clksel = _name##_div, \
123 .clksel_reg = _clksel_reg, \
124 .clksel_mask = _clksel_mask, \
125 .ops = &clkhwops_omap4_dpllmx, \
127 DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
129 /* struct clksel_rate.flags possibilities */
130 #define RATE_IN_242X (1 << 0)
131 #define RATE_IN_243X (1 << 1)
132 #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
133 #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
134 #define RATE_IN_36XX (1 << 4)
135 #define RATE_IN_4430 (1 << 5)
136 #define RATE_IN_TI816X (1 << 6)
137 #define RATE_IN_4460 (1 << 7)
138 #define RATE_IN_AM33XX (1 << 8)
139 #define RATE_IN_TI814X (1 << 9)
141 #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
142 #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
143 #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
144 #define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
146 /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
147 #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
151 * struct clksel_rate - register bitfield values corresponding to clk divisors
152 * @val: register bitfield value (shifted to bit 0)
153 * @div: clock divisor corresponding to @val
154 * @flags: (see "struct clksel_rate.flags possibilities" above)
156 * @val should match the value of a read from struct clk.clksel_reg
157 * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
159 * @div is the divisor that should be applied to the parent clock's rate
160 * to produce the current clock's rate.
169 * struct clksel - available parent clocks, and a pointer to their divisors
170 * @parent: struct clk * to a possible parent clock
171 * @rates: available divisors for this parent clock
173 * A struct clksel is always associated with one or more struct clks
174 * and one or more struct clksel_rates.
178 const struct clksel_rate *rates;
181 struct clk_hw_omap_ops {
182 void (*find_idlest)(struct clk_hw_omap *oclk,
183 void __iomem **idlest_reg,
184 u8 *idlest_bit, u8 *idlest_val);
185 void (*find_companion)(struct clk_hw_omap *oclk,
186 void __iomem **other_reg,
188 void (*allow_idle)(struct clk_hw_omap *oclk);
189 void (*deny_idle)(struct clk_hw_omap *oclk);
192 unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
193 unsigned long parent_rate);
195 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
196 #define CORE_CLK_SRC_32K 0x0
197 #define CORE_CLK_SRC_DPLL 0x1
198 #define CORE_CLK_SRC_DPLL_X2 0x2
200 /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
201 #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
202 #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
203 #define OMAP2XXX_EN_DPLL_LOCKED 0x3
205 /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
206 #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
207 #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
208 #define OMAP3XXX_EN_DPLL_LOCKED 0x7
210 /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
211 #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
212 #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
213 #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
214 #define OMAP4XXX_EN_DPLL_LOCKED 0x7
216 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
217 void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
218 void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
219 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
220 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
221 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
223 void __init omap2_clk_disable_clkdm_control(void);
225 /* clkt_clksel.c public functions */
226 u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
227 unsigned long target_rate,
229 u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
230 unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
231 long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
232 unsigned long *parent_rate);
233 int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
234 unsigned long parent_rate);
235 int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
237 /* clkt_iclk.c public functions */
238 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
239 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
241 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
243 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
244 void __iomem **other_reg,
246 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
247 void __iomem **idlest_reg,
248 u8 *idlest_bit, u8 *idlest_val);
249 int omap2_clk_enable_autoidle_all(void);
250 int omap2_clk_allow_idle(struct clk *clk);
251 int omap2_clk_deny_idle(struct clk *clk);
252 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
253 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
254 const char *core_ck_name,
255 const char *mpu_ck_name);
257 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
258 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
262 extern const struct clkops clkops_omap2_dflt_wait;
263 extern const struct clkops clkops_dummy;
264 extern const struct clkops clkops_omap2_dflt;
266 extern struct clk_functions omap2_clk_functions;
268 extern const struct clksel_rate gpt_32k_rates[];
269 extern const struct clksel_rate gpt_sys_rates[];
270 extern const struct clksel_rate gfx_l3_rates[];
271 extern const struct clksel_rate dsp_ick_rates[];
272 extern struct clk dummy_ck;
274 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
275 extern const struct clk_hw_omap_ops clkhwops_wait;
276 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
277 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
278 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
279 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
280 extern const struct clk_hw_omap_ops clkhwops_apll54;
281 extern const struct clk_hw_omap_ops clkhwops_apll96;
282 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
283 extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
285 /* clksel_rate blocks shared between OMAP44xx and AM33xx */
286 extern const struct clksel_rate div_1_0_rates[];
287 extern const struct clksel_rate div3_1to4_rates[];
288 extern const struct clksel_rate div_1_1_rates[];
289 extern const struct clksel_rate div_1_2_rates[];
290 extern const struct clksel_rate div_1_3_rates[];
291 extern const struct clksel_rate div_1_4_rates[];
292 extern const struct clksel_rate div31_1to31_rates[];
294 extern void __iomem *clk_memmaps[];
296 extern int am33xx_clk_init(void);
298 extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
299 extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
301 extern void omap_clocks_register(struct omap_clk *oclks, int cnt);