4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
21 * XXX Some of the ES1 clocks have been removed/changed; once support
22 * is added for discriminating clocks by ES level, these should be added back
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/clk.h>
30 #include <plat/hardware.h>
31 #include <plat/clkdev_omap.h>
35 #include "clock44xx.h"
38 #include "cm-regbits-44xx.h"
40 #include "prm-regbits-44xx.h"
44 /* OMAP4 modulemode control */
45 #define OMAP4430_MODULEMODE_HWCTRL 0
46 #define OMAP4430_MODULEMODE_SWCTRL 1
50 static struct clk extalt_clkin_ck = {
51 .name = "extalt_clkin_ck",
56 static struct clk pad_clks_ck = {
57 .name = "pad_clks_ck",
59 .ops = &clkops_omap2_dflt,
60 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
61 .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
64 static struct clk pad_slimbus_core_clks_ck = {
65 .name = "pad_slimbus_core_clks_ck",
70 static struct clk secure_32k_clk_src_ck = {
71 .name = "secure_32k_clk_src_ck",
76 static struct clk slimbus_clk = {
77 .name = "slimbus_clk",
79 .ops = &clkops_omap2_dflt,
80 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
81 .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
84 static struct clk sys_32k_ck = {
90 static struct clk virt_12000000_ck = {
91 .name = "virt_12000000_ck",
96 static struct clk virt_13000000_ck = {
97 .name = "virt_13000000_ck",
102 static struct clk virt_16800000_ck = {
103 .name = "virt_16800000_ck",
108 static struct clk virt_19200000_ck = {
109 .name = "virt_19200000_ck",
114 static struct clk virt_26000000_ck = {
115 .name = "virt_26000000_ck",
120 static struct clk virt_27000000_ck = {
121 .name = "virt_27000000_ck",
126 static struct clk virt_38400000_ck = {
127 .name = "virt_38400000_ck",
132 static const struct clksel_rate div_1_0_rates[] = {
133 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
137 static const struct clksel_rate div_1_1_rates[] = {
138 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
142 static const struct clksel_rate div_1_2_rates[] = {
143 { .div = 1, .val = 2, .flags = RATE_IN_4430 },
147 static const struct clksel_rate div_1_3_rates[] = {
148 { .div = 1, .val = 3, .flags = RATE_IN_4430 },
152 static const struct clksel_rate div_1_4_rates[] = {
153 { .div = 1, .val = 4, .flags = RATE_IN_4430 },
157 static const struct clksel_rate div_1_5_rates[] = {
158 { .div = 1, .val = 5, .flags = RATE_IN_4430 },
162 static const struct clksel_rate div_1_6_rates[] = {
163 { .div = 1, .val = 6, .flags = RATE_IN_4430 },
167 static const struct clksel_rate div_1_7_rates[] = {
168 { .div = 1, .val = 7, .flags = RATE_IN_4430 },
172 static const struct clksel sys_clkin_sel[] = {
173 { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
174 { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
175 { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
176 { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
177 { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
178 { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
179 { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
183 static struct clk sys_clkin_ck = {
184 .name = "sys_clkin_ck",
186 .clksel = sys_clkin_sel,
187 .init = &omap2_init_clksel_parent,
188 .clksel_reg = OMAP4430_CM_SYS_CLKSEL,
189 .clksel_mask = OMAP4430_SYS_CLKSEL_MASK,
191 .recalc = &omap2_clksel_recalc,
194 static struct clk tie_low_clock_ck = {
195 .name = "tie_low_clock_ck",
200 static struct clk utmi_phy_clkout_ck = {
201 .name = "utmi_phy_clkout_ck",
206 static struct clk xclk60mhsp1_ck = {
207 .name = "xclk60mhsp1_ck",
212 static struct clk xclk60mhsp2_ck = {
213 .name = "xclk60mhsp2_ck",
218 static struct clk xclk60motg_ck = {
219 .name = "xclk60motg_ck",
224 /* Module clocks and DPLL outputs */
226 static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
227 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
228 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
232 static struct clk abe_dpll_bypass_clk_mux_ck = {
233 .name = "abe_dpll_bypass_clk_mux_ck",
234 .parent = &sys_clkin_ck,
236 .recalc = &followparent_recalc,
239 static struct clk abe_dpll_refclk_mux_ck = {
240 .name = "abe_dpll_refclk_mux_ck",
241 .parent = &sys_clkin_ck,
242 .clksel = abe_dpll_bypass_clk_mux_sel,
243 .init = &omap2_init_clksel_parent,
244 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
245 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
247 .recalc = &omap2_clksel_recalc,
251 static struct dpll_data dpll_abe_dd = {
252 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
253 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
254 .clk_ref = &abe_dpll_refclk_mux_ck,
255 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
256 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
257 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
258 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
259 .mult_mask = OMAP4430_DPLL_MULT_MASK,
260 .div1_mask = OMAP4430_DPLL_DIV_MASK,
261 .enable_mask = OMAP4430_DPLL_EN_MASK,
262 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
263 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
264 .max_multiplier = 2047,
270 static struct clk dpll_abe_ck = {
271 .name = "dpll_abe_ck",
272 .parent = &abe_dpll_refclk_mux_ck,
273 .dpll_data = &dpll_abe_dd,
274 .init = &omap2_init_dpll_parent,
275 .ops = &clkops_omap3_noncore_dpll_ops,
276 .recalc = &omap4_dpll_regm4xen_recalc,
277 .round_rate = &omap4_dpll_regm4xen_round_rate,
278 .set_rate = &omap3_noncore_dpll_set_rate,
281 static struct clk dpll_abe_x2_ck = {
282 .name = "dpll_abe_x2_ck",
283 .parent = &dpll_abe_ck,
284 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
285 .flags = CLOCK_CLKOUTX2,
286 .ops = &clkops_omap4_dpllmx_ops,
287 .recalc = &omap3_clkoutx2_recalc,
290 static const struct clksel_rate div31_1to31_rates[] = {
291 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
292 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
293 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
294 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
295 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
296 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
297 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
298 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
299 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
300 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
301 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
302 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
303 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
304 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
305 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
306 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
307 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
308 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
309 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
310 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
311 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
312 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
313 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
314 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
315 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
316 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
317 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
318 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
319 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
320 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
321 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
325 static const struct clksel dpll_abe_m2x2_div[] = {
326 { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
330 static struct clk dpll_abe_m2x2_ck = {
331 .name = "dpll_abe_m2x2_ck",
332 .parent = &dpll_abe_x2_ck,
333 .clksel = dpll_abe_m2x2_div,
334 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
335 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
336 .ops = &clkops_omap4_dpllmx_ops,
337 .recalc = &omap2_clksel_recalc,
338 .round_rate = &omap2_clksel_round_rate,
339 .set_rate = &omap2_clksel_set_rate,
342 static struct clk abe_24m_fclk = {
343 .name = "abe_24m_fclk",
344 .parent = &dpll_abe_m2x2_ck,
347 .recalc = &omap_fixed_divisor_recalc,
350 static const struct clksel_rate div3_1to4_rates[] = {
351 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
352 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
353 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
357 static const struct clksel abe_clk_div[] = {
358 { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
362 static struct clk abe_clk = {
364 .parent = &dpll_abe_m2x2_ck,
365 .clksel = abe_clk_div,
366 .clksel_reg = OMAP4430_CM_CLKSEL_ABE,
367 .clksel_mask = OMAP4430_CLKSEL_OPP_MASK,
369 .recalc = &omap2_clksel_recalc,
370 .round_rate = &omap2_clksel_round_rate,
371 .set_rate = &omap2_clksel_set_rate,
374 static const struct clksel_rate div2_1to2_rates[] = {
375 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
376 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
380 static const struct clksel aess_fclk_div[] = {
381 { .parent = &abe_clk, .rates = div2_1to2_rates },
385 static struct clk aess_fclk = {
388 .clksel = aess_fclk_div,
389 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
390 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
392 .recalc = &omap2_clksel_recalc,
393 .round_rate = &omap2_clksel_round_rate,
394 .set_rate = &omap2_clksel_set_rate,
397 static struct clk dpll_abe_m3x2_ck = {
398 .name = "dpll_abe_m3x2_ck",
399 .parent = &dpll_abe_x2_ck,
400 .clksel = dpll_abe_m2x2_div,
401 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
402 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
403 .ops = &clkops_omap4_dpllmx_ops,
404 .recalc = &omap2_clksel_recalc,
405 .round_rate = &omap2_clksel_round_rate,
406 .set_rate = &omap2_clksel_set_rate,
409 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
410 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
411 { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
415 static struct clk core_hsd_byp_clk_mux_ck = {
416 .name = "core_hsd_byp_clk_mux_ck",
417 .parent = &sys_clkin_ck,
418 .clksel = core_hsd_byp_clk_mux_sel,
419 .init = &omap2_init_clksel_parent,
420 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
421 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
423 .recalc = &omap2_clksel_recalc,
427 static struct dpll_data dpll_core_dd = {
428 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
429 .clk_bypass = &core_hsd_byp_clk_mux_ck,
430 .clk_ref = &sys_clkin_ck,
431 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
432 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
433 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
434 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
435 .mult_mask = OMAP4430_DPLL_MULT_MASK,
436 .div1_mask = OMAP4430_DPLL_DIV_MASK,
437 .enable_mask = OMAP4430_DPLL_EN_MASK,
438 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
439 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
440 .max_multiplier = 2047,
446 static struct clk dpll_core_ck = {
447 .name = "dpll_core_ck",
448 .parent = &sys_clkin_ck,
449 .dpll_data = &dpll_core_dd,
450 .init = &omap2_init_dpll_parent,
451 .ops = &clkops_omap3_core_dpll_ops,
452 .recalc = &omap3_dpll_recalc,
455 static struct clk dpll_core_x2_ck = {
456 .name = "dpll_core_x2_ck",
457 .parent = &dpll_core_ck,
458 .flags = CLOCK_CLKOUTX2,
460 .recalc = &omap3_clkoutx2_recalc,
463 static const struct clksel dpll_core_m6x2_div[] = {
464 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
468 static struct clk dpll_core_m6x2_ck = {
469 .name = "dpll_core_m6x2_ck",
470 .parent = &dpll_core_x2_ck,
471 .clksel = dpll_core_m6x2_div,
472 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
473 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
474 .ops = &clkops_omap4_dpllmx_ops,
475 .recalc = &omap2_clksel_recalc,
476 .round_rate = &omap2_clksel_round_rate,
477 .set_rate = &omap2_clksel_set_rate,
480 static const struct clksel dbgclk_mux_sel[] = {
481 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
482 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
486 static struct clk dbgclk_mux_ck = {
487 .name = "dbgclk_mux_ck",
488 .parent = &sys_clkin_ck,
490 .recalc = &followparent_recalc,
493 static const struct clksel dpll_core_m2_div[] = {
494 { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
498 static struct clk dpll_core_m2_ck = {
499 .name = "dpll_core_m2_ck",
500 .parent = &dpll_core_ck,
501 .clksel = dpll_core_m2_div,
502 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
503 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
504 .ops = &clkops_omap4_dpllmx_ops,
505 .recalc = &omap2_clksel_recalc,
506 .round_rate = &omap2_clksel_round_rate,
507 .set_rate = &omap2_clksel_set_rate,
510 static struct clk ddrphy_ck = {
512 .parent = &dpll_core_m2_ck,
515 .recalc = &omap_fixed_divisor_recalc,
518 static struct clk dpll_core_m5x2_ck = {
519 .name = "dpll_core_m5x2_ck",
520 .parent = &dpll_core_x2_ck,
521 .clksel = dpll_core_m6x2_div,
522 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
523 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
524 .ops = &clkops_omap4_dpllmx_ops,
525 .recalc = &omap2_clksel_recalc,
526 .round_rate = &omap2_clksel_round_rate,
527 .set_rate = &omap2_clksel_set_rate,
530 static const struct clksel div_core_div[] = {
531 { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
535 static struct clk div_core_ck = {
536 .name = "div_core_ck",
537 .parent = &dpll_core_m5x2_ck,
538 .clksel = div_core_div,
539 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
540 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
542 .recalc = &omap2_clksel_recalc,
543 .round_rate = &omap2_clksel_round_rate,
544 .set_rate = &omap2_clksel_set_rate,
547 static const struct clksel_rate div4_1to8_rates[] = {
548 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
549 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
550 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
551 { .div = 8, .val = 3, .flags = RATE_IN_4430 },
555 static const struct clksel div_iva_hs_clk_div[] = {
556 { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
560 static struct clk div_iva_hs_clk = {
561 .name = "div_iva_hs_clk",
562 .parent = &dpll_core_m5x2_ck,
563 .clksel = div_iva_hs_clk_div,
564 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
565 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
567 .recalc = &omap2_clksel_recalc,
568 .round_rate = &omap2_clksel_round_rate,
569 .set_rate = &omap2_clksel_set_rate,
572 static struct clk div_mpu_hs_clk = {
573 .name = "div_mpu_hs_clk",
574 .parent = &dpll_core_m5x2_ck,
575 .clksel = div_iva_hs_clk_div,
576 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
577 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
579 .recalc = &omap2_clksel_recalc,
580 .round_rate = &omap2_clksel_round_rate,
581 .set_rate = &omap2_clksel_set_rate,
584 static struct clk dpll_core_m4x2_ck = {
585 .name = "dpll_core_m4x2_ck",
586 .parent = &dpll_core_x2_ck,
587 .clksel = dpll_core_m6x2_div,
588 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
589 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
590 .ops = &clkops_omap4_dpllmx_ops,
591 .recalc = &omap2_clksel_recalc,
592 .round_rate = &omap2_clksel_round_rate,
593 .set_rate = &omap2_clksel_set_rate,
596 static struct clk dll_clk_div_ck = {
597 .name = "dll_clk_div_ck",
598 .parent = &dpll_core_m4x2_ck,
601 .recalc = &omap_fixed_divisor_recalc,
604 static const struct clksel dpll_abe_m2_div[] = {
605 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
609 static struct clk dpll_abe_m2_ck = {
610 .name = "dpll_abe_m2_ck",
611 .parent = &dpll_abe_ck,
612 .clksel = dpll_abe_m2_div,
613 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
614 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
615 .ops = &clkops_omap4_dpllmx_ops,
616 .recalc = &omap2_clksel_recalc,
617 .round_rate = &omap2_clksel_round_rate,
618 .set_rate = &omap2_clksel_set_rate,
621 static struct clk dpll_core_m3x2_ck = {
622 .name = "dpll_core_m3x2_ck",
623 .parent = &dpll_core_x2_ck,
624 .clksel = dpll_core_m6x2_div,
625 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
626 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
627 .ops = &clkops_omap2_dflt,
628 .recalc = &omap2_clksel_recalc,
629 .round_rate = &omap2_clksel_round_rate,
630 .set_rate = &omap2_clksel_set_rate,
631 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
632 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
635 static struct clk dpll_core_m7x2_ck = {
636 .name = "dpll_core_m7x2_ck",
637 .parent = &dpll_core_x2_ck,
638 .clksel = dpll_core_m6x2_div,
639 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
640 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
641 .ops = &clkops_omap4_dpllmx_ops,
642 .recalc = &omap2_clksel_recalc,
643 .round_rate = &omap2_clksel_round_rate,
644 .set_rate = &omap2_clksel_set_rate,
647 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
648 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
649 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
653 static struct clk iva_hsd_byp_clk_mux_ck = {
654 .name = "iva_hsd_byp_clk_mux_ck",
655 .parent = &sys_clkin_ck,
656 .clksel = iva_hsd_byp_clk_mux_sel,
657 .init = &omap2_init_clksel_parent,
658 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
659 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
661 .recalc = &omap2_clksel_recalc,
665 static struct dpll_data dpll_iva_dd = {
666 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
667 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
668 .clk_ref = &sys_clkin_ck,
669 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
670 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
671 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
672 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
673 .mult_mask = OMAP4430_DPLL_MULT_MASK,
674 .div1_mask = OMAP4430_DPLL_DIV_MASK,
675 .enable_mask = OMAP4430_DPLL_EN_MASK,
676 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
677 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
678 .max_multiplier = 2047,
684 static struct clk dpll_iva_ck = {
685 .name = "dpll_iva_ck",
686 .parent = &sys_clkin_ck,
687 .dpll_data = &dpll_iva_dd,
688 .init = &omap2_init_dpll_parent,
689 .ops = &clkops_omap3_noncore_dpll_ops,
690 .recalc = &omap3_dpll_recalc,
691 .round_rate = &omap2_dpll_round_rate,
692 .set_rate = &omap3_noncore_dpll_set_rate,
695 static struct clk dpll_iva_x2_ck = {
696 .name = "dpll_iva_x2_ck",
697 .parent = &dpll_iva_ck,
698 .flags = CLOCK_CLKOUTX2,
700 .recalc = &omap3_clkoutx2_recalc,
703 static const struct clksel dpll_iva_m4x2_div[] = {
704 { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
708 static struct clk dpll_iva_m4x2_ck = {
709 .name = "dpll_iva_m4x2_ck",
710 .parent = &dpll_iva_x2_ck,
711 .clksel = dpll_iva_m4x2_div,
712 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
713 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
714 .ops = &clkops_omap4_dpllmx_ops,
715 .recalc = &omap2_clksel_recalc,
716 .round_rate = &omap2_clksel_round_rate,
717 .set_rate = &omap2_clksel_set_rate,
720 static struct clk dpll_iva_m5x2_ck = {
721 .name = "dpll_iva_m5x2_ck",
722 .parent = &dpll_iva_x2_ck,
723 .clksel = dpll_iva_m4x2_div,
724 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
725 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
726 .ops = &clkops_omap4_dpllmx_ops,
727 .recalc = &omap2_clksel_recalc,
728 .round_rate = &omap2_clksel_round_rate,
729 .set_rate = &omap2_clksel_set_rate,
733 static struct dpll_data dpll_mpu_dd = {
734 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
735 .clk_bypass = &div_mpu_hs_clk,
736 .clk_ref = &sys_clkin_ck,
737 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
738 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
739 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
740 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
741 .mult_mask = OMAP4430_DPLL_MULT_MASK,
742 .div1_mask = OMAP4430_DPLL_DIV_MASK,
743 .enable_mask = OMAP4430_DPLL_EN_MASK,
744 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
745 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
746 .max_multiplier = 2047,
752 static struct clk dpll_mpu_ck = {
753 .name = "dpll_mpu_ck",
754 .parent = &sys_clkin_ck,
755 .dpll_data = &dpll_mpu_dd,
756 .init = &omap2_init_dpll_parent,
757 .ops = &clkops_omap3_noncore_dpll_ops,
758 .recalc = &omap3_dpll_recalc,
759 .round_rate = &omap2_dpll_round_rate,
760 .set_rate = &omap3_noncore_dpll_set_rate,
763 static const struct clksel dpll_mpu_m2_div[] = {
764 { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
768 static struct clk dpll_mpu_m2_ck = {
769 .name = "dpll_mpu_m2_ck",
770 .parent = &dpll_mpu_ck,
771 .clksel = dpll_mpu_m2_div,
772 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
773 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
774 .ops = &clkops_omap4_dpllmx_ops,
775 .recalc = &omap2_clksel_recalc,
776 .round_rate = &omap2_clksel_round_rate,
777 .set_rate = &omap2_clksel_set_rate,
780 static struct clk per_hs_clk_div_ck = {
781 .name = "per_hs_clk_div_ck",
782 .parent = &dpll_abe_m3x2_ck,
785 .recalc = &omap_fixed_divisor_recalc,
788 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
789 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
790 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
794 static struct clk per_hsd_byp_clk_mux_ck = {
795 .name = "per_hsd_byp_clk_mux_ck",
796 .parent = &sys_clkin_ck,
797 .clksel = per_hsd_byp_clk_mux_sel,
798 .init = &omap2_init_clksel_parent,
799 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
800 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
802 .recalc = &omap2_clksel_recalc,
806 static struct dpll_data dpll_per_dd = {
807 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
808 .clk_bypass = &per_hsd_byp_clk_mux_ck,
809 .clk_ref = &sys_clkin_ck,
810 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
811 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
812 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
813 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
814 .mult_mask = OMAP4430_DPLL_MULT_MASK,
815 .div1_mask = OMAP4430_DPLL_DIV_MASK,
816 .enable_mask = OMAP4430_DPLL_EN_MASK,
817 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
818 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
819 .max_multiplier = 2047,
825 static struct clk dpll_per_ck = {
826 .name = "dpll_per_ck",
827 .parent = &sys_clkin_ck,
828 .dpll_data = &dpll_per_dd,
829 .init = &omap2_init_dpll_parent,
830 .ops = &clkops_omap3_noncore_dpll_ops,
831 .recalc = &omap3_dpll_recalc,
832 .round_rate = &omap2_dpll_round_rate,
833 .set_rate = &omap3_noncore_dpll_set_rate,
836 static const struct clksel dpll_per_m2_div[] = {
837 { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
841 static struct clk dpll_per_m2_ck = {
842 .name = "dpll_per_m2_ck",
843 .parent = &dpll_per_ck,
844 .clksel = dpll_per_m2_div,
845 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
846 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
847 .ops = &clkops_omap4_dpllmx_ops,
848 .recalc = &omap2_clksel_recalc,
849 .round_rate = &omap2_clksel_round_rate,
850 .set_rate = &omap2_clksel_set_rate,
853 static struct clk dpll_per_x2_ck = {
854 .name = "dpll_per_x2_ck",
855 .parent = &dpll_per_ck,
856 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
857 .flags = CLOCK_CLKOUTX2,
858 .ops = &clkops_omap4_dpllmx_ops,
859 .recalc = &omap3_clkoutx2_recalc,
862 static const struct clksel dpll_per_m2x2_div[] = {
863 { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
867 static struct clk dpll_per_m2x2_ck = {
868 .name = "dpll_per_m2x2_ck",
869 .parent = &dpll_per_x2_ck,
870 .clksel = dpll_per_m2x2_div,
871 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
872 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
873 .ops = &clkops_omap4_dpllmx_ops,
874 .recalc = &omap2_clksel_recalc,
875 .round_rate = &omap2_clksel_round_rate,
876 .set_rate = &omap2_clksel_set_rate,
879 static struct clk dpll_per_m3x2_ck = {
880 .name = "dpll_per_m3x2_ck",
881 .parent = &dpll_per_x2_ck,
882 .clksel = dpll_per_m2x2_div,
883 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
884 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
885 .ops = &clkops_omap2_dflt,
886 .recalc = &omap2_clksel_recalc,
887 .round_rate = &omap2_clksel_round_rate,
888 .set_rate = &omap2_clksel_set_rate,
889 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
890 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
893 static struct clk dpll_per_m4x2_ck = {
894 .name = "dpll_per_m4x2_ck",
895 .parent = &dpll_per_x2_ck,
896 .clksel = dpll_per_m2x2_div,
897 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
898 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
899 .ops = &clkops_omap4_dpllmx_ops,
900 .recalc = &omap2_clksel_recalc,
901 .round_rate = &omap2_clksel_round_rate,
902 .set_rate = &omap2_clksel_set_rate,
905 static struct clk dpll_per_m5x2_ck = {
906 .name = "dpll_per_m5x2_ck",
907 .parent = &dpll_per_x2_ck,
908 .clksel = dpll_per_m2x2_div,
909 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
910 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
911 .ops = &clkops_omap4_dpllmx_ops,
912 .recalc = &omap2_clksel_recalc,
913 .round_rate = &omap2_clksel_round_rate,
914 .set_rate = &omap2_clksel_set_rate,
917 static struct clk dpll_per_m6x2_ck = {
918 .name = "dpll_per_m6x2_ck",
919 .parent = &dpll_per_x2_ck,
920 .clksel = dpll_per_m2x2_div,
921 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
922 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
923 .ops = &clkops_omap4_dpllmx_ops,
924 .recalc = &omap2_clksel_recalc,
925 .round_rate = &omap2_clksel_round_rate,
926 .set_rate = &omap2_clksel_set_rate,
929 static struct clk dpll_per_m7x2_ck = {
930 .name = "dpll_per_m7x2_ck",
931 .parent = &dpll_per_x2_ck,
932 .clksel = dpll_per_m2x2_div,
933 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
934 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
935 .ops = &clkops_omap4_dpllmx_ops,
936 .recalc = &omap2_clksel_recalc,
937 .round_rate = &omap2_clksel_round_rate,
938 .set_rate = &omap2_clksel_set_rate,
941 static struct clk usb_hs_clk_div_ck = {
942 .name = "usb_hs_clk_div_ck",
943 .parent = &dpll_abe_m3x2_ck,
946 .recalc = &omap_fixed_divisor_recalc,
950 static struct dpll_data dpll_usb_dd = {
951 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
952 .clk_bypass = &usb_hs_clk_div_ck,
953 .flags = DPLL_J_TYPE,
954 .clk_ref = &sys_clkin_ck,
955 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
956 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
957 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
958 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
959 .mult_mask = OMAP4430_DPLL_MULT_MASK,
960 .div1_mask = OMAP4430_DPLL_DIV_MASK,
961 .enable_mask = OMAP4430_DPLL_EN_MASK,
962 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
963 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
964 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
965 .max_multiplier = 4095,
971 static struct clk dpll_usb_ck = {
972 .name = "dpll_usb_ck",
973 .parent = &sys_clkin_ck,
974 .dpll_data = &dpll_usb_dd,
975 .init = &omap2_init_dpll_parent,
976 .ops = &clkops_omap3_noncore_dpll_ops,
977 .recalc = &omap3_dpll_recalc,
978 .round_rate = &omap2_dpll_round_rate,
979 .set_rate = &omap3_noncore_dpll_set_rate,
982 static struct clk dpll_usb_clkdcoldo_ck = {
983 .name = "dpll_usb_clkdcoldo_ck",
984 .parent = &dpll_usb_ck,
985 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
986 .ops = &clkops_omap4_dpllmx_ops,
987 .recalc = &followparent_recalc,
990 static const struct clksel dpll_usb_m2_div[] = {
991 { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
995 static struct clk dpll_usb_m2_ck = {
996 .name = "dpll_usb_m2_ck",
997 .parent = &dpll_usb_ck,
998 .clksel = dpll_usb_m2_div,
999 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
1000 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
1001 .ops = &clkops_omap4_dpllmx_ops,
1002 .recalc = &omap2_clksel_recalc,
1003 .round_rate = &omap2_clksel_round_rate,
1004 .set_rate = &omap2_clksel_set_rate,
1007 static const struct clksel ducati_clk_mux_sel[] = {
1008 { .parent = &div_core_ck, .rates = div_1_0_rates },
1009 { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1013 static struct clk ducati_clk_mux_ck = {
1014 .name = "ducati_clk_mux_ck",
1015 .parent = &div_core_ck,
1016 .clksel = ducati_clk_mux_sel,
1017 .init = &omap2_init_clksel_parent,
1018 .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1019 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1020 .ops = &clkops_null,
1021 .recalc = &omap2_clksel_recalc,
1024 static struct clk func_12m_fclk = {
1025 .name = "func_12m_fclk",
1026 .parent = &dpll_per_m2x2_ck,
1027 .ops = &clkops_null,
1029 .recalc = &omap_fixed_divisor_recalc,
1032 static struct clk func_24m_clk = {
1033 .name = "func_24m_clk",
1034 .parent = &dpll_per_m2_ck,
1035 .ops = &clkops_null,
1037 .recalc = &omap_fixed_divisor_recalc,
1040 static struct clk func_24mc_fclk = {
1041 .name = "func_24mc_fclk",
1042 .parent = &dpll_per_m2x2_ck,
1043 .ops = &clkops_null,
1045 .recalc = &omap_fixed_divisor_recalc,
1048 static const struct clksel_rate div2_4to8_rates[] = {
1049 { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1050 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1054 static const struct clksel func_48m_fclk_div[] = {
1055 { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1059 static struct clk func_48m_fclk = {
1060 .name = "func_48m_fclk",
1061 .parent = &dpll_per_m2x2_ck,
1062 .clksel = func_48m_fclk_div,
1063 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1064 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1065 .ops = &clkops_null,
1066 .recalc = &omap2_clksel_recalc,
1067 .round_rate = &omap2_clksel_round_rate,
1068 .set_rate = &omap2_clksel_set_rate,
1071 static struct clk func_48mc_fclk = {
1072 .name = "func_48mc_fclk",
1073 .parent = &dpll_per_m2x2_ck,
1074 .ops = &clkops_null,
1076 .recalc = &omap_fixed_divisor_recalc,
1079 static const struct clksel_rate div2_2to4_rates[] = {
1080 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1081 { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1085 static const struct clksel func_64m_fclk_div[] = {
1086 { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1090 static struct clk func_64m_fclk = {
1091 .name = "func_64m_fclk",
1092 .parent = &dpll_per_m4x2_ck,
1093 .clksel = func_64m_fclk_div,
1094 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1095 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1096 .ops = &clkops_null,
1097 .recalc = &omap2_clksel_recalc,
1098 .round_rate = &omap2_clksel_round_rate,
1099 .set_rate = &omap2_clksel_set_rate,
1102 static const struct clksel func_96m_fclk_div[] = {
1103 { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1107 static struct clk func_96m_fclk = {
1108 .name = "func_96m_fclk",
1109 .parent = &dpll_per_m2x2_ck,
1110 .clksel = func_96m_fclk_div,
1111 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1112 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1113 .ops = &clkops_null,
1114 .recalc = &omap2_clksel_recalc,
1115 .round_rate = &omap2_clksel_round_rate,
1116 .set_rate = &omap2_clksel_set_rate,
1119 static const struct clksel_rate div2_1to8_rates[] = {
1120 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1121 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1125 static const struct clksel init_60m_fclk_div[] = {
1126 { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1130 static struct clk init_60m_fclk = {
1131 .name = "init_60m_fclk",
1132 .parent = &dpll_usb_m2_ck,
1133 .clksel = init_60m_fclk_div,
1134 .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ,
1135 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1136 .ops = &clkops_null,
1137 .recalc = &omap2_clksel_recalc,
1138 .round_rate = &omap2_clksel_round_rate,
1139 .set_rate = &omap2_clksel_set_rate,
1142 static const struct clksel l3_div_div[] = {
1143 { .parent = &div_core_ck, .rates = div2_1to2_rates },
1147 static struct clk l3_div_ck = {
1148 .name = "l3_div_ck",
1149 .parent = &div_core_ck,
1150 .clksel = l3_div_div,
1151 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1152 .clksel_mask = OMAP4430_CLKSEL_L3_MASK,
1153 .ops = &clkops_null,
1154 .recalc = &omap2_clksel_recalc,
1155 .round_rate = &omap2_clksel_round_rate,
1156 .set_rate = &omap2_clksel_set_rate,
1159 static const struct clksel l4_div_div[] = {
1160 { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1164 static struct clk l4_div_ck = {
1165 .name = "l4_div_ck",
1166 .parent = &l3_div_ck,
1167 .clksel = l4_div_div,
1168 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1169 .clksel_mask = OMAP4430_CLKSEL_L4_MASK,
1170 .ops = &clkops_null,
1171 .recalc = &omap2_clksel_recalc,
1172 .round_rate = &omap2_clksel_round_rate,
1173 .set_rate = &omap2_clksel_set_rate,
1176 static struct clk lp_clk_div_ck = {
1177 .name = "lp_clk_div_ck",
1178 .parent = &dpll_abe_m2x2_ck,
1179 .ops = &clkops_null,
1181 .recalc = &omap_fixed_divisor_recalc,
1184 static const struct clksel l4_wkup_clk_mux_sel[] = {
1185 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1186 { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1190 static struct clk l4_wkup_clk_mux_ck = {
1191 .name = "l4_wkup_clk_mux_ck",
1192 .parent = &sys_clkin_ck,
1193 .clksel = l4_wkup_clk_mux_sel,
1194 .init = &omap2_init_clksel_parent,
1195 .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL,
1196 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1197 .ops = &clkops_null,
1198 .recalc = &omap2_clksel_recalc,
1201 static const struct clksel_rate div2_2to1_rates[] = {
1202 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
1203 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1207 static const struct clksel ocp_abe_iclk_div[] = {
1208 { .parent = &aess_fclk, .rates = div2_2to1_rates },
1212 static struct clk mpu_periphclk = {
1213 .name = "mpu_periphclk",
1214 .parent = &dpll_mpu_ck,
1215 .ops = &clkops_null,
1217 .recalc = &omap_fixed_divisor_recalc,
1220 static struct clk ocp_abe_iclk = {
1221 .name = "ocp_abe_iclk",
1222 .parent = &aess_fclk,
1223 .clksel = ocp_abe_iclk_div,
1224 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1225 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
1226 .ops = &clkops_null,
1227 .recalc = &omap2_clksel_recalc,
1230 static struct clk per_abe_24m_fclk = {
1231 .name = "per_abe_24m_fclk",
1232 .parent = &dpll_abe_m2_ck,
1233 .ops = &clkops_null,
1235 .recalc = &omap_fixed_divisor_recalc,
1238 static const struct clksel per_abe_nc_fclk_div[] = {
1239 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1243 static struct clk per_abe_nc_fclk = {
1244 .name = "per_abe_nc_fclk",
1245 .parent = &dpll_abe_m2_ck,
1246 .clksel = per_abe_nc_fclk_div,
1247 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1248 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1249 .ops = &clkops_null,
1250 .recalc = &omap2_clksel_recalc,
1251 .round_rate = &omap2_clksel_round_rate,
1252 .set_rate = &omap2_clksel_set_rate,
1255 static const struct clksel pmd_stm_clock_mux_sel[] = {
1256 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1257 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1258 { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1262 static struct clk pmd_stm_clock_mux_ck = {
1263 .name = "pmd_stm_clock_mux_ck",
1264 .parent = &sys_clkin_ck,
1265 .ops = &clkops_null,
1266 .recalc = &followparent_recalc,
1269 static struct clk pmd_trace_clk_mux_ck = {
1270 .name = "pmd_trace_clk_mux_ck",
1271 .parent = &sys_clkin_ck,
1272 .ops = &clkops_null,
1273 .recalc = &followparent_recalc,
1276 static const struct clksel syc_clk_div_div[] = {
1277 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1281 static struct clk syc_clk_div_ck = {
1282 .name = "syc_clk_div_ck",
1283 .parent = &sys_clkin_ck,
1284 .clksel = syc_clk_div_div,
1285 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1286 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1287 .ops = &clkops_null,
1288 .recalc = &omap2_clksel_recalc,
1289 .round_rate = &omap2_clksel_round_rate,
1290 .set_rate = &omap2_clksel_set_rate,
1293 /* Leaf clocks controlled by modules */
1295 static struct clk aes1_fck = {
1297 .ops = &clkops_omap2_dflt,
1298 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1299 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1300 .clkdm_name = "l4_secure_clkdm",
1301 .parent = &l3_div_ck,
1302 .recalc = &followparent_recalc,
1305 static struct clk aes2_fck = {
1307 .ops = &clkops_omap2_dflt,
1308 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1309 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1310 .clkdm_name = "l4_secure_clkdm",
1311 .parent = &l3_div_ck,
1312 .recalc = &followparent_recalc,
1315 static struct clk aess_fck = {
1317 .ops = &clkops_omap2_dflt,
1318 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1319 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1320 .clkdm_name = "abe_clkdm",
1321 .parent = &aess_fclk,
1322 .recalc = &followparent_recalc,
1325 static struct clk bandgap_fclk = {
1326 .name = "bandgap_fclk",
1327 .ops = &clkops_omap2_dflt,
1328 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1329 .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1330 .clkdm_name = "l4_wkup_clkdm",
1331 .parent = &sys_32k_ck,
1332 .recalc = &followparent_recalc,
1335 static struct clk des3des_fck = {
1336 .name = "des3des_fck",
1337 .ops = &clkops_omap2_dflt,
1338 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1339 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1340 .clkdm_name = "l4_secure_clkdm",
1341 .parent = &l4_div_ck,
1342 .recalc = &followparent_recalc,
1345 static const struct clksel dmic_sync_mux_sel[] = {
1346 { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1347 { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1348 { .parent = &func_24m_clk, .rates = div_1_2_rates },
1352 static struct clk dmic_sync_mux_ck = {
1353 .name = "dmic_sync_mux_ck",
1354 .parent = &abe_24m_fclk,
1355 .clksel = dmic_sync_mux_sel,
1356 .init = &omap2_init_clksel_parent,
1357 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1358 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1359 .ops = &clkops_null,
1360 .recalc = &omap2_clksel_recalc,
1363 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1364 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1365 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1366 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1370 /* Merged func_dmic_abe_gfclk into dmic */
1371 static struct clk dmic_fck = {
1373 .parent = &dmic_sync_mux_ck,
1374 .clksel = func_dmic_abe_gfclk_sel,
1375 .init = &omap2_init_clksel_parent,
1376 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1377 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1378 .ops = &clkops_omap2_dflt,
1379 .recalc = &omap2_clksel_recalc,
1380 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1381 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1382 .clkdm_name = "abe_clkdm",
1385 static struct clk dsp_fck = {
1387 .ops = &clkops_omap2_dflt,
1388 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1389 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1390 .clkdm_name = "tesla_clkdm",
1391 .parent = &dpll_iva_m4x2_ck,
1392 .recalc = &followparent_recalc,
1395 static struct clk dss_sys_clk = {
1396 .name = "dss_sys_clk",
1397 .ops = &clkops_omap2_dflt,
1398 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1399 .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1400 .clkdm_name = "l3_dss_clkdm",
1401 .parent = &syc_clk_div_ck,
1402 .recalc = &followparent_recalc,
1405 static struct clk dss_tv_clk = {
1406 .name = "dss_tv_clk",
1407 .ops = &clkops_omap2_dflt,
1408 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1409 .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1410 .clkdm_name = "l3_dss_clkdm",
1411 .parent = &extalt_clkin_ck,
1412 .recalc = &followparent_recalc,
1415 static struct clk dss_dss_clk = {
1416 .name = "dss_dss_clk",
1417 .ops = &clkops_omap2_dflt,
1418 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1419 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1420 .clkdm_name = "l3_dss_clkdm",
1421 .parent = &dpll_per_m5x2_ck,
1422 .recalc = &followparent_recalc,
1425 static const struct clksel_rate div3_8to32_rates[] = {
1426 { .div = 8, .val = 0, .flags = RATE_IN_4460 },
1427 { .div = 16, .val = 1, .flags = RATE_IN_4460 },
1428 { .div = 32, .val = 2, .flags = RATE_IN_4460 },
1432 static const struct clksel div_ts_div[] = {
1433 { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
1437 static struct clk div_ts_ck = {
1438 .name = "div_ts_ck",
1439 .parent = &l4_wkup_clk_mux_ck,
1440 .clksel = div_ts_div,
1441 .clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1442 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1443 .ops = &clkops_null,
1444 .recalc = &omap2_clksel_recalc,
1445 .round_rate = &omap2_clksel_round_rate,
1446 .set_rate = &omap2_clksel_set_rate,
1449 static struct clk bandgap_ts_fclk = {
1450 .name = "bandgap_ts_fclk",
1451 .ops = &clkops_omap2_dflt,
1452 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1453 .enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
1454 .clkdm_name = "l4_wkup_clkdm",
1455 .parent = &div_ts_ck,
1456 .recalc = &followparent_recalc,
1459 static struct clk dss_48mhz_clk = {
1460 .name = "dss_48mhz_clk",
1461 .ops = &clkops_omap2_dflt,
1462 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1463 .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1464 .clkdm_name = "l3_dss_clkdm",
1465 .parent = &func_48mc_fclk,
1466 .recalc = &followparent_recalc,
1469 static struct clk dss_fck = {
1471 .ops = &clkops_omap2_dflt,
1472 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1473 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1474 .clkdm_name = "l3_dss_clkdm",
1475 .parent = &l3_div_ck,
1476 .recalc = &followparent_recalc,
1479 static struct clk efuse_ctrl_cust_fck = {
1480 .name = "efuse_ctrl_cust_fck",
1481 .ops = &clkops_omap2_dflt,
1482 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1483 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1484 .clkdm_name = "l4_cefuse_clkdm",
1485 .parent = &sys_clkin_ck,
1486 .recalc = &followparent_recalc,
1489 static struct clk emif1_fck = {
1490 .name = "emif1_fck",
1491 .ops = &clkops_omap2_dflt,
1492 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1493 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1494 .flags = ENABLE_ON_INIT,
1495 .clkdm_name = "l3_emif_clkdm",
1496 .parent = &ddrphy_ck,
1497 .recalc = &followparent_recalc,
1500 static struct clk emif2_fck = {
1501 .name = "emif2_fck",
1502 .ops = &clkops_omap2_dflt,
1503 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1504 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1505 .flags = ENABLE_ON_INIT,
1506 .clkdm_name = "l3_emif_clkdm",
1507 .parent = &ddrphy_ck,
1508 .recalc = &followparent_recalc,
1511 static const struct clksel fdif_fclk_div[] = {
1512 { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1516 /* Merged fdif_fclk into fdif */
1517 static struct clk fdif_fck = {
1519 .parent = &dpll_per_m4x2_ck,
1520 .clksel = fdif_fclk_div,
1521 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1522 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
1523 .ops = &clkops_omap2_dflt,
1524 .recalc = &omap2_clksel_recalc,
1525 .round_rate = &omap2_clksel_round_rate,
1526 .set_rate = &omap2_clksel_set_rate,
1527 .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1528 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1529 .clkdm_name = "iss_clkdm",
1532 static struct clk fpka_fck = {
1534 .ops = &clkops_omap2_dflt,
1535 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1536 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1537 .clkdm_name = "l4_secure_clkdm",
1538 .parent = &l4_div_ck,
1539 .recalc = &followparent_recalc,
1542 static struct clk gpio1_dbclk = {
1543 .name = "gpio1_dbclk",
1544 .ops = &clkops_omap2_dflt,
1545 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1546 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1547 .clkdm_name = "l4_wkup_clkdm",
1548 .parent = &sys_32k_ck,
1549 .recalc = &followparent_recalc,
1552 static struct clk gpio1_ick = {
1553 .name = "gpio1_ick",
1554 .ops = &clkops_omap2_dflt,
1555 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1556 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1557 .clkdm_name = "l4_wkup_clkdm",
1558 .parent = &l4_wkup_clk_mux_ck,
1559 .recalc = &followparent_recalc,
1562 static struct clk gpio2_dbclk = {
1563 .name = "gpio2_dbclk",
1564 .ops = &clkops_omap2_dflt,
1565 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1566 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1567 .clkdm_name = "l4_per_clkdm",
1568 .parent = &sys_32k_ck,
1569 .recalc = &followparent_recalc,
1572 static struct clk gpio2_ick = {
1573 .name = "gpio2_ick",
1574 .ops = &clkops_omap2_dflt,
1575 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1576 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1577 .clkdm_name = "l4_per_clkdm",
1578 .parent = &l4_div_ck,
1579 .recalc = &followparent_recalc,
1582 static struct clk gpio3_dbclk = {
1583 .name = "gpio3_dbclk",
1584 .ops = &clkops_omap2_dflt,
1585 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1586 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1587 .clkdm_name = "l4_per_clkdm",
1588 .parent = &sys_32k_ck,
1589 .recalc = &followparent_recalc,
1592 static struct clk gpio3_ick = {
1593 .name = "gpio3_ick",
1594 .ops = &clkops_omap2_dflt,
1595 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1596 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1597 .clkdm_name = "l4_per_clkdm",
1598 .parent = &l4_div_ck,
1599 .recalc = &followparent_recalc,
1602 static struct clk gpio4_dbclk = {
1603 .name = "gpio4_dbclk",
1604 .ops = &clkops_omap2_dflt,
1605 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1606 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1607 .clkdm_name = "l4_per_clkdm",
1608 .parent = &sys_32k_ck,
1609 .recalc = &followparent_recalc,
1612 static struct clk gpio4_ick = {
1613 .name = "gpio4_ick",
1614 .ops = &clkops_omap2_dflt,
1615 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1616 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1617 .clkdm_name = "l4_per_clkdm",
1618 .parent = &l4_div_ck,
1619 .recalc = &followparent_recalc,
1622 static struct clk gpio5_dbclk = {
1623 .name = "gpio5_dbclk",
1624 .ops = &clkops_omap2_dflt,
1625 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1626 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1627 .clkdm_name = "l4_per_clkdm",
1628 .parent = &sys_32k_ck,
1629 .recalc = &followparent_recalc,
1632 static struct clk gpio5_ick = {
1633 .name = "gpio5_ick",
1634 .ops = &clkops_omap2_dflt,
1635 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1636 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1637 .clkdm_name = "l4_per_clkdm",
1638 .parent = &l4_div_ck,
1639 .recalc = &followparent_recalc,
1642 static struct clk gpio6_dbclk = {
1643 .name = "gpio6_dbclk",
1644 .ops = &clkops_omap2_dflt,
1645 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1646 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1647 .clkdm_name = "l4_per_clkdm",
1648 .parent = &sys_32k_ck,
1649 .recalc = &followparent_recalc,
1652 static struct clk gpio6_ick = {
1653 .name = "gpio6_ick",
1654 .ops = &clkops_omap2_dflt,
1655 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1656 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1657 .clkdm_name = "l4_per_clkdm",
1658 .parent = &l4_div_ck,
1659 .recalc = &followparent_recalc,
1662 static struct clk gpmc_ick = {
1664 .ops = &clkops_omap2_dflt,
1665 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1666 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1667 .flags = ENABLE_ON_INIT,
1668 .clkdm_name = "l3_2_clkdm",
1669 .parent = &l3_div_ck,
1670 .recalc = &followparent_recalc,
1673 static const struct clksel sgx_clk_mux_sel[] = {
1674 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1675 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1679 /* Merged sgx_clk_mux into gpu */
1680 static struct clk gpu_fck = {
1682 .parent = &dpll_core_m7x2_ck,
1683 .clksel = sgx_clk_mux_sel,
1684 .init = &omap2_init_clksel_parent,
1685 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1686 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1687 .ops = &clkops_omap2_dflt,
1688 .recalc = &omap2_clksel_recalc,
1689 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1690 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1691 .clkdm_name = "l3_gfx_clkdm",
1694 static struct clk hdq1w_fck = {
1695 .name = "hdq1w_fck",
1696 .ops = &clkops_omap2_dflt,
1697 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1698 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1699 .clkdm_name = "l4_per_clkdm",
1700 .parent = &func_12m_fclk,
1701 .recalc = &followparent_recalc,
1704 static const struct clksel hsi_fclk_div[] = {
1705 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1709 /* Merged hsi_fclk into hsi */
1710 static struct clk hsi_fck = {
1712 .parent = &dpll_per_m2x2_ck,
1713 .clksel = hsi_fclk_div,
1714 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1715 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1716 .ops = &clkops_omap2_dflt,
1717 .recalc = &omap2_clksel_recalc,
1718 .round_rate = &omap2_clksel_round_rate,
1719 .set_rate = &omap2_clksel_set_rate,
1720 .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1721 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1722 .clkdm_name = "l3_init_clkdm",
1725 static struct clk i2c1_fck = {
1727 .ops = &clkops_omap2_dflt,
1728 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1729 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1730 .clkdm_name = "l4_per_clkdm",
1731 .parent = &func_96m_fclk,
1732 .recalc = &followparent_recalc,
1735 static struct clk i2c2_fck = {
1737 .ops = &clkops_omap2_dflt,
1738 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1739 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1740 .clkdm_name = "l4_per_clkdm",
1741 .parent = &func_96m_fclk,
1742 .recalc = &followparent_recalc,
1745 static struct clk i2c3_fck = {
1747 .ops = &clkops_omap2_dflt,
1748 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1749 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1750 .clkdm_name = "l4_per_clkdm",
1751 .parent = &func_96m_fclk,
1752 .recalc = &followparent_recalc,
1755 static struct clk i2c4_fck = {
1757 .ops = &clkops_omap2_dflt,
1758 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1759 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1760 .clkdm_name = "l4_per_clkdm",
1761 .parent = &func_96m_fclk,
1762 .recalc = &followparent_recalc,
1765 static struct clk ipu_fck = {
1767 .ops = &clkops_omap2_dflt,
1768 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1769 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1770 .clkdm_name = "ducati_clkdm",
1771 .parent = &ducati_clk_mux_ck,
1772 .recalc = &followparent_recalc,
1775 static struct clk iss_ctrlclk = {
1776 .name = "iss_ctrlclk",
1777 .ops = &clkops_omap2_dflt,
1778 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1779 .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1780 .clkdm_name = "iss_clkdm",
1781 .parent = &func_96m_fclk,
1782 .recalc = &followparent_recalc,
1785 static struct clk iss_fck = {
1787 .ops = &clkops_omap2_dflt,
1788 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1789 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1790 .clkdm_name = "iss_clkdm",
1791 .parent = &ducati_clk_mux_ck,
1792 .recalc = &followparent_recalc,
1795 static struct clk iva_fck = {
1797 .ops = &clkops_omap2_dflt,
1798 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1799 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1800 .clkdm_name = "ivahd_clkdm",
1801 .parent = &dpll_iva_m5x2_ck,
1802 .recalc = &followparent_recalc,
1805 static struct clk kbd_fck = {
1807 .ops = &clkops_omap2_dflt,
1808 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1809 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1810 .clkdm_name = "l4_wkup_clkdm",
1811 .parent = &sys_32k_ck,
1812 .recalc = &followparent_recalc,
1815 static struct clk l3_instr_ick = {
1816 .name = "l3_instr_ick",
1817 .ops = &clkops_omap2_dflt,
1818 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1819 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1820 .flags = ENABLE_ON_INIT,
1821 .clkdm_name = "l3_instr_clkdm",
1822 .parent = &l3_div_ck,
1823 .recalc = &followparent_recalc,
1826 static struct clk l3_main_3_ick = {
1827 .name = "l3_main_3_ick",
1828 .ops = &clkops_omap2_dflt,
1829 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1830 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1831 .flags = ENABLE_ON_INIT,
1832 .clkdm_name = "l3_instr_clkdm",
1833 .parent = &l3_div_ck,
1834 .recalc = &followparent_recalc,
1837 static struct clk mcasp_sync_mux_ck = {
1838 .name = "mcasp_sync_mux_ck",
1839 .parent = &abe_24m_fclk,
1840 .clksel = dmic_sync_mux_sel,
1841 .init = &omap2_init_clksel_parent,
1842 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1843 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1844 .ops = &clkops_null,
1845 .recalc = &omap2_clksel_recalc,
1848 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1849 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1850 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1851 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1855 /* Merged func_mcasp_abe_gfclk into mcasp */
1856 static struct clk mcasp_fck = {
1857 .name = "mcasp_fck",
1858 .parent = &mcasp_sync_mux_ck,
1859 .clksel = func_mcasp_abe_gfclk_sel,
1860 .init = &omap2_init_clksel_parent,
1861 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1862 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1863 .ops = &clkops_omap2_dflt,
1864 .recalc = &omap2_clksel_recalc,
1865 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1866 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1867 .clkdm_name = "abe_clkdm",
1870 static struct clk mcbsp1_sync_mux_ck = {
1871 .name = "mcbsp1_sync_mux_ck",
1872 .parent = &abe_24m_fclk,
1873 .clksel = dmic_sync_mux_sel,
1874 .init = &omap2_init_clksel_parent,
1875 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1876 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1877 .ops = &clkops_null,
1878 .recalc = &omap2_clksel_recalc,
1881 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1882 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1883 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1884 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1888 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1889 static struct clk mcbsp1_fck = {
1890 .name = "mcbsp1_fck",
1891 .parent = &mcbsp1_sync_mux_ck,
1892 .clksel = func_mcbsp1_gfclk_sel,
1893 .init = &omap2_init_clksel_parent,
1894 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1895 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1896 .ops = &clkops_omap2_dflt,
1897 .recalc = &omap2_clksel_recalc,
1898 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1899 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1900 .clkdm_name = "abe_clkdm",
1903 static struct clk mcbsp2_sync_mux_ck = {
1904 .name = "mcbsp2_sync_mux_ck",
1905 .parent = &abe_24m_fclk,
1906 .clksel = dmic_sync_mux_sel,
1907 .init = &omap2_init_clksel_parent,
1908 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1909 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1910 .ops = &clkops_null,
1911 .recalc = &omap2_clksel_recalc,
1914 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1915 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1916 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1917 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1921 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1922 static struct clk mcbsp2_fck = {
1923 .name = "mcbsp2_fck",
1924 .parent = &mcbsp2_sync_mux_ck,
1925 .clksel = func_mcbsp2_gfclk_sel,
1926 .init = &omap2_init_clksel_parent,
1927 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1928 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1929 .ops = &clkops_omap2_dflt,
1930 .recalc = &omap2_clksel_recalc,
1931 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1932 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1933 .clkdm_name = "abe_clkdm",
1936 static struct clk mcbsp3_sync_mux_ck = {
1937 .name = "mcbsp3_sync_mux_ck",
1938 .parent = &abe_24m_fclk,
1939 .clksel = dmic_sync_mux_sel,
1940 .init = &omap2_init_clksel_parent,
1941 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1942 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1943 .ops = &clkops_null,
1944 .recalc = &omap2_clksel_recalc,
1947 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1948 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1949 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1950 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1954 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1955 static struct clk mcbsp3_fck = {
1956 .name = "mcbsp3_fck",
1957 .parent = &mcbsp3_sync_mux_ck,
1958 .clksel = func_mcbsp3_gfclk_sel,
1959 .init = &omap2_init_clksel_parent,
1960 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1961 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1962 .ops = &clkops_omap2_dflt,
1963 .recalc = &omap2_clksel_recalc,
1964 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1965 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1966 .clkdm_name = "abe_clkdm",
1969 static const struct clksel mcbsp4_sync_mux_sel[] = {
1970 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1971 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1975 static struct clk mcbsp4_sync_mux_ck = {
1976 .name = "mcbsp4_sync_mux_ck",
1977 .parent = &func_96m_fclk,
1978 .clksel = mcbsp4_sync_mux_sel,
1979 .init = &omap2_init_clksel_parent,
1980 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1981 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1982 .ops = &clkops_null,
1983 .recalc = &omap2_clksel_recalc,
1986 static const struct clksel per_mcbsp4_gfclk_sel[] = {
1987 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1988 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1992 /* Merged per_mcbsp4_gfclk into mcbsp4 */
1993 static struct clk mcbsp4_fck = {
1994 .name = "mcbsp4_fck",
1995 .parent = &mcbsp4_sync_mux_ck,
1996 .clksel = per_mcbsp4_gfclk_sel,
1997 .init = &omap2_init_clksel_parent,
1998 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1999 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
2000 .ops = &clkops_omap2_dflt,
2001 .recalc = &omap2_clksel_recalc,
2002 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2003 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2004 .clkdm_name = "l4_per_clkdm",
2007 static struct clk mcpdm_fck = {
2008 .name = "mcpdm_fck",
2009 .ops = &clkops_omap2_dflt,
2010 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2011 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2012 .clkdm_name = "abe_clkdm",
2013 .parent = &pad_clks_ck,
2014 .recalc = &followparent_recalc,
2017 static struct clk mcspi1_fck = {
2018 .name = "mcspi1_fck",
2019 .ops = &clkops_omap2_dflt,
2020 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2021 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2022 .clkdm_name = "l4_per_clkdm",
2023 .parent = &func_48m_fclk,
2024 .recalc = &followparent_recalc,
2027 static struct clk mcspi2_fck = {
2028 .name = "mcspi2_fck",
2029 .ops = &clkops_omap2_dflt,
2030 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2031 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2032 .clkdm_name = "l4_per_clkdm",
2033 .parent = &func_48m_fclk,
2034 .recalc = &followparent_recalc,
2037 static struct clk mcspi3_fck = {
2038 .name = "mcspi3_fck",
2039 .ops = &clkops_omap2_dflt,
2040 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2041 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2042 .clkdm_name = "l4_per_clkdm",
2043 .parent = &func_48m_fclk,
2044 .recalc = &followparent_recalc,
2047 static struct clk mcspi4_fck = {
2048 .name = "mcspi4_fck",
2049 .ops = &clkops_omap2_dflt,
2050 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2051 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2052 .clkdm_name = "l4_per_clkdm",
2053 .parent = &func_48m_fclk,
2054 .recalc = &followparent_recalc,
2057 static const struct clksel hsmmc1_fclk_sel[] = {
2058 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
2059 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
2063 /* Merged hsmmc1_fclk into mmc1 */
2064 static struct clk mmc1_fck = {
2066 .parent = &func_64m_fclk,
2067 .clksel = hsmmc1_fclk_sel,
2068 .init = &omap2_init_clksel_parent,
2069 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2070 .clksel_mask = OMAP4430_CLKSEL_MASK,
2071 .ops = &clkops_omap2_dflt,
2072 .recalc = &omap2_clksel_recalc,
2073 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2074 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2075 .clkdm_name = "l3_init_clkdm",
2078 /* Merged hsmmc2_fclk into mmc2 */
2079 static struct clk mmc2_fck = {
2081 .parent = &func_64m_fclk,
2082 .clksel = hsmmc1_fclk_sel,
2083 .init = &omap2_init_clksel_parent,
2084 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2085 .clksel_mask = OMAP4430_CLKSEL_MASK,
2086 .ops = &clkops_omap2_dflt,
2087 .recalc = &omap2_clksel_recalc,
2088 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2089 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2090 .clkdm_name = "l3_init_clkdm",
2093 static struct clk mmc3_fck = {
2095 .ops = &clkops_omap2_dflt,
2096 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2097 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2098 .clkdm_name = "l4_per_clkdm",
2099 .parent = &func_48m_fclk,
2100 .recalc = &followparent_recalc,
2103 static struct clk mmc4_fck = {
2105 .ops = &clkops_omap2_dflt,
2106 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2107 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2108 .clkdm_name = "l4_per_clkdm",
2109 .parent = &func_48m_fclk,
2110 .recalc = &followparent_recalc,
2113 static struct clk mmc5_fck = {
2115 .ops = &clkops_omap2_dflt,
2116 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2117 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2118 .clkdm_name = "l4_per_clkdm",
2119 .parent = &func_48m_fclk,
2120 .recalc = &followparent_recalc,
2123 static struct clk ocp2scp_usb_phy_phy_48m = {
2124 .name = "ocp2scp_usb_phy_phy_48m",
2125 .ops = &clkops_omap2_dflt,
2126 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2127 .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2128 .clkdm_name = "l3_init_clkdm",
2129 .parent = &func_48m_fclk,
2130 .recalc = &followparent_recalc,
2133 static struct clk ocp2scp_usb_phy_ick = {
2134 .name = "ocp2scp_usb_phy_ick",
2135 .ops = &clkops_omap2_dflt,
2136 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2137 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2138 .clkdm_name = "l3_init_clkdm",
2139 .parent = &l4_div_ck,
2140 .recalc = &followparent_recalc,
2143 static struct clk ocp_wp_noc_ick = {
2144 .name = "ocp_wp_noc_ick",
2145 .ops = &clkops_omap2_dflt,
2146 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2147 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2148 .flags = ENABLE_ON_INIT,
2149 .clkdm_name = "l3_instr_clkdm",
2150 .parent = &l3_div_ck,
2151 .recalc = &followparent_recalc,
2154 static struct clk rng_ick = {
2156 .ops = &clkops_omap2_dflt,
2157 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2158 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2159 .clkdm_name = "l4_secure_clkdm",
2160 .parent = &l4_div_ck,
2161 .recalc = &followparent_recalc,
2164 static struct clk sha2md5_fck = {
2165 .name = "sha2md5_fck",
2166 .ops = &clkops_omap2_dflt,
2167 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2168 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2169 .clkdm_name = "l4_secure_clkdm",
2170 .parent = &l3_div_ck,
2171 .recalc = &followparent_recalc,
2174 static struct clk sl2if_ick = {
2175 .name = "sl2if_ick",
2176 .ops = &clkops_omap2_dflt,
2177 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2178 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2179 .clkdm_name = "ivahd_clkdm",
2180 .parent = &dpll_iva_m5x2_ck,
2181 .recalc = &followparent_recalc,
2184 static struct clk slimbus1_fclk_1 = {
2185 .name = "slimbus1_fclk_1",
2186 .ops = &clkops_omap2_dflt,
2187 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2188 .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2189 .clkdm_name = "abe_clkdm",
2190 .parent = &func_24m_clk,
2191 .recalc = &followparent_recalc,
2194 static struct clk slimbus1_fclk_0 = {
2195 .name = "slimbus1_fclk_0",
2196 .ops = &clkops_omap2_dflt,
2197 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2198 .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2199 .clkdm_name = "abe_clkdm",
2200 .parent = &abe_24m_fclk,
2201 .recalc = &followparent_recalc,
2204 static struct clk slimbus1_fclk_2 = {
2205 .name = "slimbus1_fclk_2",
2206 .ops = &clkops_omap2_dflt,
2207 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2208 .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2209 .clkdm_name = "abe_clkdm",
2210 .parent = &pad_clks_ck,
2211 .recalc = &followparent_recalc,
2214 static struct clk slimbus1_slimbus_clk = {
2215 .name = "slimbus1_slimbus_clk",
2216 .ops = &clkops_omap2_dflt,
2217 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2218 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2219 .clkdm_name = "abe_clkdm",
2220 .parent = &slimbus_clk,
2221 .recalc = &followparent_recalc,
2224 static struct clk slimbus1_fck = {
2225 .name = "slimbus1_fck",
2226 .ops = &clkops_omap2_dflt,
2227 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2228 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2229 .clkdm_name = "abe_clkdm",
2230 .parent = &ocp_abe_iclk,
2231 .recalc = &followparent_recalc,
2234 static struct clk slimbus2_fclk_1 = {
2235 .name = "slimbus2_fclk_1",
2236 .ops = &clkops_omap2_dflt,
2237 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2238 .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2239 .clkdm_name = "l4_per_clkdm",
2240 .parent = &per_abe_24m_fclk,
2241 .recalc = &followparent_recalc,
2244 static struct clk slimbus2_fclk_0 = {
2245 .name = "slimbus2_fclk_0",
2246 .ops = &clkops_omap2_dflt,
2247 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2248 .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2249 .clkdm_name = "l4_per_clkdm",
2250 .parent = &func_24mc_fclk,
2251 .recalc = &followparent_recalc,
2254 static struct clk slimbus2_slimbus_clk = {
2255 .name = "slimbus2_slimbus_clk",
2256 .ops = &clkops_omap2_dflt,
2257 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2258 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2259 .clkdm_name = "l4_per_clkdm",
2260 .parent = &pad_slimbus_core_clks_ck,
2261 .recalc = &followparent_recalc,
2264 static struct clk slimbus2_fck = {
2265 .name = "slimbus2_fck",
2266 .ops = &clkops_omap2_dflt,
2267 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2268 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2269 .clkdm_name = "l4_per_clkdm",
2270 .parent = &l4_div_ck,
2271 .recalc = &followparent_recalc,
2274 static struct clk smartreflex_core_fck = {
2275 .name = "smartreflex_core_fck",
2276 .ops = &clkops_omap2_dflt,
2277 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2278 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2279 .clkdm_name = "l4_ao_clkdm",
2280 .parent = &l4_wkup_clk_mux_ck,
2281 .recalc = &followparent_recalc,
2284 static struct clk smartreflex_iva_fck = {
2285 .name = "smartreflex_iva_fck",
2286 .ops = &clkops_omap2_dflt,
2287 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2288 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2289 .clkdm_name = "l4_ao_clkdm",
2290 .parent = &l4_wkup_clk_mux_ck,
2291 .recalc = &followparent_recalc,
2294 static struct clk smartreflex_mpu_fck = {
2295 .name = "smartreflex_mpu_fck",
2296 .ops = &clkops_omap2_dflt,
2297 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2298 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2299 .clkdm_name = "l4_ao_clkdm",
2300 .parent = &l4_wkup_clk_mux_ck,
2301 .recalc = &followparent_recalc,
2304 /* Merged dmt1_clk_mux into timer1 */
2305 static struct clk timer1_fck = {
2306 .name = "timer1_fck",
2307 .parent = &sys_clkin_ck,
2308 .clksel = abe_dpll_bypass_clk_mux_sel,
2309 .init = &omap2_init_clksel_parent,
2310 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2311 .clksel_mask = OMAP4430_CLKSEL_MASK,
2312 .ops = &clkops_omap2_dflt,
2313 .recalc = &omap2_clksel_recalc,
2314 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2315 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2316 .clkdm_name = "l4_wkup_clkdm",
2319 /* Merged cm2_dm10_mux into timer10 */
2320 static struct clk timer10_fck = {
2321 .name = "timer10_fck",
2322 .parent = &sys_clkin_ck,
2323 .clksel = abe_dpll_bypass_clk_mux_sel,
2324 .init = &omap2_init_clksel_parent,
2325 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2326 .clksel_mask = OMAP4430_CLKSEL_MASK,
2327 .ops = &clkops_omap2_dflt,
2328 .recalc = &omap2_clksel_recalc,
2329 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2330 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2331 .clkdm_name = "l4_per_clkdm",
2334 /* Merged cm2_dm11_mux into timer11 */
2335 static struct clk timer11_fck = {
2336 .name = "timer11_fck",
2337 .parent = &sys_clkin_ck,
2338 .clksel = abe_dpll_bypass_clk_mux_sel,
2339 .init = &omap2_init_clksel_parent,
2340 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2341 .clksel_mask = OMAP4430_CLKSEL_MASK,
2342 .ops = &clkops_omap2_dflt,
2343 .recalc = &omap2_clksel_recalc,
2344 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2345 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2346 .clkdm_name = "l4_per_clkdm",
2349 /* Merged cm2_dm2_mux into timer2 */
2350 static struct clk timer2_fck = {
2351 .name = "timer2_fck",
2352 .parent = &sys_clkin_ck,
2353 .clksel = abe_dpll_bypass_clk_mux_sel,
2354 .init = &omap2_init_clksel_parent,
2355 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2356 .clksel_mask = OMAP4430_CLKSEL_MASK,
2357 .ops = &clkops_omap2_dflt,
2358 .recalc = &omap2_clksel_recalc,
2359 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2360 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2361 .clkdm_name = "l4_per_clkdm",
2364 /* Merged cm2_dm3_mux into timer3 */
2365 static struct clk timer3_fck = {
2366 .name = "timer3_fck",
2367 .parent = &sys_clkin_ck,
2368 .clksel = abe_dpll_bypass_clk_mux_sel,
2369 .init = &omap2_init_clksel_parent,
2370 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2371 .clksel_mask = OMAP4430_CLKSEL_MASK,
2372 .ops = &clkops_omap2_dflt,
2373 .recalc = &omap2_clksel_recalc,
2374 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2375 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2376 .clkdm_name = "l4_per_clkdm",
2379 /* Merged cm2_dm4_mux into timer4 */
2380 static struct clk timer4_fck = {
2381 .name = "timer4_fck",
2382 .parent = &sys_clkin_ck,
2383 .clksel = abe_dpll_bypass_clk_mux_sel,
2384 .init = &omap2_init_clksel_parent,
2385 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2386 .clksel_mask = OMAP4430_CLKSEL_MASK,
2387 .ops = &clkops_omap2_dflt,
2388 .recalc = &omap2_clksel_recalc,
2389 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2390 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2391 .clkdm_name = "l4_per_clkdm",
2394 static const struct clksel timer5_sync_mux_sel[] = {
2395 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2396 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2400 /* Merged timer5_sync_mux into timer5 */
2401 static struct clk timer5_fck = {
2402 .name = "timer5_fck",
2403 .parent = &syc_clk_div_ck,
2404 .clksel = timer5_sync_mux_sel,
2405 .init = &omap2_init_clksel_parent,
2406 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2407 .clksel_mask = OMAP4430_CLKSEL_MASK,
2408 .ops = &clkops_omap2_dflt,
2409 .recalc = &omap2_clksel_recalc,
2410 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2411 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2412 .clkdm_name = "abe_clkdm",
2415 /* Merged timer6_sync_mux into timer6 */
2416 static struct clk timer6_fck = {
2417 .name = "timer6_fck",
2418 .parent = &syc_clk_div_ck,
2419 .clksel = timer5_sync_mux_sel,
2420 .init = &omap2_init_clksel_parent,
2421 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2422 .clksel_mask = OMAP4430_CLKSEL_MASK,
2423 .ops = &clkops_omap2_dflt,
2424 .recalc = &omap2_clksel_recalc,
2425 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2426 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2427 .clkdm_name = "abe_clkdm",
2430 /* Merged timer7_sync_mux into timer7 */
2431 static struct clk timer7_fck = {
2432 .name = "timer7_fck",
2433 .parent = &syc_clk_div_ck,
2434 .clksel = timer5_sync_mux_sel,
2435 .init = &omap2_init_clksel_parent,
2436 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2437 .clksel_mask = OMAP4430_CLKSEL_MASK,
2438 .ops = &clkops_omap2_dflt,
2439 .recalc = &omap2_clksel_recalc,
2440 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2441 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2442 .clkdm_name = "abe_clkdm",
2445 /* Merged timer8_sync_mux into timer8 */
2446 static struct clk timer8_fck = {
2447 .name = "timer8_fck",
2448 .parent = &syc_clk_div_ck,
2449 .clksel = timer5_sync_mux_sel,
2450 .init = &omap2_init_clksel_parent,
2451 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2452 .clksel_mask = OMAP4430_CLKSEL_MASK,
2453 .ops = &clkops_omap2_dflt,
2454 .recalc = &omap2_clksel_recalc,
2455 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2456 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2457 .clkdm_name = "abe_clkdm",
2460 /* Merged cm2_dm9_mux into timer9 */
2461 static struct clk timer9_fck = {
2462 .name = "timer9_fck",
2463 .parent = &sys_clkin_ck,
2464 .clksel = abe_dpll_bypass_clk_mux_sel,
2465 .init = &omap2_init_clksel_parent,
2466 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2467 .clksel_mask = OMAP4430_CLKSEL_MASK,
2468 .ops = &clkops_omap2_dflt,
2469 .recalc = &omap2_clksel_recalc,
2470 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2471 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2472 .clkdm_name = "l4_per_clkdm",
2475 static struct clk uart1_fck = {
2476 .name = "uart1_fck",
2477 .ops = &clkops_omap2_dflt,
2478 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2479 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2480 .clkdm_name = "l4_per_clkdm",
2481 .parent = &func_48m_fclk,
2482 .recalc = &followparent_recalc,
2485 static struct clk uart2_fck = {
2486 .name = "uart2_fck",
2487 .ops = &clkops_omap2_dflt,
2488 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2489 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2490 .clkdm_name = "l4_per_clkdm",
2491 .parent = &func_48m_fclk,
2492 .recalc = &followparent_recalc,
2495 static struct clk uart3_fck = {
2496 .name = "uart3_fck",
2497 .ops = &clkops_omap2_dflt,
2498 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2499 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2500 .clkdm_name = "l4_per_clkdm",
2501 .parent = &func_48m_fclk,
2502 .recalc = &followparent_recalc,
2505 static struct clk uart4_fck = {
2506 .name = "uart4_fck",
2507 .ops = &clkops_omap2_dflt,
2508 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2509 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2510 .clkdm_name = "l4_per_clkdm",
2511 .parent = &func_48m_fclk,
2512 .recalc = &followparent_recalc,
2515 static struct clk usb_host_fs_fck = {
2516 .name = "usb_host_fs_fck",
2517 .ops = &clkops_omap2_dflt,
2518 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2519 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2520 .clkdm_name = "l3_init_clkdm",
2521 .parent = &func_48mc_fclk,
2522 .recalc = &followparent_recalc,
2525 static const struct clksel utmi_p1_gfclk_sel[] = {
2526 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2527 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2531 static struct clk utmi_p1_gfclk = {
2532 .name = "utmi_p1_gfclk",
2533 .parent = &init_60m_fclk,
2534 .clksel = utmi_p1_gfclk_sel,
2535 .init = &omap2_init_clksel_parent,
2536 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2537 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2538 .ops = &clkops_null,
2539 .recalc = &omap2_clksel_recalc,
2542 static struct clk usb_host_hs_utmi_p1_clk = {
2543 .name = "usb_host_hs_utmi_p1_clk",
2544 .ops = &clkops_omap2_dflt,
2545 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2546 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2547 .clkdm_name = "l3_init_clkdm",
2548 .parent = &utmi_p1_gfclk,
2549 .recalc = &followparent_recalc,
2552 static const struct clksel utmi_p2_gfclk_sel[] = {
2553 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2554 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2558 static struct clk utmi_p2_gfclk = {
2559 .name = "utmi_p2_gfclk",
2560 .parent = &init_60m_fclk,
2561 .clksel = utmi_p2_gfclk_sel,
2562 .init = &omap2_init_clksel_parent,
2563 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2564 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2565 .ops = &clkops_null,
2566 .recalc = &omap2_clksel_recalc,
2569 static struct clk usb_host_hs_utmi_p2_clk = {
2570 .name = "usb_host_hs_utmi_p2_clk",
2571 .ops = &clkops_omap2_dflt,
2572 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2573 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2574 .clkdm_name = "l3_init_clkdm",
2575 .parent = &utmi_p2_gfclk,
2576 .recalc = &followparent_recalc,
2579 static struct clk usb_host_hs_utmi_p3_clk = {
2580 .name = "usb_host_hs_utmi_p3_clk",
2581 .ops = &clkops_omap2_dflt,
2582 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2583 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2584 .clkdm_name = "l3_init_clkdm",
2585 .parent = &init_60m_fclk,
2586 .recalc = &followparent_recalc,
2589 static struct clk usb_host_hs_hsic480m_p1_clk = {
2590 .name = "usb_host_hs_hsic480m_p1_clk",
2591 .ops = &clkops_omap2_dflt,
2592 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2593 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2594 .clkdm_name = "l3_init_clkdm",
2595 .parent = &dpll_usb_m2_ck,
2596 .recalc = &followparent_recalc,
2599 static struct clk usb_host_hs_hsic60m_p1_clk = {
2600 .name = "usb_host_hs_hsic60m_p1_clk",
2601 .ops = &clkops_omap2_dflt,
2602 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2603 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2604 .clkdm_name = "l3_init_clkdm",
2605 .parent = &init_60m_fclk,
2606 .recalc = &followparent_recalc,
2609 static struct clk usb_host_hs_hsic60m_p2_clk = {
2610 .name = "usb_host_hs_hsic60m_p2_clk",
2611 .ops = &clkops_omap2_dflt,
2612 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2613 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2614 .clkdm_name = "l3_init_clkdm",
2615 .parent = &init_60m_fclk,
2616 .recalc = &followparent_recalc,
2619 static struct clk usb_host_hs_hsic480m_p2_clk = {
2620 .name = "usb_host_hs_hsic480m_p2_clk",
2621 .ops = &clkops_omap2_dflt,
2622 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2623 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2624 .clkdm_name = "l3_init_clkdm",
2625 .parent = &dpll_usb_m2_ck,
2626 .recalc = &followparent_recalc,
2629 static struct clk usb_host_hs_func48mclk = {
2630 .name = "usb_host_hs_func48mclk",
2631 .ops = &clkops_omap2_dflt,
2632 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2633 .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2634 .clkdm_name = "l3_init_clkdm",
2635 .parent = &func_48mc_fclk,
2636 .recalc = &followparent_recalc,
2639 static struct clk usb_host_hs_fck = {
2640 .name = "usb_host_hs_fck",
2641 .ops = &clkops_omap2_dflt,
2642 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2643 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2644 .clkdm_name = "l3_init_clkdm",
2645 .parent = &init_60m_fclk,
2646 .recalc = &followparent_recalc,
2649 static const struct clksel otg_60m_gfclk_sel[] = {
2650 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2651 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2655 static struct clk otg_60m_gfclk = {
2656 .name = "otg_60m_gfclk",
2657 .parent = &utmi_phy_clkout_ck,
2658 .clksel = otg_60m_gfclk_sel,
2659 .init = &omap2_init_clksel_parent,
2660 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2661 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2662 .ops = &clkops_null,
2663 .recalc = &omap2_clksel_recalc,
2666 static struct clk usb_otg_hs_xclk = {
2667 .name = "usb_otg_hs_xclk",
2668 .ops = &clkops_omap2_dflt,
2669 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2670 .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2671 .clkdm_name = "l3_init_clkdm",
2672 .parent = &otg_60m_gfclk,
2673 .recalc = &followparent_recalc,
2676 static struct clk usb_otg_hs_ick = {
2677 .name = "usb_otg_hs_ick",
2678 .ops = &clkops_omap2_dflt,
2679 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2680 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2681 .clkdm_name = "l3_init_clkdm",
2682 .parent = &l3_div_ck,
2683 .recalc = &followparent_recalc,
2686 static struct clk usb_phy_cm_clk32k = {
2687 .name = "usb_phy_cm_clk32k",
2688 .ops = &clkops_omap2_dflt,
2689 .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2690 .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2691 .clkdm_name = "l4_ao_clkdm",
2692 .parent = &sys_32k_ck,
2693 .recalc = &followparent_recalc,
2696 static struct clk usb_tll_hs_usb_ch2_clk = {
2697 .name = "usb_tll_hs_usb_ch2_clk",
2698 .ops = &clkops_omap2_dflt,
2699 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2700 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2701 .clkdm_name = "l3_init_clkdm",
2702 .parent = &init_60m_fclk,
2703 .recalc = &followparent_recalc,
2706 static struct clk usb_tll_hs_usb_ch0_clk = {
2707 .name = "usb_tll_hs_usb_ch0_clk",
2708 .ops = &clkops_omap2_dflt,
2709 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2710 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2711 .clkdm_name = "l3_init_clkdm",
2712 .parent = &init_60m_fclk,
2713 .recalc = &followparent_recalc,
2716 static struct clk usb_tll_hs_usb_ch1_clk = {
2717 .name = "usb_tll_hs_usb_ch1_clk",
2718 .ops = &clkops_omap2_dflt,
2719 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2720 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2721 .clkdm_name = "l3_init_clkdm",
2722 .parent = &init_60m_fclk,
2723 .recalc = &followparent_recalc,
2726 static struct clk usb_tll_hs_ick = {
2727 .name = "usb_tll_hs_ick",
2728 .ops = &clkops_omap2_dflt,
2729 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2730 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2731 .clkdm_name = "l3_init_clkdm",
2732 .parent = &l4_div_ck,
2733 .recalc = &followparent_recalc,
2736 static const struct clksel_rate div2_14to18_rates[] = {
2737 { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2738 { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2742 static const struct clksel usim_fclk_div[] = {
2743 { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2747 static struct clk usim_ck = {
2749 .parent = &dpll_per_m4x2_ck,
2750 .clksel = usim_fclk_div,
2751 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2752 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
2753 .ops = &clkops_null,
2754 .recalc = &omap2_clksel_recalc,
2755 .round_rate = &omap2_clksel_round_rate,
2756 .set_rate = &omap2_clksel_set_rate,
2759 static struct clk usim_fclk = {
2760 .name = "usim_fclk",
2761 .ops = &clkops_omap2_dflt,
2762 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2763 .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2764 .clkdm_name = "l4_wkup_clkdm",
2766 .recalc = &followparent_recalc,
2769 static struct clk usim_fck = {
2771 .ops = &clkops_omap2_dflt,
2772 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2773 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2774 .clkdm_name = "l4_wkup_clkdm",
2775 .parent = &sys_32k_ck,
2776 .recalc = &followparent_recalc,
2779 static struct clk wd_timer2_fck = {
2780 .name = "wd_timer2_fck",
2781 .ops = &clkops_omap2_dflt,
2782 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2783 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2784 .clkdm_name = "l4_wkup_clkdm",
2785 .parent = &sys_32k_ck,
2786 .recalc = &followparent_recalc,
2789 static struct clk wd_timer3_fck = {
2790 .name = "wd_timer3_fck",
2791 .ops = &clkops_omap2_dflt,
2792 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2793 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2794 .clkdm_name = "abe_clkdm",
2795 .parent = &sys_32k_ck,
2796 .recalc = &followparent_recalc,
2799 /* Remaining optional clocks */
2800 static const struct clksel stm_clk_div_div[] = {
2801 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2805 static struct clk stm_clk_div_ck = {
2806 .name = "stm_clk_div_ck",
2807 .parent = &pmd_stm_clock_mux_ck,
2808 .clksel = stm_clk_div_div,
2809 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2810 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2811 .ops = &clkops_null,
2812 .recalc = &omap2_clksel_recalc,
2813 .round_rate = &omap2_clksel_round_rate,
2814 .set_rate = &omap2_clksel_set_rate,
2817 static const struct clksel trace_clk_div_div[] = {
2818 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2822 static struct clk trace_clk_div_ck = {
2823 .name = "trace_clk_div_ck",
2824 .parent = &pmd_trace_clk_mux_ck,
2825 .clksel = trace_clk_div_div,
2826 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2827 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2828 .ops = &clkops_null,
2829 .recalc = &omap2_clksel_recalc,
2830 .round_rate = &omap2_clksel_round_rate,
2831 .set_rate = &omap2_clksel_set_rate,
2834 /* SCRM aux clk nodes */
2836 static const struct clksel auxclk_src_sel[] = {
2837 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2838 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2839 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2843 static const struct clksel_rate div16_1to16_rates[] = {
2844 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
2845 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
2846 { .div = 3, .val = 2, .flags = RATE_IN_4430 },
2847 { .div = 4, .val = 3, .flags = RATE_IN_4430 },
2848 { .div = 5, .val = 4, .flags = RATE_IN_4430 },
2849 { .div = 6, .val = 5, .flags = RATE_IN_4430 },
2850 { .div = 7, .val = 6, .flags = RATE_IN_4430 },
2851 { .div = 8, .val = 7, .flags = RATE_IN_4430 },
2852 { .div = 9, .val = 8, .flags = RATE_IN_4430 },
2853 { .div = 10, .val = 9, .flags = RATE_IN_4430 },
2854 { .div = 11, .val = 10, .flags = RATE_IN_4430 },
2855 { .div = 12, .val = 11, .flags = RATE_IN_4430 },
2856 { .div = 13, .val = 12, .flags = RATE_IN_4430 },
2857 { .div = 14, .val = 13, .flags = RATE_IN_4430 },
2858 { .div = 15, .val = 14, .flags = RATE_IN_4430 },
2859 { .div = 16, .val = 15, .flags = RATE_IN_4430 },
2863 static struct clk auxclk0_src_ck = {
2864 .name = "auxclk0_src_ck",
2865 .parent = &sys_clkin_ck,
2866 .init = &omap2_init_clksel_parent,
2867 .ops = &clkops_omap2_dflt,
2868 .clksel = auxclk_src_sel,
2869 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2870 .clksel_mask = OMAP4_SRCSELECT_MASK,
2871 .recalc = &omap2_clksel_recalc,
2872 .enable_reg = OMAP4_SCRM_AUXCLK0,
2873 .enable_bit = OMAP4_ENABLE_SHIFT,
2876 static const struct clksel auxclk0_sel[] = {
2877 { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
2881 static struct clk auxclk0_ck = {
2882 .name = "auxclk0_ck",
2883 .parent = &auxclk0_src_ck,
2884 .clksel = auxclk0_sel,
2885 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2886 .clksel_mask = OMAP4_CLKDIV_MASK,
2887 .ops = &clkops_null,
2888 .recalc = &omap2_clksel_recalc,
2889 .round_rate = &omap2_clksel_round_rate,
2890 .set_rate = &omap2_clksel_set_rate,
2893 static struct clk auxclk1_src_ck = {
2894 .name = "auxclk1_src_ck",
2895 .parent = &sys_clkin_ck,
2896 .init = &omap2_init_clksel_parent,
2897 .ops = &clkops_omap2_dflt,
2898 .clksel = auxclk_src_sel,
2899 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2900 .clksel_mask = OMAP4_SRCSELECT_MASK,
2901 .recalc = &omap2_clksel_recalc,
2902 .enable_reg = OMAP4_SCRM_AUXCLK1,
2903 .enable_bit = OMAP4_ENABLE_SHIFT,
2906 static const struct clksel auxclk1_sel[] = {
2907 { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
2911 static struct clk auxclk1_ck = {
2912 .name = "auxclk1_ck",
2913 .parent = &auxclk1_src_ck,
2914 .clksel = auxclk1_sel,
2915 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2916 .clksel_mask = OMAP4_CLKDIV_MASK,
2917 .ops = &clkops_null,
2918 .recalc = &omap2_clksel_recalc,
2919 .round_rate = &omap2_clksel_round_rate,
2920 .set_rate = &omap2_clksel_set_rate,
2923 static struct clk auxclk2_src_ck = {
2924 .name = "auxclk2_src_ck",
2925 .parent = &sys_clkin_ck,
2926 .init = &omap2_init_clksel_parent,
2927 .ops = &clkops_omap2_dflt,
2928 .clksel = auxclk_src_sel,
2929 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2930 .clksel_mask = OMAP4_SRCSELECT_MASK,
2931 .recalc = &omap2_clksel_recalc,
2932 .enable_reg = OMAP4_SCRM_AUXCLK2,
2933 .enable_bit = OMAP4_ENABLE_SHIFT,
2936 static const struct clksel auxclk2_sel[] = {
2937 { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
2941 static struct clk auxclk2_ck = {
2942 .name = "auxclk2_ck",
2943 .parent = &auxclk2_src_ck,
2944 .clksel = auxclk2_sel,
2945 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2946 .clksel_mask = OMAP4_CLKDIV_MASK,
2947 .ops = &clkops_null,
2948 .recalc = &omap2_clksel_recalc,
2949 .round_rate = &omap2_clksel_round_rate,
2950 .set_rate = &omap2_clksel_set_rate,
2953 static struct clk auxclk3_src_ck = {
2954 .name = "auxclk3_src_ck",
2955 .parent = &sys_clkin_ck,
2956 .init = &omap2_init_clksel_parent,
2957 .ops = &clkops_omap2_dflt,
2958 .clksel = auxclk_src_sel,
2959 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2960 .clksel_mask = OMAP4_SRCSELECT_MASK,
2961 .recalc = &omap2_clksel_recalc,
2962 .enable_reg = OMAP4_SCRM_AUXCLK3,
2963 .enable_bit = OMAP4_ENABLE_SHIFT,
2966 static const struct clksel auxclk3_sel[] = {
2967 { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
2971 static struct clk auxclk3_ck = {
2972 .name = "auxclk3_ck",
2973 .parent = &auxclk3_src_ck,
2974 .clksel = auxclk3_sel,
2975 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2976 .clksel_mask = OMAP4_CLKDIV_MASK,
2977 .ops = &clkops_null,
2978 .recalc = &omap2_clksel_recalc,
2979 .round_rate = &omap2_clksel_round_rate,
2980 .set_rate = &omap2_clksel_set_rate,
2983 static struct clk auxclk4_src_ck = {
2984 .name = "auxclk4_src_ck",
2985 .parent = &sys_clkin_ck,
2986 .init = &omap2_init_clksel_parent,
2987 .ops = &clkops_omap2_dflt,
2988 .clksel = auxclk_src_sel,
2989 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2990 .clksel_mask = OMAP4_SRCSELECT_MASK,
2991 .recalc = &omap2_clksel_recalc,
2992 .enable_reg = OMAP4_SCRM_AUXCLK4,
2993 .enable_bit = OMAP4_ENABLE_SHIFT,
2996 static const struct clksel auxclk4_sel[] = {
2997 { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
3001 static struct clk auxclk4_ck = {
3002 .name = "auxclk4_ck",
3003 .parent = &auxclk4_src_ck,
3004 .clksel = auxclk4_sel,
3005 .clksel_reg = OMAP4_SCRM_AUXCLK4,
3006 .clksel_mask = OMAP4_CLKDIV_MASK,
3007 .ops = &clkops_null,
3008 .recalc = &omap2_clksel_recalc,
3009 .round_rate = &omap2_clksel_round_rate,
3010 .set_rate = &omap2_clksel_set_rate,
3013 static struct clk auxclk5_src_ck = {
3014 .name = "auxclk5_src_ck",
3015 .parent = &sys_clkin_ck,
3016 .init = &omap2_init_clksel_parent,
3017 .ops = &clkops_omap2_dflt,
3018 .clksel = auxclk_src_sel,
3019 .clksel_reg = OMAP4_SCRM_AUXCLK5,
3020 .clksel_mask = OMAP4_SRCSELECT_MASK,
3021 .recalc = &omap2_clksel_recalc,
3022 .enable_reg = OMAP4_SCRM_AUXCLK5,
3023 .enable_bit = OMAP4_ENABLE_SHIFT,
3026 static const struct clksel auxclk5_sel[] = {
3027 { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
3031 static struct clk auxclk5_ck = {
3032 .name = "auxclk5_ck",
3033 .parent = &auxclk5_src_ck,
3034 .clksel = auxclk5_sel,
3035 .clksel_reg = OMAP4_SCRM_AUXCLK5,
3036 .clksel_mask = OMAP4_CLKDIV_MASK,
3037 .ops = &clkops_null,
3038 .recalc = &omap2_clksel_recalc,
3039 .round_rate = &omap2_clksel_round_rate,
3040 .set_rate = &omap2_clksel_set_rate,
3043 static const struct clksel auxclkreq_sel[] = {
3044 { .parent = &auxclk0_ck, .rates = div_1_0_rates },
3045 { .parent = &auxclk1_ck, .rates = div_1_1_rates },
3046 { .parent = &auxclk2_ck, .rates = div_1_2_rates },
3047 { .parent = &auxclk3_ck, .rates = div_1_3_rates },
3048 { .parent = &auxclk4_ck, .rates = div_1_4_rates },
3049 { .parent = &auxclk5_ck, .rates = div_1_5_rates },
3053 static struct clk auxclkreq0_ck = {
3054 .name = "auxclkreq0_ck",
3055 .parent = &auxclk0_ck,
3056 .init = &omap2_init_clksel_parent,
3057 .ops = &clkops_null,
3058 .clksel = auxclkreq_sel,
3059 .clksel_reg = OMAP4_SCRM_AUXCLKREQ0,
3060 .clksel_mask = OMAP4_MAPPING_MASK,
3061 .recalc = &omap2_clksel_recalc,
3064 static struct clk auxclkreq1_ck = {
3065 .name = "auxclkreq1_ck",
3066 .parent = &auxclk1_ck,
3067 .init = &omap2_init_clksel_parent,
3068 .ops = &clkops_null,
3069 .clksel = auxclkreq_sel,
3070 .clksel_reg = OMAP4_SCRM_AUXCLKREQ1,
3071 .clksel_mask = OMAP4_MAPPING_MASK,
3072 .recalc = &omap2_clksel_recalc,
3075 static struct clk auxclkreq2_ck = {
3076 .name = "auxclkreq2_ck",
3077 .parent = &auxclk2_ck,
3078 .init = &omap2_init_clksel_parent,
3079 .ops = &clkops_null,
3080 .clksel = auxclkreq_sel,
3081 .clksel_reg = OMAP4_SCRM_AUXCLKREQ2,
3082 .clksel_mask = OMAP4_MAPPING_MASK,
3083 .recalc = &omap2_clksel_recalc,
3086 static struct clk auxclkreq3_ck = {
3087 .name = "auxclkreq3_ck",
3088 .parent = &auxclk3_ck,
3089 .init = &omap2_init_clksel_parent,
3090 .ops = &clkops_null,
3091 .clksel = auxclkreq_sel,
3092 .clksel_reg = OMAP4_SCRM_AUXCLKREQ3,
3093 .clksel_mask = OMAP4_MAPPING_MASK,
3094 .recalc = &omap2_clksel_recalc,
3097 static struct clk auxclkreq4_ck = {
3098 .name = "auxclkreq4_ck",
3099 .parent = &auxclk4_ck,
3100 .init = &omap2_init_clksel_parent,
3101 .ops = &clkops_null,
3102 .clksel = auxclkreq_sel,
3103 .clksel_reg = OMAP4_SCRM_AUXCLKREQ4,
3104 .clksel_mask = OMAP4_MAPPING_MASK,
3105 .recalc = &omap2_clksel_recalc,
3108 static struct clk auxclkreq5_ck = {
3109 .name = "auxclkreq5_ck",
3110 .parent = &auxclk5_ck,
3111 .init = &omap2_init_clksel_parent,
3112 .ops = &clkops_null,
3113 .clksel = auxclkreq_sel,
3114 .clksel_reg = OMAP4_SCRM_AUXCLKREQ5,
3115 .clksel_mask = OMAP4_MAPPING_MASK,
3116 .recalc = &omap2_clksel_recalc,
3123 static struct omap_clk omap44xx_clks[] = {
3124 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
3125 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
3126 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
3127 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
3128 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
3129 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
3130 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
3131 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
3132 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
3133 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
3134 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
3135 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
3136 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
3137 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
3138 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
3139 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
3140 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
3141 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
3142 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
3143 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
3144 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
3145 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
3146 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X),
3147 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
3148 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
3149 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
3150 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
3151 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X),
3152 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
3153 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
3154 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X),
3155 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X),
3156 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
3157 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
3158 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
3159 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X),
3160 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
3161 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
3162 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
3163 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X),
3164 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
3165 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
3166 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X),
3167 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X),
3168 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
3169 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
3170 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X),
3171 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X),
3172 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X),
3173 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
3174 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
3175 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
3176 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
3177 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
3178 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
3179 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X),
3180 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
3181 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X),
3182 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X),
3183 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
3184 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
3185 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
3186 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
3187 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
3188 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
3189 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
3190 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
3191 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
3192 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
3193 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
3194 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
3195 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
3196 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
3197 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
3198 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
3199 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
3200 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
3201 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
3202 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
3203 CLK("smp_twd", NULL, &mpu_periphclk, CK_443X),
3204 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
3205 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
3206 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
3207 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
3208 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
3209 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
3210 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
3211 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
3212 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
3213 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
3214 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
3215 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
3216 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
3217 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
3218 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
3219 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
3220 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
3221 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
3222 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
3223 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
3224 CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
3225 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
3226 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
3227 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
3228 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
3229 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
3230 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
3231 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
3232 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
3233 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
3234 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
3235 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
3236 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
3237 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
3238 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
3239 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
3240 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
3241 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
3242 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
3243 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
3244 CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
3245 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
3246 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
3247 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
3248 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
3249 CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
3250 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
3251 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
3252 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
3253 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
3254 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
3255 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
3256 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
3257 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
3258 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
3259 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
3260 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X),
3261 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
3262 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X),
3263 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
3264 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
3265 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
3266 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
3267 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
3268 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
3269 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
3270 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
3271 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
3272 CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
3273 CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
3274 CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
3275 CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
3276 CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
3277 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
3278 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
3279 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
3280 CLK("omap_rng", "ick", &rng_ick, CK_443X),
3281 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
3282 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
3283 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
3284 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
3285 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
3286 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
3287 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
3288 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
3289 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
3290 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
3291 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
3292 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
3293 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
3294 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
3295 CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X),
3296 CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X),
3297 CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X),
3298 CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X),
3299 CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X),
3300 CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X),
3301 CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X),
3302 CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X),
3303 CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X),
3304 CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X),
3305 CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X),
3306 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
3307 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
3308 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
3309 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
3310 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
3311 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
3312 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
3313 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
3314 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
3315 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
3316 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
3317 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
3318 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
3319 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
3320 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
3321 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X),
3322 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
3323 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
3324 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
3325 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
3326 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
3327 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
3328 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
3329 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
3330 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
3331 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
3332 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
3333 CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
3334 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
3335 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
3336 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
3337 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
3338 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
3339 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
3340 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
3341 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3342 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
3343 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
3344 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3345 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
3346 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
3347 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3348 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
3349 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
3350 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3351 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
3352 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
3353 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3354 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3355 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
3356 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
3357 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
3358 CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X),
3359 CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X),
3360 CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X),
3361 CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X),
3362 CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X),
3363 CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X),
3364 CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
3365 CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
3366 CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
3367 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
3368 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
3369 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
3370 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
3371 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
3372 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
3373 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
3374 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
3375 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X),
3376 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X),
3377 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
3378 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
3379 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
3380 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
3381 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
3382 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
3383 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
3384 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
3385 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
3386 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
3387 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
3388 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
3389 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
3390 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
3391 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
3392 CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X),
3393 CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X),
3394 CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_443X),
3395 CLK("omap_timer.4", "32k_ck", &sys_32k_ck, CK_443X),
3396 CLK("omap_timer.5", "32k_ck", &sys_32k_ck, CK_443X),
3397 CLK("omap_timer.6", "32k_ck", &sys_32k_ck, CK_443X),
3398 CLK("omap_timer.7", "32k_ck", &sys_32k_ck, CK_443X),
3399 CLK("omap_timer.8", "32k_ck", &sys_32k_ck, CK_443X),
3400 CLK("omap_timer.9", "32k_ck", &sys_32k_ck, CK_443X),
3401 CLK("omap_timer.10", "32k_ck", &sys_32k_ck, CK_443X),
3402 CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_443X),
3403 CLK("omap_timer.1", "sys_ck", &sys_clkin_ck, CK_443X),
3404 CLK("omap_timer.2", "sys_ck", &sys_clkin_ck, CK_443X),
3405 CLK("omap_timer.3", "sys_ck", &sys_clkin_ck, CK_443X),
3406 CLK("omap_timer.4", "sys_ck", &sys_clkin_ck, CK_443X),
3407 CLK("omap_timer.9", "sys_ck", &sys_clkin_ck, CK_443X),
3408 CLK("omap_timer.10", "sys_ck", &sys_clkin_ck, CK_443X),
3409 CLK("omap_timer.11", "sys_ck", &sys_clkin_ck, CK_443X),
3410 CLK("omap_timer.5", "sys_ck", &syc_clk_div_ck, CK_443X),
3411 CLK("omap_timer.6", "sys_ck", &syc_clk_div_ck, CK_443X),
3412 CLK("omap_timer.7", "sys_ck", &syc_clk_div_ck, CK_443X),
3413 CLK("omap_timer.8", "sys_ck", &syc_clk_div_ck, CK_443X),
3416 int __init omap4xxx_clk_init(void)
3421 if (cpu_is_omap443x()) {
3422 cpu_mask = RATE_IN_4430;
3423 cpu_clkflg = CK_443X;
3424 } else if (cpu_is_omap446x()) {
3425 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
3426 cpu_clkflg = CK_446X | CK_443X;
3431 clk_init(&omap2_clk_functions);
3434 * Must stay commented until all OMAP SoC drivers are
3435 * converted to runtime PM, or drivers may start crashing
3437 * omap2_clk_disable_clkdm_control();
3440 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3442 clk_preinit(c->lk.clk);
3444 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3446 if (c->cpu & cpu_clkflg) {
3448 clk_register(c->lk.clk);
3449 omap2_init_clk_clkdm(c->lk.clk);
3452 /* Disable autoidle on all clocks; let the PM code enable it later */
3453 omap_clk_disable_autoidle_all();
3455 recalculate_root_clocks();
3458 * Only enable those clocks we will need, let the drivers
3459 * enable other clocks as necessary
3461 clk_enable_init_clocks();