4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
7 * Reference taken from from OMAP4 cminst44xx.c
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
25 #include "../plat-omap/common.h"
27 #include "clockdomain.h"
30 #include "cm-regbits-34xx.h"
31 #include "cm-regbits-33xx.h"
35 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
37 * 0x0 func: Module is fully functional, including OCP
38 * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
40 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
41 * using separate functional clock
42 * 0x3 disabled: Module is disabled and cannot be accessed
45 #define CLKCTRL_IDLEST_FUNCTIONAL 0x0
46 #define CLKCTRL_IDLEST_INTRANSITION 0x1
47 #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
48 #define CLKCTRL_IDLEST_DISABLED 0x3
50 /* Private functions */
52 /* Read a register in a CM instance */
53 static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
55 return __raw_readl(cm_base + inst + idx);
58 /* Write into a register in a CM */
59 static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
61 __raw_writel(val, cm_base + inst + idx);
64 /* Read-modify-write a register in CM */
65 static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
69 v = am33xx_cm_read_reg(inst, idx);
72 am33xx_cm_write_reg(v, inst, idx);
77 static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx)
79 return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx);
82 static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx)
84 return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx);
87 static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
91 v = am33xx_cm_read_reg(inst, idx);
99 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
100 * @inst: CM instance register offset (*_INST macro)
101 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
102 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
104 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
107 static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
109 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
110 v &= AM33XX_IDLEST_MASK;
111 v >>= AM33XX_IDLEST_SHIFT;
116 * _is_module_ready - can module registers be accessed without causing an abort?
117 * @inst: CM instance register offset (*_INST macro)
118 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
119 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
121 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
122 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
124 static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
128 v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs);
130 return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
131 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
135 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
136 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
137 * @inst: CM instance register offset (*_INST macro)
138 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
140 * @c must be the unshifted value for CLKTRCTRL - i.e., this function
141 * will handle the shift itself.
143 static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
147 v = am33xx_cm_read_reg(inst, cdoffs);
148 v &= ~AM33XX_CLKTRCTRL_MASK;
149 v |= c << AM33XX_CLKTRCTRL_SHIFT;
150 am33xx_cm_write_reg(v, inst, cdoffs);
153 /* Public functions */
156 * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
157 * @inst: CM instance register offset (*_INST macro)
158 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
160 * Returns true if the clockdomain referred to by (@inst, @cdoffs)
161 * is in hardware-supervised idle mode, or 0 otherwise.
163 bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
167 v = am33xx_cm_read_reg(inst, cdoffs);
168 v &= AM33XX_CLKTRCTRL_MASK;
169 v >>= AM33XX_CLKTRCTRL_SHIFT;
171 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
175 * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
176 * @inst: CM instance register offset (*_INST macro)
177 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
179 * Put a clockdomain referred to by (@inst, @cdoffs) into
180 * hardware-supervised idle mode. No return value.
182 void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
184 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
188 * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
189 * @inst: CM instance register offset (*_INST macro)
190 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
192 * Put a clockdomain referred to by (@inst, @cdoffs) into
193 * software-supervised idle mode, i.e., controlled manually by the
194 * Linux OMAP clockdomain code. No return value.
196 void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
198 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
202 * am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle
203 * @inst: CM instance register offset (*_INST macro)
204 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
206 * Put a clockdomain referred to by (@inst, @cdoffs) into idle
209 void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
211 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
215 * am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle
216 * @inst: CM instance register offset (*_INST macro)
217 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
219 * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
220 * waking it up. No return value.
222 void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
224 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
232 * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state
233 * @inst: CM instance register offset (*_INST macro)
234 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
235 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
237 * Wait for the module IDLEST to be functional. If the idle state is in any
238 * the non functional state (trans, idle or disabled), module and thus the
239 * sysconfig cannot be accessed and will probably lead to an "imprecise
242 int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
249 omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
250 MAX_MODULE_READY_TIME, i);
252 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
256 * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
258 * @inst: CM instance register offset (*_INST macro)
259 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
260 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
262 * Wait for the module IDLEST to be disabled. Some PRCM transition,
263 * like reset assertion or parent clock de-activation must wait the
264 * module to be fully disabled.
266 int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
273 omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) ==
274 CLKCTRL_IDLEST_DISABLED),
275 MAX_MODULE_READY_TIME, i);
277 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
281 * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL
282 * @mode: Module mode (SW or HW)
283 * @inst: CM instance register offset (*_INST macro)
284 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
285 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
289 void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
293 v = am33xx_cm_read_reg(inst, clkctrl_offs);
294 v &= ~AM33XX_MODULEMODE_MASK;
295 v |= mode << AM33XX_MODULEMODE_SHIFT;
296 am33xx_cm_write_reg(v, inst, clkctrl_offs);
300 * am33xx_cm_module_disable - Disable the module inside CLKCTRL
301 * @inst: CM instance register offset (*_INST macro)
302 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
303 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
307 void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
311 v = am33xx_cm_read_reg(inst, clkctrl_offs);
312 v &= ~AM33XX_MODULEMODE_MASK;
313 am33xx_cm_write_reg(v, inst, clkctrl_offs);
317 * Clockdomain low-level functions
320 static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
322 am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
326 static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
328 am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
332 static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
334 am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
337 static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
339 am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
342 static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
344 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
345 return am33xx_clkdm_wakeup(clkdm);
350 static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
354 hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
356 if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
357 am33xx_clkdm_sleep(clkdm);
362 struct clkdm_ops am33xx_clkdm_operations = {
363 .clkdm_sleep = am33xx_clkdm_sleep,
364 .clkdm_wakeup = am33xx_clkdm_wakeup,
365 .clkdm_allow_idle = am33xx_clkdm_allow_idle,
366 .clkdm_deny_idle = am33xx_clkdm_deny_idle,
367 .clkdm_clk_enable = am33xx_clkdm_clk_enable,
368 .clkdm_clk_disable = am33xx_clkdm_clk_disable,