4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
7 * Reference taken from from OMAP4 cminst44xx.c
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
27 #include "cm-regbits-34xx.h"
28 #include "cm-regbits-33xx.h"
32 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
34 * 0x0 func: Module is fully functional, including OCP
35 * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
37 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
38 * using separate functional clock
39 * 0x3 disabled: Module is disabled and cannot be accessed
42 #define CLKCTRL_IDLEST_FUNCTIONAL 0x0
43 #define CLKCTRL_IDLEST_INTRANSITION 0x1
44 #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
45 #define CLKCTRL_IDLEST_DISABLED 0x3
47 /* Private functions */
49 /* Read a register in a CM instance */
50 static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
52 return __raw_readl(cm_base + inst + idx);
55 /* Write into a register in a CM */
56 static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
58 __raw_writel(val, cm_base + inst + idx);
61 /* Read-modify-write a register in CM */
62 static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
66 v = am33xx_cm_read_reg(inst, idx);
69 am33xx_cm_write_reg(v, inst, idx);
74 static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx)
76 return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx);
79 static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx)
81 return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx);
84 static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
88 v = am33xx_cm_read_reg(inst, idx);
96 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
97 * @inst: CM instance register offset (*_INST macro)
98 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
99 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
101 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
104 static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
106 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
107 v &= AM33XX_IDLEST_MASK;
108 v >>= AM33XX_IDLEST_SHIFT;
113 * _is_module_ready - can module registers be accessed without causing an abort?
114 * @inst: CM instance register offset (*_INST macro)
115 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
116 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
118 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
119 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
121 static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
125 v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs);
127 return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
128 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
132 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
133 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
134 * @inst: CM instance register offset (*_INST macro)
135 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
137 * @c must be the unshifted value for CLKTRCTRL - i.e., this function
138 * will handle the shift itself.
140 static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
144 v = am33xx_cm_read_reg(inst, cdoffs);
145 v &= ~AM33XX_CLKTRCTRL_MASK;
146 v |= c << AM33XX_CLKTRCTRL_SHIFT;
147 am33xx_cm_write_reg(v, inst, cdoffs);
150 /* Public functions */
153 * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
154 * @inst: CM instance register offset (*_INST macro)
155 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
157 * Returns true if the clockdomain referred to by (@inst, @cdoffs)
158 * is in hardware-supervised idle mode, or 0 otherwise.
160 bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
164 v = am33xx_cm_read_reg(inst, cdoffs);
165 v &= AM33XX_CLKTRCTRL_MASK;
166 v >>= AM33XX_CLKTRCTRL_SHIFT;
168 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
172 * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
173 * @inst: CM instance register offset (*_INST macro)
174 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
176 * Put a clockdomain referred to by (@inst, @cdoffs) into
177 * hardware-supervised idle mode. No return value.
179 void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
181 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
185 * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
186 * @inst: CM instance register offset (*_INST macro)
187 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
189 * Put a clockdomain referred to by (@inst, @cdoffs) into
190 * software-supervised idle mode, i.e., controlled manually by the
191 * Linux OMAP clockdomain code. No return value.
193 void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
195 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
199 * am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle
200 * @inst: CM instance register offset (*_INST macro)
201 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
203 * Put a clockdomain referred to by (@inst, @cdoffs) into idle
206 void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
208 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
212 * am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle
213 * @inst: CM instance register offset (*_INST macro)
214 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
216 * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
217 * waking it up. No return value.
219 void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
221 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
229 * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state
230 * @inst: CM instance register offset (*_INST macro)
231 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
232 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
234 * Wait for the module IDLEST to be functional. If the idle state is in any
235 * the non functional state (trans, idle or disabled), module and thus the
236 * sysconfig cannot be accessed and will probably lead to an "imprecise
239 int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
246 omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
247 MAX_MODULE_READY_TIME, i);
249 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
253 * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
255 * @inst: CM instance register offset (*_INST macro)
256 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
257 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
259 * Wait for the module IDLEST to be disabled. Some PRCM transition,
260 * like reset assertion or parent clock de-activation must wait the
261 * module to be fully disabled.
263 int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
270 omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) ==
271 CLKCTRL_IDLEST_DISABLED),
272 MAX_MODULE_READY_TIME, i);
274 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
278 * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL
279 * @mode: Module mode (SW or HW)
280 * @inst: CM instance register offset (*_INST macro)
281 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
282 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
286 void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
290 v = am33xx_cm_read_reg(inst, clkctrl_offs);
291 v &= ~AM33XX_MODULEMODE_MASK;
292 v |= mode << AM33XX_MODULEMODE_SHIFT;
293 am33xx_cm_write_reg(v, inst, clkctrl_offs);
297 * am33xx_cm_module_disable - Disable the module inside CLKCTRL
298 * @inst: CM instance register offset (*_INST macro)
299 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
300 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
304 void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
308 v = am33xx_cm_read_reg(inst, clkctrl_offs);
309 v &= ~AM33XX_MODULEMODE_MASK;
310 am33xx_cm_write_reg(v, inst, clkctrl_offs);