arch/arm/mach-omap2/devices.c

   1 /*
   2  * linux/arch/arm/mach-omap2/devices.c
   3  *
   4  * OMAP2 platform device setup/initialization
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/io.h>
  17 #include <linux/clk.h>
  18
  19 #include <mach/hardware.h>
  20 #include <mach/irqs.h>
  21 #include <asm/mach-types.h>
  22 #include <asm/mach/map.h>
  23 #include <asm/pmu.h>
  24
  25 #include <plat/control.h>
  26 #include <plat/tc.h>
  27 #include <plat/board.h>
  28 #include <mach/gpio.h>
  29 #include <plat/mmc.h>
  30 #include <plat/dma.h>
  31
  32 #include "mux.h"
  33
  34 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
  35
  36 static struct resource cam_resources[] = {
  37         {
  38                 .start          = OMAP24XX_CAMERA_BASE,
  39                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
  40                 .flags          = IORESOURCE_MEM,
  41         },
  42         {
  43                 .start          = INT_24XX_CAM_IRQ,
  44                 .flags          = IORESOURCE_IRQ,
  45         }
  46 };
  47
  48 static struct platform_device omap_cam_device = {
  49         .name           = "omap24xxcam",
  50         .id             = -1,
  51         .num_resources  = ARRAY_SIZE(cam_resources),
  52         .resource       = cam_resources,
  53 };
  54
  55 static inline void omap_init_camera(void)
  56 {
  57         platform_device_register(&omap_cam_device);
  58 }
  59
  60 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
  61
  62 static struct resource omap3isp_resources[] = {
  63         {
  64                 .start          = OMAP3430_ISP_BASE,
  65                 .end            = OMAP3430_ISP_END,
  66                 .flags          = IORESOURCE_MEM,
  67         },
  68         {
  69                 .start          = OMAP3430_ISP_CBUFF_BASE,
  70                 .end            = OMAP3430_ISP_CBUFF_END,
  71                 .flags          = IORESOURCE_MEM,
  72         },
  73         {
  74                 .start          = OMAP3430_ISP_CCP2_BASE,
  75                 .end            = OMAP3430_ISP_CCP2_END,
  76                 .flags          = IORESOURCE_MEM,
  77         },
  78         {
  79                 .start          = OMAP3430_ISP_CCDC_BASE,
  80                 .end            = OMAP3430_ISP_CCDC_END,
  81                 .flags          = IORESOURCE_MEM,
  82         },
  83         {
  84                 .start          = OMAP3430_ISP_HIST_BASE,
  85                 .end            = OMAP3430_ISP_HIST_END,
  86                 .flags          = IORESOURCE_MEM,
  87         },
  88         {
  89                 .start          = OMAP3430_ISP_H3A_BASE,
  90                 .end            = OMAP3430_ISP_H3A_END,
  91                 .flags          = IORESOURCE_MEM,
  92         },
  93         {
  94                 .start          = OMAP3430_ISP_PREV_BASE,
  95                 .end            = OMAP3430_ISP_PREV_END,
  96                 .flags          = IORESOURCE_MEM,
  97         },
  98         {
  99                 .start          = OMAP3430_ISP_RESZ_BASE,
 100                 .end            = OMAP3430_ISP_RESZ_END,
 101                 .flags          = IORESOURCE_MEM,
 102         },
 103         {
 104                 .start          = OMAP3430_ISP_SBL_BASE,
 105                 .end            = OMAP3430_ISP_SBL_END,
 106                 .flags          = IORESOURCE_MEM,
 107         },
 108         {
 109                 .start          = OMAP3430_ISP_CSI2A_BASE,
 110                 .end            = OMAP3430_ISP_CSI2A_END,
 111                 .flags          = IORESOURCE_MEM,
 112         },
 113         {
 114                 .start          = OMAP3430_ISP_CSI2PHY_BASE,
 115                 .end            = OMAP3430_ISP_CSI2PHY_END,
 116                 .flags          = IORESOURCE_MEM,
 117         },
 118         {
 119                 .start          = INT_34XX_CAM_IRQ,
 120                 .flags          = IORESOURCE_IRQ,
 121         }
 122 };
 123
 124 static struct platform_device omap3isp_device = {
 125         .name           = "omap3isp",
 126         .id             = -1,
 127         .num_resources  = ARRAY_SIZE(omap3isp_resources),
 128         .resource       = omap3isp_resources,
 129 };
 130
 131 static inline void omap_init_camera(void)
 132 {
 133         platform_device_register(&omap3isp_device);
 134 }
 135 #else
 136 static inline void omap_init_camera(void)
 137 {
 138 }
 139 #endif
 140
 141 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
 142
 143 #define MBOX_REG_SIZE   0x120
 144
 145 #ifdef CONFIG_ARCH_OMAP2
 146 static struct resource omap2_mbox_resources[] = {
 147         {
 148                 .start          = OMAP24XX_MAILBOX_BASE,
 149                 .end            = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
 150                 .flags          = IORESOURCE_MEM,
 151         },
 152         {
 153                 .start          = INT_24XX_MAIL_U0_MPU,
 154                 .flags          = IORESOURCE_IRQ,
 155         },
 156         {
 157                 .start          = INT_24XX_MAIL_U3_MPU,
 158                 .flags          = IORESOURCE_IRQ,
 159         },
 160 };
 161 static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
 162 #else
 163 #define omap2_mbox_resources            NULL
 164 #define omap2_mbox_resources_sz         0
 165 #endif
 166
 167 #ifdef CONFIG_ARCH_OMAP3
 168 static struct resource omap3_mbox_resources[] = {
 169         {
 170                 .start          = OMAP34XX_MAILBOX_BASE,
 171                 .end            = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
 172                 .flags          = IORESOURCE_MEM,
 173         },
 174         {
 175                 .start          = INT_24XX_MAIL_U0_MPU,
 176                 .flags          = IORESOURCE_IRQ,
 177         },
 178 };
 179 static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
 180 #else
 181 #define omap3_mbox_resources            NULL
 182 #define omap3_mbox_resources_sz         0
 183 #endif
 184
 185 #ifdef CONFIG_ARCH_OMAP4
 186
 187 #define OMAP4_MBOX_REG_SIZE     0x130
 188 static struct resource omap4_mbox_resources[] = {
 189         {
 190                 .start          = OMAP44XX_MAILBOX_BASE,
 191                 .end            = OMAP44XX_MAILBOX_BASE +
 192                                         OMAP4_MBOX_REG_SIZE - 1,
 193                 .flags          = IORESOURCE_MEM,
 194         },
 195         {
 196                 .start          = OMAP44XX_IRQ_MAIL_U0,
 197                 .flags          = IORESOURCE_IRQ,
 198         },
 199 };
 200 static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
 201 #else
 202 #define omap4_mbox_resources            NULL
 203 #define omap4_mbox_resources_sz         0
 204 #endif
 205
 206 static struct platform_device mbox_device = {
 207         .name           = "omap2-mailbox",
 208         .id             = -1,
 209 };
 210
 211 static inline void omap_init_mbox(void)
 212 {
 213         if (cpu_is_omap24xx()) {
 214                 mbox_device.resource = omap2_mbox_resources;
 215                 mbox_device.num_resources = omap2_mbox_resources_sz;
 216         } else if (cpu_is_omap34xx()) {
 217                 mbox_device.resource = omap3_mbox_resources;
 218                 mbox_device.num_resources = omap3_mbox_resources_sz;
 219         } else if (cpu_is_omap44xx()) {
 220                 mbox_device.resource = omap4_mbox_resources;
 221                 mbox_device.num_resources = omap4_mbox_resources_sz;
 222         } else {
 223                 pr_err("%s: platform not supported\n", __func__);
 224                 return;
 225         }
 226         platform_device_register(&mbox_device);
 227 }
 228 #else
 229 static inline void omap_init_mbox(void) { }
 230 #endif /* CONFIG_OMAP_MBOX_FWK */
 231
 232 static inline void omap_init_sti(void) {}
 233
 234 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 235
 236 #include <plat/mcspi.h>
 237
 238 #define OMAP2_MCSPI1_BASE               0x48098000
 239 #define OMAP2_MCSPI2_BASE               0x4809a000
 240 #define OMAP2_MCSPI3_BASE               0x480b8000
 241 #define OMAP2_MCSPI4_BASE               0x480ba000
 242
 243 #define OMAP4_MCSPI1_BASE               0x48098100
 244 #define OMAP4_MCSPI2_BASE               0x4809a100
 245 #define OMAP4_MCSPI3_BASE               0x480b8100
 246 #define OMAP4_MCSPI4_BASE               0x480ba100
 247
 248 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
 249         .num_cs         = 4,
 250 };
 251
 252 static struct resource omap2_mcspi1_resources[] = {
 253         {
 254                 .start          = OMAP2_MCSPI1_BASE,
 255                 .end            = OMAP2_MCSPI1_BASE + 0xff,
 256                 .flags          = IORESOURCE_MEM,
 257         },
 258 };
 259
 260 static struct platform_device omap2_mcspi1 = {
 261         .name           = "omap2_mcspi",
 262         .id             = 1,
 263         .num_resources  = ARRAY_SIZE(omap2_mcspi1_resources),
 264         .resource       = omap2_mcspi1_resources,
 265         .dev            = {
 266                 .platform_data = &omap2_mcspi1_config,
 267         },
 268 };
 269
 270 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
 271         .num_cs         = 2,
 272 };
 273
 274 static struct resource omap2_mcspi2_resources[] = {
 275         {
 276                 .start          = OMAP2_MCSPI2_BASE,
 277                 .end            = OMAP2_MCSPI2_BASE + 0xff,
 278                 .flags          = IORESOURCE_MEM,
 279         },
 280 };
 281
 282 static struct platform_device omap2_mcspi2 = {
 283         .name           = "omap2_mcspi",
 284         .id             = 2,
 285         .num_resources  = ARRAY_SIZE(omap2_mcspi2_resources),
 286         .resource       = omap2_mcspi2_resources,
 287         .dev            = {
 288                 .platform_data = &omap2_mcspi2_config,
 289         },
 290 };
 291
 292 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
 293         defined(CONFIG_ARCH_OMAP4)
 294 static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
 295         .num_cs         = 2,
 296 };
 297
 298 static struct resource omap2_mcspi3_resources[] = {
 299         {
 300         .start          = OMAP2_MCSPI3_BASE,
 301         .end            = OMAP2_MCSPI3_BASE + 0xff,
 302         .flags          = IORESOURCE_MEM,
 303         },
 304 };
 305
 306 static struct platform_device omap2_mcspi3 = {
 307         .name           = "omap2_mcspi",
 308         .id             = 3,
 309         .num_resources  = ARRAY_SIZE(omap2_mcspi3_resources),
 310         .resource       = omap2_mcspi3_resources,
 311         .dev            = {
 312                 .platform_data = &omap2_mcspi3_config,
 313         },
 314 };
 315 #endif
 316
 317 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 318 static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
 319         .num_cs         = 1,
 320 };
 321
 322 static struct resource omap2_mcspi4_resources[] = {
 323         {
 324                 .start          = OMAP2_MCSPI4_BASE,
 325                 .end            = OMAP2_MCSPI4_BASE + 0xff,
 326                 .flags          = IORESOURCE_MEM,
 327         },
 328 };
 329
 330 static struct platform_device omap2_mcspi4 = {
 331         .name           = "omap2_mcspi",
 332         .id             = 4,
 333         .num_resources  = ARRAY_SIZE(omap2_mcspi4_resources),
 334         .resource       = omap2_mcspi4_resources,
 335         .dev            = {
 336                 .platform_data = &omap2_mcspi4_config,
 337         },
 338 };
 339 #endif
 340
 341 #ifdef CONFIG_ARCH_OMAP4
 342 static inline void omap4_mcspi_fixup(void)
 343 {
 344         omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
 345         omap2_mcspi1_resources[0].end   = OMAP4_MCSPI1_BASE + 0xff;
 346         omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
 347         omap2_mcspi2_resources[0].end   = OMAP4_MCSPI2_BASE + 0xff;
 348         omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
 349         omap2_mcspi3_resources[0].end   = OMAP4_MCSPI3_BASE + 0xff;
 350         omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
 351         omap2_mcspi4_resources[0].end   = OMAP4_MCSPI4_BASE + 0xff;
 352 }
 353 #else
 354 static inline void omap4_mcspi_fixup(void)
 355 {
 356 }
 357 #endif
 358
 359 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
 360         defined(CONFIG_ARCH_OMAP4)
 361 static inline void omap2_mcspi3_init(void)
 362 {
 363         platform_device_register(&omap2_mcspi3);
 364 }
 365 #else
 366 static inline void omap2_mcspi3_init(void)
 367 {
 368 }
 369 #endif
 370
 371 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 372 static inline void omap2_mcspi4_init(void)
 373 {
 374         platform_device_register(&omap2_mcspi4);
 375 }
 376 #else
 377 static inline void omap2_mcspi4_init(void)
 378 {
 379 }
 380 #endif
 381
 382 static void omap_init_mcspi(void)
 383 {
 384         if (cpu_is_omap44xx())
 385                 omap4_mcspi_fixup();
 386
 387         platform_device_register(&omap2_mcspi1);
 388         platform_device_register(&omap2_mcspi2);
 389
 390         if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
 391                 omap2_mcspi3_init();
 392
 393         if (cpu_is_omap343x() || cpu_is_omap44xx())
 394                 omap2_mcspi4_init();
 395 }
 396
 397 #else
 398 static inline void omap_init_mcspi(void) {}
 399 #endif
 400
 401 static struct resource omap2_pmu_resource = {
 402         .start  = 3,
 403         .end    = 3,
 404         .flags  = IORESOURCE_IRQ,
 405 };
 406
 407 static struct resource omap3_pmu_resource = {
 408         .start  = INT_34XX_BENCH_MPU_EMUL,
 409         .end    = INT_34XX_BENCH_MPU_EMUL,
 410         .flags  = IORESOURCE_IRQ,
 411 };
 412
 413 static struct platform_device omap_pmu_device = {
 414         .name           = "arm-pmu",
 415         .id             = ARM_PMU_DEVICE_CPU,
 416         .num_resources  = 1,
 417 };
 418
 419 static void omap_init_pmu(void)
 420 {
 421         if (cpu_is_omap24xx())
 422                 omap_pmu_device.resource = &omap2_pmu_resource;
 423         else if (cpu_is_omap34xx())
 424                 omap_pmu_device.resource = &omap3_pmu_resource;
 425         else
 426                 return;
 427
 428         platform_device_register(&omap_pmu_device);
 429 }
 430
 431
 432 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
 433
 434 #ifdef CONFIG_ARCH_OMAP2
 435 static struct resource omap2_sham_resources[] = {
 436         {
 437                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
 438                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
 439                 .flags  = IORESOURCE_MEM,
 440         },
 441         {
 442                 .start  = INT_24XX_SHA1MD5,
 443                 .flags  = IORESOURCE_IRQ,
 444         }
 445 };
 446 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
 447 #else
 448 #define omap2_sham_resources            NULL
 449 #define omap2_sham_resources_sz         0
 450 #endif
 451
 452 #ifdef CONFIG_ARCH_OMAP3
 453 static struct resource omap3_sham_resources[] = {
 454         {
 455                 .start  = OMAP34XX_SEC_SHA1MD5_BASE,
 456                 .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
 457                 .flags  = IORESOURCE_MEM,
 458         },
 459         {
 460                 .start  = INT_34XX_SHA1MD52_IRQ,
 461                 .flags  = IORESOURCE_IRQ,
 462         },
 463         {
 464                 .start  = OMAP34XX_DMA_SHA1MD5_RX,
 465                 .flags  = IORESOURCE_DMA,
 466         }
 467 };
 468 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
 469 #else
 470 #define omap3_sham_resources            NULL
 471 #define omap3_sham_resources_sz         0
 472 #endif
 473
 474 static struct platform_device sham_device = {
 475         .name           = "omap-sham",
 476         .id             = -1,
 477 };
 478
 479 static void omap_init_sham(void)
 480 {
 481         if (cpu_is_omap24xx()) {
 482                 sham_device.resource = omap2_sham_resources;
 483                 sham_device.num_resources = omap2_sham_resources_sz;
 484         } else if (cpu_is_omap34xx()) {
 485                 sham_device.resource = omap3_sham_resources;
 486                 sham_device.num_resources = omap3_sham_resources_sz;
 487         } else {
 488                 pr_err("%s: platform not supported\n", __func__);
 489                 return;
 490         }
 491         platform_device_register(&sham_device);
 492 }
 493 #else
 494 static inline void omap_init_sham(void) { }
 495 #endif
 496
 497 /*-------------------------------------------------------------------------*/
 498
 499 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 500
 501 #define MMCHS_SYSCONFIG                 0x0010
 502 #define MMCHS_SYSCONFIG_SWRESET         (1 << 1)
 503 #define MMCHS_SYSSTATUS                 0x0014
 504 #define MMCHS_SYSSTATUS_RESETDONE       (1 << 0)
 505
 506 static struct platform_device dummy_pdev = {
 507         .dev = {
 508                 .bus = &platform_bus_type,
 509         },
 510 };
 511
 512 /**
 513  * omap_hsmmc_reset() - Full reset of each HS-MMC controller
 514  *
 515  * Ensure that each MMC controller is fully reset.  Controllers
 516  * left in an unknown state (by bootloader) may prevent retention
 517  * or OFF-mode.  This is especially important in cases where the
 518  * MMC driver is not enabled, _or_ built as a module.
 519  *
 520  * In order for reset to work, interface, functional and debounce
 521  * clocks must be enabled.  The debounce clock comes from func_32k_clk
 522  * and is not under SW control, so we only enable i- and f-clocks.
 523  **/
 524 static void __init omap_hsmmc_reset(void)
 525 {
 526         u32 i, nr_controllers;
 527
 528         if (cpu_is_omap242x())
 529                 return;
 530
 531         nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
 532                 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
 533
 534         for (i = 0; i < nr_controllers; i++) {
 535                 u32 v, base = 0;
 536                 struct clk *iclk, *fclk;
 537                 struct device *dev = &dummy_pdev.dev;
 538
 539                 switch (i) {
 540                 case 0:
 541                         base = OMAP2_MMC1_BASE;
 542                         break;
 543                 case 1:
 544                         base = OMAP2_MMC2_BASE;
 545                         break;
 546                 case 2:
 547                         base = OMAP3_MMC3_BASE;
 548                         break;
 549                 case 3:
 550                         if (!cpu_is_omap44xx())
 551                                 return;
 552                         base = OMAP4_MMC4_BASE;
 553                         break;
 554                 case 4:
 555                         if (!cpu_is_omap44xx())
 556                                 return;
 557                         base = OMAP4_MMC5_BASE;
 558                         break;
 559                 }
 560
 561                 if (cpu_is_omap44xx())
 562                         base += OMAP4_MMC_REG_OFFSET;
 563
 564                 dummy_pdev.id = i;
 565                 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
 566                 iclk = clk_get(dev, "ick");
 567                 if (iclk && clk_enable(iclk))
 568                         iclk = NULL;
 569
 570                 fclk = clk_get(dev, "fck");
 571                 if (fclk && clk_enable(fclk))
 572                         fclk = NULL;
 573
 574                 if (!iclk || !fclk) {
 575                         printk(KERN_WARNING
 576                                "%s: Unable to enable clocks for MMC%d, "
 577                                "cannot reset.\n",  __func__, i);
 578                         break;
 579                 }
 580
 581                 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
 582                 v = omap_readl(base + MMCHS_SYSSTATUS);
 583                 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
 584                          MMCHS_SYSSTATUS_RESETDONE))
 585                         cpu_relax();
 586
 587                 if (fclk) {
 588                         clk_disable(fclk);
 589                         clk_put(fclk);
 590                 }
 591                 if (iclk) {
 592                         clk_disable(iclk);
 593                         clk_put(iclk);
 594                 }
 595         }
 596 }
 597 #else
 598 static inline void omap_hsmmc_reset(void) {}
 599 #endif
 600
 601 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
 602         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 603
 604 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
 605                         int controller_nr)
 606 {
 607         if ((mmc_controller->slots[0].switch_pin > 0) && \
 608                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
 609                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
 610                                         OMAP_PIN_INPUT_PULLUP);
 611         if ((mmc_controller->slots[0].gpio_wp > 0) && \
 612                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
 613                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
 614                                         OMAP_PIN_INPUT_PULLUP);
 615
 616         if (cpu_is_omap2420() && controller_nr == 0) {
 617                 omap_mux_init_signal("sdmmc_cmd", 0);
 618                 omap_mux_init_signal("sdmmc_clki", 0);
 619                 omap_mux_init_signal("sdmmc_clko", 0);
 620                 omap_mux_init_signal("sdmmc_dat0", 0);
 621                 omap_mux_init_signal("sdmmc_dat_dir0", 0);
 622                 omap_mux_init_signal("sdmmc_cmd_dir", 0);
 623                 if (mmc_controller->slots[0].wires == 4) {
 624                         omap_mux_init_signal("sdmmc_dat1", 0);
 625                         omap_mux_init_signal("sdmmc_dat2", 0);
 626                         omap_mux_init_signal("sdmmc_dat3", 0);
 627                         omap_mux_init_signal("sdmmc_dat_dir1", 0);
 628                         omap_mux_init_signal("sdmmc_dat_dir2", 0);
 629                         omap_mux_init_signal("sdmmc_dat_dir3", 0);
 630                 }
 631
 632                 /*
 633                  * Use internal loop-back in MMC/SDIO Module Input Clock
 634                  * selection
 635                  */
 636                 if (mmc_controller->slots[0].internal_clock) {
 637                         u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 638                         v |= (1 << 24);
 639                         omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 640                 }
 641         }
 642
 643         if (cpu_is_omap34xx()) {
 644                 if (controller_nr == 0) {
 645                         omap_mux_init_signal("sdmmc1_clk",
 646                                 OMAP_PIN_INPUT_PULLUP);
 647                         omap_mux_init_signal("sdmmc1_cmd",
 648                                 OMAP_PIN_INPUT_PULLUP);
 649                         omap_mux_init_signal("sdmmc1_dat0",
 650                                 OMAP_PIN_INPUT_PULLUP);
 651                         if (mmc_controller->slots[0].wires == 4 ||
 652                                 mmc_controller->slots[0].wires == 8) {
 653                                 omap_mux_init_signal("sdmmc1_dat1",
 654                                         OMAP_PIN_INPUT_PULLUP);
 655                                 omap_mux_init_signal("sdmmc1_dat2",
 656                                         OMAP_PIN_INPUT_PULLUP);
 657                                 omap_mux_init_signal("sdmmc1_dat3",
 658                                         OMAP_PIN_INPUT_PULLUP);
 659                         }
 660                         if (mmc_controller->slots[0].wires == 8) {
 661                                 omap_mux_init_signal("sdmmc1_dat4",
 662                                         OMAP_PIN_INPUT_PULLUP);
 663                                 omap_mux_init_signal("sdmmc1_dat5",
 664                                         OMAP_PIN_INPUT_PULLUP);
 665                                 omap_mux_init_signal("sdmmc1_dat6",
 666                                         OMAP_PIN_INPUT_PULLUP);
 667                                 omap_mux_init_signal("sdmmc1_dat7",
 668                                         OMAP_PIN_INPUT_PULLUP);
 669                         }
 670                 }
 671                 if (controller_nr == 1) {
 672                         /* MMC2 */
 673                         omap_mux_init_signal("sdmmc2_clk",
 674                                 OMAP_PIN_INPUT_PULLUP);
 675                         omap_mux_init_signal("sdmmc2_cmd",
 676                                 OMAP_PIN_INPUT_PULLUP);
 677                         omap_mux_init_signal("sdmmc2_dat0",
 678                                 OMAP_PIN_INPUT_PULLUP);
 679
 680                         /*
 681                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
 682                          * in the board-*.c files
 683                          */
 684                         if (mmc_controller->slots[0].wires == 4 ||
 685                                 mmc_controller->slots[0].wires == 8) {
 686                                 omap_mux_init_signal("sdmmc2_dat1",
 687                                         OMAP_PIN_INPUT_PULLUP);
 688                                 omap_mux_init_signal("sdmmc2_dat2",
 689                                         OMAP_PIN_INPUT_PULLUP);
 690                                 omap_mux_init_signal("sdmmc2_dat3",
 691                                         OMAP_PIN_INPUT_PULLUP);
 692                         }
 693                         if (mmc_controller->slots[0].wires == 8) {
 694                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
 695                                         OMAP_PIN_INPUT_PULLUP);
 696                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
 697                                         OMAP_PIN_INPUT_PULLUP);
 698                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
 699                                         OMAP_PIN_INPUT_PULLUP);
 700                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
 701                                         OMAP_PIN_INPUT_PULLUP);
 702                         }
 703                 }
 704
 705                 /*
 706                  * For MMC3 the pins need to be muxed in the board-*.c files
 707                  */
 708         }
 709 }
 710
 711 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
 712                         int nr_controllers)
 713 {
 714         int i;
 715         char *name;
 716
 717         for (i = 0; i < nr_controllers; i++) {
 718                 unsigned long base, size;
 719                 unsigned int irq = 0;
 720
 721                 if (!mmc_data[i])
 722                         continue;
 723
 724                 omap2_mmc_mux(mmc_data[i], i);
 725
 726                 switch (i) {
 727                 case 0:
 728                         base = OMAP2_MMC1_BASE;
 729                         irq = INT_24XX_MMC_IRQ;
 730                         break;
 731                 case 1:
 732                         base = OMAP2_MMC2_BASE;
 733                         irq = INT_24XX_MMC2_IRQ;
 734                         break;
 735                 case 2:
 736                         if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
 737                                 return;
 738                         base = OMAP3_MMC3_BASE;
 739                         irq = INT_34XX_MMC3_IRQ;
 740                         break;
 741                 case 3:
 742                         if (!cpu_is_omap44xx())
 743                                 return;
 744                         base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
 745                         irq = OMAP44XX_IRQ_MMC4;
 746                         break;
 747                 case 4:
 748                         if (!cpu_is_omap44xx())
 749                                 return;
 750                         base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
 751                         irq = OMAP44XX_IRQ_MMC5;
 752                         break;
 753                 default:
 754                         continue;
 755                 }
 756
 757                 if (cpu_is_omap2420()) {
 758                         size = OMAP2420_MMC_SIZE;
 759                         name = "mmci-omap";
 760                 } else if (cpu_is_omap44xx()) {
 761                         if (i < 3) {
 762                                 base += OMAP4_MMC_REG_OFFSET;
 763                                 irq += OMAP44XX_IRQ_GIC_START;
 764                         }
 765                         size = OMAP4_HSMMC_SIZE;
 766                         name = "mmci-omap-hs";
 767                 } else {
 768                         size = OMAP3_HSMMC_SIZE;
 769                         name = "mmci-omap-hs";
 770                 }
 771                 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
 772         };
 773 }
 774
 775 #endif
 776
 777 /*-------------------------------------------------------------------------*/
 778
 779 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
 780 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
 781 #define OMAP_HDQ_BASE   0x480B2000
 782 #endif
 783 static struct resource omap_hdq_resources[] = {
 784         {
 785                 .start          = OMAP_HDQ_BASE,
 786                 .end            = OMAP_HDQ_BASE + 0x1C,
 787                 .flags          = IORESOURCE_MEM,
 788         },
 789         {
 790                 .start          = INT_24XX_HDQ_IRQ,
 791                 .flags          = IORESOURCE_IRQ,
 792         },
 793 };
 794 static struct platform_device omap_hdq_dev = {
 795         .name = "omap_hdq",
 796         .id = 0,
 797         .dev = {
 798                 .platform_data = NULL,
 799         },
 800         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
 801         .resource       = omap_hdq_resources,
 802 };
 803 static inline void omap_hdq_init(void)
 804 {
 805         (void) platform_device_register(&omap_hdq_dev);
 806 }
 807 #else
 808 static inline void omap_hdq_init(void) {}
 809 #endif
 810
 811 /*---------------------------------------------------------------------------*/
 812
 813 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
 814         defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
 815 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
 816 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
 817 };
 818 #else
 819 static struct resource omap_vout_resource[2] = {
 820 };
 821 #endif
 822
 823 static struct platform_device omap_vout_device = {
 824         .name           = "omap_vout",
 825         .num_resources  = ARRAY_SIZE(omap_vout_resource),
 826         .resource       = &omap_vout_resource[0],
 827         .id             = -1,
 828 };
 829 static void omap_init_vout(void)
 830 {
 831         if (platform_device_register(&omap_vout_device) < 0)
 832                 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
 833 }
 834 #else
 835 static inline void omap_init_vout(void) {}
 836 #endif
 837
 838 /*-------------------------------------------------------------------------*/
 839
 840 static int __init omap2_init_devices(void)
 841 {
 842         /* please keep these calls, and their implementations above,
 843          * in alphabetical order so they're easier to sort through.
 844          */
 845         omap_hsmmc_reset();
 846         omap_init_camera();
 847         omap_init_mbox();
 848         omap_init_mcspi();
 849         omap_init_pmu();
 850         omap_hdq_init();
 851         omap_init_sti();
 852         omap_init_sham();
 853         omap_init_vout();
 854
 855         return 0;
 856 }
 857 arch_initcall(omap2_init_devices);