2 * OMAP2plus display device setup / initialization.
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25 #include <linux/delay.h>
27 #include <linux/of_platform.h>
28 #include <linux/slab.h>
30 #include <video/omapdss.h>
31 #include "omap_hwmod.h"
32 #include "omap_device.h"
42 #define DISPC_CONTROL 0x0040
43 #define DISPC_CONTROL2 0x0238
44 #define DISPC_CONTROL3 0x0848
45 #define DISPC_IRQSTATUS 0x0018
47 #define DSS_SYSCONFIG 0x10
48 #define DSS_SYSSTATUS 0x14
49 #define DSS_CONTROL 0x40
50 #define DSS_SDI_CONTROL 0x44
51 #define DSS_PLL_CONTROL 0x48
53 #define LCD_EN_MASK (0x1 << 0)
54 #define DIGIT_EN_MASK (0x1 << 1)
56 #define FRAMEDONE_IRQ_SHIFT 0
57 #define EVSYNC_EVEN_IRQ_SHIFT 2
58 #define EVSYNC_ODD_IRQ_SHIFT 3
59 #define FRAMEDONE2_IRQ_SHIFT 22
60 #define FRAMEDONE3_IRQ_SHIFT 30
61 #define FRAMEDONETV_IRQ_SHIFT 24
64 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
65 * reset before deciding that something has gone wrong
67 #define FRAMEDONE_IRQ_TIMEOUT 100
69 static struct platform_device omap_display_device = {
73 .platform_data = NULL,
77 struct omap_dss_hwmod_data {
83 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
84 { "dss_core", "omapdss_dss", -1 },
85 { "dss_dispc", "omapdss_dispc", -1 },
86 { "dss_rfbi", "omapdss_rfbi", -1 },
87 { "dss_venc", "omapdss_venc", -1 },
90 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
91 { "dss_core", "omapdss_dss", -1 },
92 { "dss_dispc", "omapdss_dispc", -1 },
93 { "dss_rfbi", "omapdss_rfbi", -1 },
94 { "dss_venc", "omapdss_venc", -1 },
95 { "dss_dsi1", "omapdss_dsi", 0 },
98 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
99 { "dss_core", "omapdss_dss", -1 },
100 { "dss_dispc", "omapdss_dispc", -1 },
101 { "dss_rfbi", "omapdss_rfbi", -1 },
102 { "dss_dsi1", "omapdss_dsi", 0 },
103 { "dss_dsi2", "omapdss_dsi", 1 },
104 { "dss_hdmi", "omapdss_hdmi", -1 },
107 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
109 u32 enable_mask, enable_shift;
110 u32 pipd_mask, pipd_shift;
114 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
115 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
116 pipd_mask = OMAP4_DSI1_PIPD_MASK;
117 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
118 } else if (dsi_id == 1) {
119 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
120 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
121 pipd_mask = OMAP4_DSI2_PIPD_MASK;
122 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
127 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
132 reg |= (lanes << enable_shift) & enable_mask;
133 reg |= (lanes << pipd_shift) & pipd_mask;
135 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
140 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
142 if (cpu_is_omap44xx())
143 return omap4_dsi_mux_pads(dsi_id, lane_mask);
148 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
150 if (cpu_is_omap44xx())
151 omap4_dsi_mux_pads(dsi_id, 0);
154 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
156 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
159 static struct platform_device *create_dss_pdev(const char *pdev_name,
160 int pdev_id, const char *oh_name, void *pdata, int pdata_len,
161 struct platform_device *parent)
163 struct platform_device *pdev;
164 struct omap_device *od;
165 struct omap_hwmod *ohs[1];
166 struct omap_hwmod *oh;
169 oh = omap_hwmod_lookup(oh_name);
171 pr_err("Could not look up %s\n", oh_name);
176 pdev = platform_device_alloc(pdev_name, pdev_id);
178 pr_err("Could not create pdev for %s\n", pdev_name);
184 pdev->dev.parent = &parent->dev;
187 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
189 dev_set_name(&pdev->dev, "%s", pdev->name);
192 od = omap_device_alloc(pdev, ohs, 1);
194 pr_err("Could not alloc omap_device for %s\n", pdev_name);
199 r = platform_device_add_data(pdev, pdata, pdata_len);
201 pr_err("Could not set pdata for %s\n", pdev_name);
205 r = omap_device_register(pdev);
207 pr_err("Could not register omap_device for %s\n", pdev_name);
217 static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
218 int pdev_id, void *pdata, int pdata_len,
219 struct platform_device *parent)
221 struct platform_device *pdev;
224 pdev = platform_device_alloc(pdev_name, pdev_id);
226 pr_err("Could not create pdev for %s\n", pdev_name);
232 pdev->dev.parent = &parent->dev;
235 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
237 dev_set_name(&pdev->dev, "%s", pdev->name);
239 r = platform_device_add_data(pdev, pdata, pdata_len);
241 pr_err("Could not set pdata for %s\n", pdev_name);
245 r = platform_device_add(pdev);
247 pr_err("Could not register platform_device for %s\n", pdev_name);
257 static enum omapdss_version __init omap_display_get_version(void)
259 if (cpu_is_omap24xx())
260 return OMAPDSS_VER_OMAP24xx;
261 else if (cpu_is_omap3630())
262 return OMAPDSS_VER_OMAP3630;
263 else if (cpu_is_omap34xx()) {
264 if (soc_is_am35xx()) {
265 return OMAPDSS_VER_AM35xx;
267 if (omap_rev() < OMAP3430_REV_ES3_0)
268 return OMAPDSS_VER_OMAP34xx_ES1;
270 return OMAPDSS_VER_OMAP34xx_ES3;
272 } else if (omap_rev() == OMAP4430_REV_ES1_0)
273 return OMAPDSS_VER_OMAP4430_ES1;
274 else if (omap_rev() == OMAP4430_REV_ES2_0 ||
275 omap_rev() == OMAP4430_REV_ES2_1 ||
276 omap_rev() == OMAP4430_REV_ES2_2)
277 return OMAPDSS_VER_OMAP4430_ES2;
278 else if (cpu_is_omap44xx())
279 return OMAPDSS_VER_OMAP4;
280 else if (soc_is_omap54xx())
281 return OMAPDSS_VER_OMAP5;
283 return OMAPDSS_VER_UNKNOWN;
286 int __init omap_display_init(struct omap_dss_board_info *board_data)
289 struct platform_device *pdev;
291 const struct omap_dss_hwmod_data *curr_dss_hwmod;
292 struct platform_device *dss_pdev;
293 enum omapdss_version ver;
295 /* create omapdss device */
297 ver = omap_display_get_version();
299 if (ver == OMAPDSS_VER_UNKNOWN) {
300 pr_err("DSS not supported on this SoC\n");
304 board_data->version = ver;
305 board_data->dsi_enable_pads = omap_dsi_enable_pads;
306 board_data->dsi_disable_pads = omap_dsi_disable_pads;
307 board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
309 omap_display_device.dev.platform_data = board_data;
311 r = platform_device_register(&omap_display_device);
313 pr_err("Unable to register omapdss device\n");
317 /* create devices for dss hwmods */
319 if (cpu_is_omap24xx()) {
320 curr_dss_hwmod = omap2_dss_hwmod_data;
321 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
322 } else if (cpu_is_omap34xx()) {
323 curr_dss_hwmod = omap3_dss_hwmod_data;
324 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
326 curr_dss_hwmod = omap4_dss_hwmod_data;
327 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
331 * First create the pdev for dss_core, which is used as a parent device
332 * by the other dss pdevs. Note: dss_core has to be the first item in
335 dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
336 curr_dss_hwmod[0].id,
337 curr_dss_hwmod[0].oh_name,
338 board_data, sizeof(*board_data),
341 if (IS_ERR(dss_pdev)) {
342 pr_err("Could not build omap_device for %s\n",
343 curr_dss_hwmod[0].oh_name);
345 return PTR_ERR(dss_pdev);
348 for (i = 1; i < oh_count; i++) {
349 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
350 curr_dss_hwmod[i].id,
351 curr_dss_hwmod[i].oh_name,
352 board_data, sizeof(*board_data),
356 pr_err("Could not build omap_device for %s\n",
357 curr_dss_hwmod[i].oh_name);
359 return PTR_ERR(pdev);
363 /* Create devices for DPI and SDI */
365 pdev = create_simple_dss_pdev("omapdss_dpi", 0,
366 board_data, sizeof(*board_data), dss_pdev);
368 pr_err("Could not build platform_device for omapdss_dpi\n");
369 return PTR_ERR(pdev);
372 if (cpu_is_omap34xx()) {
373 pdev = create_simple_dss_pdev("omapdss_sdi", 0,
374 board_data, sizeof(*board_data), dss_pdev);
376 pr_err("Could not build platform_device for omapdss_sdi\n");
377 return PTR_ERR(pdev);
381 /* create DRM device */
384 pr_err("Unable to register omapdrm device\n");
388 /* create vrfb device */
389 r = omap_init_vrfb();
391 pr_err("Unable to register omapvrfb device\n");
395 /* create FB device */
398 pr_err("Unable to register omapfb device\n");
402 /* create V4L2 display device */
403 r = omap_init_vout();
405 pr_err("Unable to register omap_vout device\n");
412 static void dispc_disable_outputs(void)
415 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
417 struct omap_dss_dispc_dev_attr *da;
418 struct omap_hwmod *oh;
420 oh = omap_hwmod_lookup("dss_dispc");
422 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
427 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
431 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
433 /* store value of LCDENABLE and DIGITENABLE bits */
434 v = omap_hwmod_read(oh, DISPC_CONTROL);
435 lcd_en = v & LCD_EN_MASK;
436 digit_en = v & DIGIT_EN_MASK;
438 /* store value of LCDENABLE for LCD2 */
439 if (da->manager_count > 2) {
440 v = omap_hwmod_read(oh, DISPC_CONTROL2);
441 lcd2_en = v & LCD_EN_MASK;
444 /* store value of LCDENABLE for LCD3 */
445 if (da->manager_count > 3) {
446 v = omap_hwmod_read(oh, DISPC_CONTROL3);
447 lcd3_en = v & LCD_EN_MASK;
450 if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
451 return; /* no managers currently enabled */
454 * If any manager was enabled, we need to disable it before
455 * DSS clocks are disabled or DISPC module is reset
458 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
461 if (da->has_framedonetv_irq) {
462 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
464 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
465 1 << EVSYNC_ODD_IRQ_SHIFT;
470 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
472 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
475 * clear any previous FRAMEDONE, FRAMEDONETV,
476 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
478 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
480 /* disable LCD and TV managers */
481 v = omap_hwmod_read(oh, DISPC_CONTROL);
482 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
483 omap_hwmod_write(v, oh, DISPC_CONTROL);
485 /* disable LCD2 manager */
486 if (da->manager_count > 2) {
487 v = omap_hwmod_read(oh, DISPC_CONTROL2);
489 omap_hwmod_write(v, oh, DISPC_CONTROL2);
492 /* disable LCD3 manager */
493 if (da->manager_count > 3) {
494 v = omap_hwmod_read(oh, DISPC_CONTROL3);
496 omap_hwmod_write(v, oh, DISPC_CONTROL3);
500 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
503 if (i > FRAMEDONE_IRQ_TIMEOUT) {
504 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
511 int omap_dss_reset(struct omap_hwmod *oh)
513 struct omap_hwmod_opt_clk *oc;
517 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
518 pr_err("dss_core: hwmod data doesn't contain reset data\n");
522 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
524 clk_prepare_enable(oc->_clk);
526 dispc_disable_outputs();
528 /* clear SDI registers */
529 if (cpu_is_omap3430()) {
530 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
531 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
535 * clear DSS_CONTROL register to switch DSS clock sources to
538 omap_hwmod_write(0x0, oh, DSS_CONTROL);
540 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
541 & SYSS_RESETDONE_MASK),
542 MAX_MODULE_SOFTRESET_WAIT, c);
544 if (c == MAX_MODULE_SOFTRESET_WAIT)
545 pr_warning("dss_core: waiting for reset to finish failed\n");
547 pr_debug("dss_core: softreset done\n");
549 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
551 clk_disable_unprepare(oc->_clk);
553 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
558 /* list of 'compatible' nodes to convert to omapdss specific */
559 static const char * const dss_compat_conv_list[] __initconst = {
560 "composite-connector",
571 /* prepend compatible string with "omapdss," */
572 static __init void omapdss_omapify_node(struct device_node *node,
576 struct property *prop;
578 new_compat = kasprintf(GFP_KERNEL, "omapdss,%s", compat);
580 prop = kzalloc(sizeof(*prop), GFP_KERNEL);
583 pr_err("omapdss_omapify_node: kzalloc failed\n");
587 prop->name = "compatible";
588 prop->value = new_compat;
589 prop->length = strlen(new_compat) + 1;
591 of_update_property(node, prop);
595 * As omapdss panel drivers are omapdss specific, but we want to define the
596 * DT-data in generic manner, we convert the compatible strings of the panel
597 * nodes from "panel-foo" to "omapdss,panel-foo". This way we can have both
598 * correct DT data and omapdss specific drivers.
600 * When we get generic panel drivers to the kernel, this will be removed.
602 void __init omapdss_early_init_of(void)
606 for (i = 0; i < ARRAY_SIZE(dss_compat_conv_list); ++i) {
607 const char *compat = dss_compat_conv_list[i];
608 struct device_node *node = NULL;
610 while ((node = of_find_compatible_node(node, NULL, compat))) {
611 if (!of_device_is_available(node))
614 omapdss_omapify_node(node, compat);
619 struct device_node * __init omapdss_find_dss_of_node(void)
621 struct device_node *node;
623 node = of_find_compatible_node(NULL, NULL, "ti,omap2-dss");
627 node = of_find_compatible_node(NULL, NULL, "ti,omap3-dss");
631 node = of_find_compatible_node(NULL, NULL, "ti,omap4-dss");
638 int __init omapdss_init_of(void)
641 enum omapdss_version ver;
642 struct device_node *node;
643 struct platform_device *pdev;
645 static struct omap_dss_board_info board_data = {
646 .dsi_enable_pads = omap_dsi_enable_pads,
647 .dsi_disable_pads = omap_dsi_disable_pads,
648 .set_min_bus_tput = omap_dss_set_min_bus_tput,
651 /* only create dss helper devices if dss is enabled in the .dts */
653 node = omapdss_find_dss_of_node();
657 if (!of_device_is_available(node))
660 ver = omap_display_get_version();
662 if (ver == OMAPDSS_VER_UNKNOWN) {
663 pr_err("DSS not supported on this SoC\n");
667 pdev = of_find_device_by_node(node);
670 pr_err("Unable to find DSS platform device\n");
674 r = of_platform_populate(node, NULL, NULL, &pdev->dev);
676 pr_err("Unable to populate DSS submodule devices\n");
680 board_data.version = ver;
682 omap_display_device.dev.platform_data = &board_data;
684 r = platform_device_register(&omap_display_device);
686 pr_err("Unable to register omapdss device\n");
690 /* create DRM device */
693 pr_err("Unable to register omapdrm device\n");
697 /* create vrfb device */
698 r = omap_init_vrfb();
700 pr_err("Unable to register omapvrfb device\n");
704 /* create FB device */
707 pr_err("Unable to register omapfb device\n");
711 /* create V4L2 display device */
712 r = omap_init_vout();
714 pr_err("Unable to register omap_vout device\n");