2 * OMAP2plus display device setup / initialization.
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25 #include <linux/delay.h>
27 #include <video/omapdss.h>
28 #include "omap_hwmod.h"
29 #include "omap_device.h"
39 #define DISPC_CONTROL 0x0040
40 #define DISPC_CONTROL2 0x0238
41 #define DISPC_CONTROL3 0x0848
42 #define DISPC_IRQSTATUS 0x0018
44 #define DSS_SYSCONFIG 0x10
45 #define DSS_SYSSTATUS 0x14
46 #define DSS_CONTROL 0x40
47 #define DSS_SDI_CONTROL 0x44
48 #define DSS_PLL_CONTROL 0x48
50 #define LCD_EN_MASK (0x1 << 0)
51 #define DIGIT_EN_MASK (0x1 << 1)
53 #define FRAMEDONE_IRQ_SHIFT 0
54 #define EVSYNC_EVEN_IRQ_SHIFT 2
55 #define EVSYNC_ODD_IRQ_SHIFT 3
56 #define FRAMEDONE2_IRQ_SHIFT 22
57 #define FRAMEDONE3_IRQ_SHIFT 30
58 #define FRAMEDONETV_IRQ_SHIFT 24
61 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
62 * reset before deciding that something has gone wrong
64 #define FRAMEDONE_IRQ_TIMEOUT 100
66 static struct platform_device omap_display_device = {
70 .platform_data = NULL,
74 struct omap_dss_hwmod_data {
80 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
81 { "dss_core", "omapdss_dss", -1 },
82 { "dss_dispc", "omapdss_dispc", -1 },
83 { "dss_rfbi", "omapdss_rfbi", -1 },
84 { "dss_venc", "omapdss_venc", -1 },
87 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
88 { "dss_core", "omapdss_dss", -1 },
89 { "dss_dispc", "omapdss_dispc", -1 },
90 { "dss_rfbi", "omapdss_rfbi", -1 },
91 { "dss_venc", "omapdss_venc", -1 },
92 { "dss_dsi1", "omapdss_dsi", 0 },
95 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
96 { "dss_core", "omapdss_dss", -1 },
97 { "dss_dispc", "omapdss_dispc", -1 },
98 { "dss_rfbi", "omapdss_rfbi", -1 },
99 { "dss_dsi1", "omapdss_dsi", 0 },
100 { "dss_dsi2", "omapdss_dsi", 1 },
101 { "dss_hdmi", "omapdss_hdmi", -1 },
104 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
106 u32 enable_mask, enable_shift;
107 u32 pipd_mask, pipd_shift;
111 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
112 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
113 pipd_mask = OMAP4_DSI1_PIPD_MASK;
114 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
115 } else if (dsi_id == 1) {
116 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
117 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
118 pipd_mask = OMAP4_DSI2_PIPD_MASK;
119 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
124 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
129 reg |= (lanes << enable_shift) & enable_mask;
130 reg |= (lanes << pipd_shift) & pipd_mask;
132 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
137 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
139 if (cpu_is_omap44xx())
140 return omap4_dsi_mux_pads(dsi_id, lane_mask);
145 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
147 if (cpu_is_omap44xx())
148 omap4_dsi_mux_pads(dsi_id, 0);
151 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
153 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
156 static struct platform_device *create_dss_pdev(const char *pdev_name,
157 int pdev_id, const char *oh_name, void *pdata, int pdata_len,
158 struct platform_device *parent)
160 struct platform_device *pdev;
161 struct omap_device *od;
162 struct omap_hwmod *ohs[1];
163 struct omap_hwmod *oh;
166 oh = omap_hwmod_lookup(oh_name);
168 pr_err("Could not look up %s\n", oh_name);
173 pdev = platform_device_alloc(pdev_name, pdev_id);
175 pr_err("Could not create pdev for %s\n", pdev_name);
181 pdev->dev.parent = &parent->dev;
184 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
186 dev_set_name(&pdev->dev, "%s", pdev->name);
189 od = omap_device_alloc(pdev, ohs, 1);
191 pr_err("Could not alloc omap_device for %s\n", pdev_name);
196 r = platform_device_add_data(pdev, pdata, pdata_len);
198 pr_err("Could not set pdata for %s\n", pdev_name);
202 r = omap_device_register(pdev);
204 pr_err("Could not register omap_device for %s\n", pdev_name);
214 static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
215 int pdev_id, void *pdata, int pdata_len,
216 struct platform_device *parent)
218 struct platform_device *pdev;
221 pdev = platform_device_alloc(pdev_name, pdev_id);
223 pr_err("Could not create pdev for %s\n", pdev_name);
229 pdev->dev.parent = &parent->dev;
232 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
234 dev_set_name(&pdev->dev, "%s", pdev->name);
236 r = platform_device_add_data(pdev, pdata, pdata_len);
238 pr_err("Could not set pdata for %s\n", pdev_name);
242 r = platform_device_add(pdev);
244 pr_err("Could not register platform_device for %s\n", pdev_name);
254 static enum omapdss_version __init omap_display_get_version(void)
256 if (cpu_is_omap24xx())
257 return OMAPDSS_VER_OMAP24xx;
258 else if (cpu_is_omap3630())
259 return OMAPDSS_VER_OMAP3630;
260 else if (cpu_is_omap34xx()) {
261 if (soc_is_am35xx()) {
262 return OMAPDSS_VER_AM35xx;
264 if (omap_rev() < OMAP3430_REV_ES3_0)
265 return OMAPDSS_VER_OMAP34xx_ES1;
267 return OMAPDSS_VER_OMAP34xx_ES3;
269 } else if (omap_rev() == OMAP4430_REV_ES1_0)
270 return OMAPDSS_VER_OMAP4430_ES1;
271 else if (omap_rev() == OMAP4430_REV_ES2_0 ||
272 omap_rev() == OMAP4430_REV_ES2_1 ||
273 omap_rev() == OMAP4430_REV_ES2_2)
274 return OMAPDSS_VER_OMAP4430_ES2;
275 else if (cpu_is_omap44xx())
276 return OMAPDSS_VER_OMAP4;
277 else if (soc_is_omap54xx())
278 return OMAPDSS_VER_OMAP5;
280 return OMAPDSS_VER_UNKNOWN;
283 int __init omap_display_init(struct omap_dss_board_info *board_data)
286 struct platform_device *pdev;
288 const struct omap_dss_hwmod_data *curr_dss_hwmod;
289 struct platform_device *dss_pdev;
290 enum omapdss_version ver;
292 /* create omapdss device */
294 ver = omap_display_get_version();
296 if (ver == OMAPDSS_VER_UNKNOWN) {
297 pr_err("DSS not supported on this SoC\n");
301 board_data->version = ver;
302 board_data->dsi_enable_pads = omap_dsi_enable_pads;
303 board_data->dsi_disable_pads = omap_dsi_disable_pads;
304 board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
306 omap_display_device.dev.platform_data = board_data;
308 r = platform_device_register(&omap_display_device);
310 pr_err("Unable to register omapdss device\n");
314 /* create devices for dss hwmods */
316 if (cpu_is_omap24xx()) {
317 curr_dss_hwmod = omap2_dss_hwmod_data;
318 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
319 } else if (cpu_is_omap34xx()) {
320 curr_dss_hwmod = omap3_dss_hwmod_data;
321 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
323 curr_dss_hwmod = omap4_dss_hwmod_data;
324 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
328 * First create the pdev for dss_core, which is used as a parent device
329 * by the other dss pdevs. Note: dss_core has to be the first item in
332 dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
333 curr_dss_hwmod[0].id,
334 curr_dss_hwmod[0].oh_name,
335 board_data, sizeof(*board_data),
338 if (IS_ERR(dss_pdev)) {
339 pr_err("Could not build omap_device for %s\n",
340 curr_dss_hwmod[0].oh_name);
342 return PTR_ERR(dss_pdev);
345 for (i = 1; i < oh_count; i++) {
346 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
347 curr_dss_hwmod[i].id,
348 curr_dss_hwmod[i].oh_name,
349 board_data, sizeof(*board_data),
353 pr_err("Could not build omap_device for %s\n",
354 curr_dss_hwmod[i].oh_name);
356 return PTR_ERR(pdev);
360 /* Create devices for DPI and SDI */
362 pdev = create_simple_dss_pdev("omapdss_dpi", 0,
363 board_data, sizeof(*board_data), dss_pdev);
365 pr_err("Could not build platform_device for omapdss_dpi\n");
366 return PTR_ERR(pdev);
369 if (cpu_is_omap34xx()) {
370 pdev = create_simple_dss_pdev("omapdss_sdi", 0,
371 board_data, sizeof(*board_data), dss_pdev);
373 pr_err("Could not build platform_device for omapdss_sdi\n");
374 return PTR_ERR(pdev);
378 /* create DRM device */
381 pr_err("Unable to register omapdrm device\n");
385 /* create vrfb device */
386 r = omap_init_vrfb();
388 pr_err("Unable to register omapvrfb device\n");
392 /* create FB device */
395 pr_err("Unable to register omapfb device\n");
399 /* create V4L2 display device */
400 r = omap_init_vout();
402 pr_err("Unable to register omap_vout device\n");
409 static void dispc_disable_outputs(void)
412 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
414 struct omap_dss_dispc_dev_attr *da;
415 struct omap_hwmod *oh;
417 oh = omap_hwmod_lookup("dss_dispc");
419 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
424 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
428 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
430 /* store value of LCDENABLE and DIGITENABLE bits */
431 v = omap_hwmod_read(oh, DISPC_CONTROL);
432 lcd_en = v & LCD_EN_MASK;
433 digit_en = v & DIGIT_EN_MASK;
435 /* store value of LCDENABLE for LCD2 */
436 if (da->manager_count > 2) {
437 v = omap_hwmod_read(oh, DISPC_CONTROL2);
438 lcd2_en = v & LCD_EN_MASK;
441 /* store value of LCDENABLE for LCD3 */
442 if (da->manager_count > 3) {
443 v = omap_hwmod_read(oh, DISPC_CONTROL3);
444 lcd3_en = v & LCD_EN_MASK;
447 if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
448 return; /* no managers currently enabled */
451 * If any manager was enabled, we need to disable it before
452 * DSS clocks are disabled or DISPC module is reset
455 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
458 if (da->has_framedonetv_irq) {
459 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
461 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
462 1 << EVSYNC_ODD_IRQ_SHIFT;
467 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
469 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
472 * clear any previous FRAMEDONE, FRAMEDONETV,
473 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
475 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
477 /* disable LCD and TV managers */
478 v = omap_hwmod_read(oh, DISPC_CONTROL);
479 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
480 omap_hwmod_write(v, oh, DISPC_CONTROL);
482 /* disable LCD2 manager */
483 if (da->manager_count > 2) {
484 v = omap_hwmod_read(oh, DISPC_CONTROL2);
486 omap_hwmod_write(v, oh, DISPC_CONTROL2);
489 /* disable LCD3 manager */
490 if (da->manager_count > 3) {
491 v = omap_hwmod_read(oh, DISPC_CONTROL3);
493 omap_hwmod_write(v, oh, DISPC_CONTROL3);
497 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
500 if (i > FRAMEDONE_IRQ_TIMEOUT) {
501 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
508 int omap_dss_reset(struct omap_hwmod *oh)
510 struct omap_hwmod_opt_clk *oc;
514 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
515 pr_err("dss_core: hwmod data doesn't contain reset data\n");
519 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
521 clk_prepare_enable(oc->_clk);
523 dispc_disable_outputs();
525 /* clear SDI registers */
526 if (cpu_is_omap3430()) {
527 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
528 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
532 * clear DSS_CONTROL register to switch DSS clock sources to
535 omap_hwmod_write(0x0, oh, DSS_CONTROL);
537 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
538 & SYSS_RESETDONE_MASK),
539 MAX_MODULE_SOFTRESET_WAIT, c);
541 if (c == MAX_MODULE_SOFTRESET_WAIT)
542 pr_warning("dss_core: waiting for reset to finish failed\n");
544 pr_debug("dss_core: softreset done\n");
546 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
548 clk_disable_unprepare(oc->_clk);
550 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;