4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 * Copyright (C) 2009 Texas Instruments
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
16 * Converted DMA library into platform driver
17 * - G, Manjunath Kondaiah <manjugk@ti.com>
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
24 #include <linux/err.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/device.h>
30 #include <linux/dma-mapping.h>
32 #include <linux/omap-dma.h>
35 #include "omap_hwmod.h"
36 #include "omap_device.h"
38 #define OMAP2_DMA_STRIDE 0x60
43 static struct omap_dma_dev_attr *d;
45 static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
47 static u16 reg_map[] = {
50 [IRQSTATUS_L0] = 0x08,
51 [IRQSTATUS_L1] = 0x0c,
52 [IRQSTATUS_L2] = 0x10,
53 [IRQSTATUS_L3] = 0x14,
54 [IRQENABLE_L0] = 0x18,
55 [IRQENABLE_L1] = 0x1c,
56 [IRQENABLE_L2] = 0x20,
57 [IRQENABLE_L3] = 0x24,
59 [OCP_SYSCONFIG] = 0x2c,
65 /* Common register offsets */
80 /* Channel specific register offsets */
87 /* OMAP4 specific registers */
93 static void __iomem *dma_base;
94 static inline void dma_write(u32 val, int reg, int lch)
99 stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
100 offset = reg_map[reg] + (stride * lch);
101 __raw_writel(val, dma_base + offset);
104 static inline u32 dma_read(int reg, int lch)
109 stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
110 offset = reg_map[reg] + (stride * lch);
111 val = __raw_readl(dma_base + offset);
115 static void omap2_clear_dma(int lch)
117 int i = dma_common_ch_start;
119 for (; i <= dma_common_ch_end; i += 1)
120 dma_write(0, i, lch);
123 static void omap2_show_dma_caps(void)
125 u8 revision = dma_read(REVISION, 0) & 0xff;
126 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
127 revision >> 4, revision & 0xf);
131 static u32 configure_dma_errata(void)
135 * Errata applicable for OMAP2430ES1.0 and all omap2420
138 * Erratum ID: Not Available
139 * Inter Frame DMA buffering issue DMA will wrongly
140 * buffer elements if packing and bursting is enabled. This might
141 * result in data gets stalled in FIFO at the end of the block.
142 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
143 * guarantee no data will stay in the DMA FIFO in case inter frame
147 * Erratum ID: Not Available
148 * DMA may hang when several channels are used in parallel
149 * In the following configuration, DMA channel hanging can occur:
150 * a. Channel i, hardware synchronized, is enabled
151 * b. Another channel (Channel x), software synchronized, is enabled.
152 * c. Channel i is disabled before end of transfer
153 * d. Channel i is reenabled.
154 * e. Steps 1 to 4 are repeated a certain number of times.
155 * f. A third channel (Channel y), software synchronized, is enabled.
156 * Channel x and Channel y may hang immediately after step 'f'.
158 * For any channel used - make sure NextLCH_ID is set to the value j.
160 if (cpu_is_omap2420() || (cpu_is_omap2430() &&
161 (omap_type() == OMAP2430_REV_ES1_0))) {
163 SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
164 SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
168 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
169 * after a transaction error.
170 * Workaround: SW should explicitely disable the channel.
172 if (cpu_class_is_omap2())
173 SET_DMA_ERRATA(DMA_ERRATA_i378);
176 * Erratum ID: i541: sDMA FIFO draining does not finish
177 * If sDMA channel is disabled on the fly, sDMA enters standby even
178 * through FIFO Drain is still in progress
179 * Workaround: Put sDMA in NoStandby more before a logical channel is
180 * disabled, then put it back to SmartStandby right after the channel
181 * finishes FIFO draining.
183 if (cpu_is_omap34xx())
184 SET_DMA_ERRATA(DMA_ERRATA_i541);
187 * Erratum ID: i88 : Special programming model needed to disable DMA
188 * before end of block.
189 * Workaround: software must ensure that the DMA is configured in No
190 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
192 if (omap_type() == OMAP3430_REV_ES1_0)
193 SET_DMA_ERRATA(DMA_ERRATA_i88);
196 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
197 * read before the DMA controller finished disabling the channel.
199 SET_DMA_ERRATA(DMA_ERRATA_3_3);
202 * Erratum ID: Not Available
203 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
204 * after secure sram context save and restore.
205 * Work around: Hence we need to manually clear those IRQs to avoid
206 * spurious interrupts. This affects only secure devices.
208 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
209 SET_DMA_ERRATA(DMA_ROMCODE_BUG);
214 /* One time initializations */
215 static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
217 struct platform_device *pdev;
218 struct omap_system_dma_plat_info *p;
219 struct resource *mem;
220 char *name = "omap_dma_system";
222 dma_stride = OMAP2_DMA_STRIDE;
223 dma_common_ch_start = CSDP;
225 p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
227 pr_err("%s: Unable to allocate pdata for %s:%s\n",
228 __func__, name, oh->name);
232 p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
233 p->show_dma_caps = omap2_show_dma_caps;
234 p->clear_dma = omap2_clear_dma;
235 p->dma_write = dma_write;
236 p->dma_read = dma_read;
238 p->clear_lch_regs = NULL;
240 p->errata = configure_dma_errata();
242 pdev = omap_device_build(name, 0, oh, p, sizeof(*p));
245 pr_err("%s: Can't build omap_device for %s:%s.\n",
246 __func__, name, oh->name);
247 return PTR_ERR(pdev);
250 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
252 dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
255 dma_base = ioremap(mem->start, resource_size(mem));
257 dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
262 d->chan = kzalloc(sizeof(struct omap_dma_lch) *
263 (d->lch_count), GFP_KERNEL);
266 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
270 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
271 d->dev_caps |= HS_CHANNELS_RESERVED;
273 /* Check the capabilities register for descriptor loading feature */
274 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
275 dma_common_ch_end = CCDN;
277 dma_common_ch_end = CCFN;
282 static const struct platform_device_info omap_dma_dev_info = {
283 .name = "omap-dma-engine",
285 .dma_mask = DMA_BIT_MASK(32),
288 static int __init omap2_system_dma_init(void)
290 struct platform_device *pdev;
293 res = omap_hwmod_for_each_by_class("dma",
294 omap2_system_dma_init_dev, NULL);
298 if (of_have_populated_dt())
301 pdev = platform_device_register_full(&omap_dma_dev_info);
303 return PTR_ERR(pdev);
307 omap_arch_initcall(omap2_system_dma_init);