2 * OMAP4-specific DPLL control functions
4 * Copyright (C) 2011 Texas Instruments, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/errno.h>
14 #include <linux/clk.h>
16 #include <linux/bitops.h>
18 #include <plat/clock.h>
22 #include "clock44xx.h"
23 #include "cm-regbits-44xx.h"
25 /* Supported only on OMAP4 */
26 int omap4_dpllmx_gatectrl_read(struct clk *clk)
31 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
34 mask = clk->flags & CLOCK_CLKOUTX2 ?
35 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
36 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
38 v = __raw_readl(clk->clksel_reg);
45 void omap4_dpllmx_allow_gatectrl(struct clk *clk)
50 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
53 mask = clk->flags & CLOCK_CLKOUTX2 ?
54 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
55 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
57 v = __raw_readl(clk->clksel_reg);
58 /* Clear the bit to allow gatectrl */
60 __raw_writel(v, clk->clksel_reg);
63 void omap4_dpllmx_deny_gatectrl(struct clk *clk)
68 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
71 mask = clk->flags & CLOCK_CLKOUTX2 ?
72 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
73 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
75 v = __raw_readl(clk->clksel_reg);
76 /* Set the bit to deny gatectrl */
78 __raw_writel(v, clk->clksel_reg);
81 const struct clkops clkops_omap4_dpllmx_ops = {
82 .allow_idle = omap4_dpllmx_allow_gatectrl,
83 .deny_idle = omap4_dpllmx_deny_gatectrl,
87 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
88 * @clk: struct clk * of the DPLL to compute the rate for
90 * Compute the output rate for the OMAP4 DPLL represented by @clk.
91 * Takes the REGM4XEN bit into consideration, which is needed for the
92 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
93 * upon success, or 0 upon error.
95 unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk)
101 if (!clk || !clk->dpll_data)
106 rate = omap2_get_dpll_rate(clk);
108 /* regm4xen adds a multiplier of 4 to DPLL calculations */
109 v = __raw_readl(dd->control_reg);
110 if (v & OMAP4430_DPLL_REGM4XEN_MASK)
111 rate *= OMAP4430_REGM4XEN_MULT;
117 * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
118 * @clk: struct clk * of the DPLL to round a rate for
119 * @target_rate: the desired rate of the DPLL
121 * Compute the rate that would be programmed into the DPLL hardware
122 * for @clk if set_rate() were to be provided with the rate
123 * @target_rate. Takes the REGM4XEN bit into consideration, which is
124 * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
125 * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
126 * ~0 if an error occurred in omap2_dpll_round_rate().
128 long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate)
131 struct dpll_data *dd;
134 if (!clk || !clk->dpll_data)
139 /* regm4xen adds a multiplier of 4 to DPLL calculations */
140 v = __raw_readl(dd->control_reg) & OMAP4430_DPLL_REGM4XEN_MASK;
143 target_rate = target_rate / OMAP4430_REGM4XEN_MULT;
145 r = omap2_dpll_round_rate(clk, target_rate);
150 clk->dpll_data->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
152 return clk->dpll_data->last_rounded_rate;