arch/arm/mach-omap2/gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #undef DEBUG
  16
  17 #include <linux/irq.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/ioport.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/io.h>
  25 #include <linux/module.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/of.h>
  29 #include <linux/of_mtd.h>
  30 #include <linux/of_device.h>
  31 #include <linux/mtd/nand.h>
  32
  33 #include <linux/platform_data/mtd-nand-omap2.h>
  34
  35 #include <asm/mach-types.h>
  36
  37 #include "soc.h"
  38 #include "common.h"
  39 #include "omap_device.h"
  40 #include "gpmc.h"
  41 #include "gpmc-nand.h"
  42
  43 #define DEVICE_NAME             "omap-gpmc"
  44
  45 /* GPMC register offsets */
  46 #define GPMC_REVISION           0x00
  47 #define GPMC_SYSCONFIG          0x10
  48 #define GPMC_SYSSTATUS          0x14
  49 #define GPMC_IRQSTATUS          0x18
  50 #define GPMC_IRQENABLE          0x1c
  51 #define GPMC_TIMEOUT_CONTROL    0x40
  52 #define GPMC_ERR_ADDRESS        0x44
  53 #define GPMC_ERR_TYPE           0x48
  54 #define GPMC_CONFIG             0x50
  55 #define GPMC_STATUS             0x54
  56 #define GPMC_PREFETCH_CONFIG1   0x1e0
  57 #define GPMC_PREFETCH_CONFIG2   0x1e4
  58 #define GPMC_PREFETCH_CONTROL   0x1ec
  59 #define GPMC_PREFETCH_STATUS    0x1f0
  60 #define GPMC_ECC_CONFIG         0x1f4
  61 #define GPMC_ECC_CONTROL        0x1f8
  62 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  63 #define GPMC_ECC1_RESULT        0x200
  64 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  66 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  67 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  68
  69 /* GPMC ECC control settings */
  70 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  71 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  72 #define GPMC_ECC_CTRL_ECCREG1           0x001
  73 #define GPMC_ECC_CTRL_ECCREG2           0x002
  74 #define GPMC_ECC_CTRL_ECCREG3           0x003
  75 #define GPMC_ECC_CTRL_ECCREG4           0x004
  76 #define GPMC_ECC_CTRL_ECCREG5           0x005
  77 #define GPMC_ECC_CTRL_ECCREG6           0x006
  78 #define GPMC_ECC_CTRL_ECCREG7           0x007
  79 #define GPMC_ECC_CTRL_ECCREG8           0x008
  80 #define GPMC_ECC_CTRL_ECCREG9           0x009
  81
  82 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  83 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  84 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  85 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  86 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  87 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  88
  89 #define GPMC_CS0_OFFSET         0x60
  90 #define GPMC_CS_SIZE            0x30
  91 #define GPMC_BCH_SIZE           0x10
  92
  93 #define GPMC_MEM_START          0x00000000
  94 #define GPMC_MEM_END            0x3FFFFFFF
  95 #define BOOT_ROM_SPACE          0x100000        /* 1MB */
  96
  97 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
  98 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
  99
 100 #define CS_NUM_SHIFT            24
 101 #define ENABLE_PREFETCH         (0x1 << 7)
 102 #define DMA_MPU_MODE            2
 103
 104 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 105 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 106
 107 #define GPMC_HAS_WR_ACCESS              0x1
 108 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 109
 110 /* XXX: Only NAND irq has been considered,currently these are the only ones used
 111  */
 112 #define GPMC_NR_IRQ             2
 113
 114 struct gpmc_client_irq  {
 115         unsigned                irq;
 116         u32                     bitmask;
 117 };
 118
 119 /* Structure to save gpmc cs context */
 120 struct gpmc_cs_config {
 121         u32 config1;
 122         u32 config2;
 123         u32 config3;
 124         u32 config4;
 125         u32 config5;
 126         u32 config6;
 127         u32 config7;
 128         int is_valid;
 129 };
 130
 131 /*
 132  * Structure to save/restore gpmc context
 133  * to support core off on OMAP3
 134  */
 135 struct omap3_gpmc_regs {
 136         u32 sysconfig;
 137         u32 irqenable;
 138         u32 timeout_ctrl;
 139         u32 config;
 140         u32 prefetch_config1;
 141         u32 prefetch_config2;
 142         u32 prefetch_control;
 143         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 144 };
 145
 146 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
 147 static struct irq_chip gpmc_irq_chip;
 148 static unsigned gpmc_irq_start;
 149
 150 static struct resource  gpmc_mem_root;
 151 static struct resource  gpmc_cs_mem[GPMC_CS_NUM];
 152 static DEFINE_SPINLOCK(gpmc_mem_lock);
 153 /* Define chip-selects as reserved by default until probe completes */
 154 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
 155 static struct device *gpmc_dev;
 156 static int gpmc_irq;
 157 static resource_size_t phys_base, mem_size;
 158 static unsigned gpmc_capability;
 159 static void __iomem *gpmc_base;
 160
 161 static struct clk *gpmc_l3_clk;
 162
 163 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 164
 165 static void gpmc_write_reg(int idx, u32 val)
 166 {
 167         __raw_writel(val, gpmc_base + idx);
 168 }
 169
 170 static u32 gpmc_read_reg(int idx)
 171 {
 172         return __raw_readl(gpmc_base + idx);
 173 }
 174
 175 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 176 {
 177         void __iomem *reg_addr;
 178
 179         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 180         __raw_writel(val, reg_addr);
 181 }
 182
 183 u32 gpmc_cs_read_reg(int cs, int idx)
 184 {
 185         void __iomem *reg_addr;
 186
 187         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 188         return __raw_readl(reg_addr);
 189 }
 190
 191 /* TODO: Add support for gpmc_fck to clock framework and use it */
 192 unsigned long gpmc_get_fclk_period(void)
 193 {
 194         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 195
 196         if (rate == 0) {
 197                 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
 198                 return 0;
 199         }
 200
 201         rate /= 1000;
 202         rate = 1000000000 / rate;       /* In picoseconds */
 203
 204         return rate;
 205 }
 206
 207 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 208 {
 209         unsigned long tick_ps;
 210
 211         /* Calculate in picosecs to yield more exact results */
 212         tick_ps = gpmc_get_fclk_period();
 213
 214         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 215 }
 216
 217 unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 218 {
 219         unsigned long tick_ps;
 220
 221         /* Calculate in picosecs to yield more exact results */
 222         tick_ps = gpmc_get_fclk_period();
 223
 224         return (time_ps + tick_ps - 1) / tick_ps;
 225 }
 226
 227 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 228 {
 229         return ticks * gpmc_get_fclk_period() / 1000;
 230 }
 231
 232 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
 233 {
 234         unsigned long ticks = gpmc_ns_to_ticks(time_ns);
 235
 236         return ticks * gpmc_get_fclk_period() / 1000;
 237 }
 238
 239 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 240 {
 241         return ticks * gpmc_get_fclk_period();
 242 }
 243
 244 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 245 {
 246         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 247
 248         return ticks * gpmc_get_fclk_period();
 249 }
 250
 251 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 252 {
 253         u32 l;
 254
 255         l = gpmc_cs_read_reg(cs, reg);
 256         if (value)
 257                 l |= mask;
 258         else
 259                 l &= ~mask;
 260         gpmc_cs_write_reg(cs, reg, l);
 261 }
 262
 263 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 264 {
 265         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 266                            GPMC_CONFIG1_TIME_PARA_GRAN,
 267                            p->time_para_granularity);
 268         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 269                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 270         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 271                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 272         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 273                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 274         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 275                            GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
 276         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 277                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 278                            p->cycle2cyclesamecsen);
 279         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 280                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 281                            p->cycle2cyclediffcsen);
 282 }
 283
 284 #ifdef DEBUG
 285 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 286                                int time, const char *name)
 287 #else
 288 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 289                                int time)
 290 #endif
 291 {
 292         u32 l;
 293         int ticks, mask, nr_bits;
 294
 295         if (time == 0)
 296                 ticks = 0;
 297         else
 298                 ticks = gpmc_ns_to_ticks(time);
 299         nr_bits = end_bit - st_bit + 1;
 300         if (ticks >= 1 << nr_bits) {
 301 #ifdef DEBUG
 302                 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
 303                                 cs, name, time, ticks, 1 << nr_bits);
 304 #endif
 305                 return -1;
 306         }
 307
 308         mask = (1 << nr_bits) - 1;
 309         l = gpmc_cs_read_reg(cs, reg);
 310 #ifdef DEBUG
 311         printk(KERN_INFO
 312                 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 313                cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
 314                         (l >> st_bit) & mask, time);
 315 #endif
 316         l &= ~(mask << st_bit);
 317         l |= ticks << st_bit;
 318         gpmc_cs_write_reg(cs, reg, l);
 319
 320         return 0;
 321 }
 322
 323 #ifdef DEBUG
 324 #define GPMC_SET_ONE(reg, st, end, field) \
 325         if (set_gpmc_timing_reg(cs, (reg), (st), (end),         \
 326                         t->field, #field) < 0)                  \
 327                 return -1
 328 #else
 329 #define GPMC_SET_ONE(reg, st, end, field) \
 330         if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
 331                 return -1
 332 #endif
 333
 334 int gpmc_calc_divider(unsigned int sync_clk)
 335 {
 336         int div;
 337         u32 l;
 338
 339         l = sync_clk + (gpmc_get_fclk_period() - 1);
 340         div = l / gpmc_get_fclk_period();
 341         if (div > 4)
 342                 return -1;
 343         if (div <= 0)
 344                 div = 1;
 345
 346         return div;
 347 }
 348
 349 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 350 {
 351         int div;
 352         u32 l;
 353
 354         div = gpmc_calc_divider(t->sync_clk);
 355         if (div < 0)
 356                 return div;
 357
 358         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 359         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 360         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 361
 362         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 363         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 364         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 365
 366         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 367         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 368         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 369         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 370
 371         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 372         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 373         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 374
 375         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 376
 377         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 378         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 379
 380         GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
 381         GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
 382
 383         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 384                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 385         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 386                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 387
 388         /* caller is expected to have initialized CONFIG1 to cover
 389          * at least sync vs async
 390          */
 391         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 392         if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
 393 #ifdef DEBUG
 394                 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
 395                                 cs, (div * gpmc_get_fclk_period()) / 1000, div);
 396 #endif
 397                 l &= ~0x03;
 398                 l |= (div - 1);
 399                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 400         }
 401
 402         gpmc_cs_bool_timings(cs, &t->bool_timings);
 403
 404         return 0;
 405 }
 406
 407 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
 408 {
 409         u32 l;
 410         u32 mask;
 411
 412         mask = (1 << GPMC_SECTION_SHIFT) - size;
 413         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 414         l &= ~0x3f;
 415         l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
 416         l &= ~(0x0f << 8);
 417         l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
 418         l |= GPMC_CONFIG7_CSVALID;
 419         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 420 }
 421
 422 static void gpmc_cs_disable_mem(int cs)
 423 {
 424         u32 l;
 425
 426         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 427         l &= ~GPMC_CONFIG7_CSVALID;
 428         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 429 }
 430
 431 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 432 {
 433         u32 l;
 434         u32 mask;
 435
 436         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 437         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 438         mask = (l >> 8) & 0x0f;
 439         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 440 }
 441
 442 static int gpmc_cs_mem_enabled(int cs)
 443 {
 444         u32 l;
 445
 446         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 447         return l & GPMC_CONFIG7_CSVALID;
 448 }
 449
 450 int gpmc_cs_set_reserved(int cs, int reserved)
 451 {
 452         if (cs > GPMC_CS_NUM)
 453                 return -ENODEV;
 454
 455         gpmc_cs_map &= ~(1 << cs);
 456         gpmc_cs_map |= (reserved ? 1 : 0) << cs;
 457
 458         return 0;
 459 }
 460
 461 int gpmc_cs_reserved(int cs)
 462 {
 463         if (cs > GPMC_CS_NUM)
 464                 return -ENODEV;
 465
 466         return gpmc_cs_map & (1 << cs);
 467 }
 468
 469 static unsigned long gpmc_mem_align(unsigned long size)
 470 {
 471         int order;
 472
 473         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 474         order = GPMC_CHUNK_SHIFT - 1;
 475         do {
 476                 size >>= 1;
 477                 order++;
 478         } while (size);
 479         size = 1 << order;
 480         return size;
 481 }
 482
 483 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 484 {
 485         struct resource *res = &gpmc_cs_mem[cs];
 486         int r;
 487
 488         size = gpmc_mem_align(size);
 489         spin_lock(&gpmc_mem_lock);
 490         res->start = base;
 491         res->end = base + size - 1;
 492         r = request_resource(&gpmc_mem_root, res);
 493         spin_unlock(&gpmc_mem_lock);
 494
 495         return r;
 496 }
 497
 498 static int gpmc_cs_delete_mem(int cs)
 499 {
 500         struct resource *res = &gpmc_cs_mem[cs];
 501         int r;
 502
 503         spin_lock(&gpmc_mem_lock);
 504         r = release_resource(&gpmc_cs_mem[cs]);
 505         res->start = 0;
 506         res->end = 0;
 507         spin_unlock(&gpmc_mem_lock);
 508
 509         return r;
 510 }
 511
 512 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 513 {
 514         struct resource *res = &gpmc_cs_mem[cs];
 515         int r = -1;
 516
 517         if (cs > GPMC_CS_NUM)
 518                 return -ENODEV;
 519
 520         size = gpmc_mem_align(size);
 521         if (size > (1 << GPMC_SECTION_SHIFT))
 522                 return -ENOMEM;
 523
 524         spin_lock(&gpmc_mem_lock);
 525         if (gpmc_cs_reserved(cs)) {
 526                 r = -EBUSY;
 527                 goto out;
 528         }
 529         if (gpmc_cs_mem_enabled(cs))
 530                 r = adjust_resource(res, res->start & ~(size - 1), size);
 531         if (r < 0)
 532                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
 533                                       size, NULL, NULL);
 534         if (r < 0)
 535                 goto out;
 536
 537         gpmc_cs_enable_mem(cs, res->start, resource_size(res));
 538         *base = res->start;
 539         gpmc_cs_set_reserved(cs, 1);
 540 out:
 541         spin_unlock(&gpmc_mem_lock);
 542         return r;
 543 }
 544 EXPORT_SYMBOL(gpmc_cs_request);
 545
 546 void gpmc_cs_free(int cs)
 547 {
 548         spin_lock(&gpmc_mem_lock);
 549         if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
 550                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
 551                 BUG();
 552                 spin_unlock(&gpmc_mem_lock);
 553                 return;
 554         }
 555         gpmc_cs_disable_mem(cs);
 556         release_resource(&gpmc_cs_mem[cs]);
 557         gpmc_cs_set_reserved(cs, 0);
 558         spin_unlock(&gpmc_mem_lock);
 559 }
 560 EXPORT_SYMBOL(gpmc_cs_free);
 561
 562 /**
 563  * gpmc_cs_configure - write request to configure gpmc
 564  * @cs: chip select number
 565  * @cmd: command type
 566  * @wval: value to write
 567  * @return status of the operation
 568  */
 569 int gpmc_cs_configure(int cs, int cmd, int wval)
 570 {
 571         int err = 0;
 572         u32 regval = 0;
 573
 574         switch (cmd) {
 575         case GPMC_ENABLE_IRQ:
 576                 gpmc_write_reg(GPMC_IRQENABLE, wval);
 577                 break;
 578
 579         case GPMC_SET_IRQ_STATUS:
 580                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
 581                 break;
 582
 583         case GPMC_CONFIG_WP:
 584                 regval = gpmc_read_reg(GPMC_CONFIG);
 585                 if (wval)
 586                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
 587                 else
 588                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
 589                 gpmc_write_reg(GPMC_CONFIG, regval);
 590                 break;
 591
 592         case GPMC_CONFIG_RDY_BSY:
 593                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 594                 if (wval)
 595                         regval |= WR_RD_PIN_MONITORING;
 596                 else
 597                         regval &= ~WR_RD_PIN_MONITORING;
 598                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 599                 break;
 600
 601         case GPMC_CONFIG_DEV_SIZE:
 602                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 603
 604                 /* clear 2 target bits */
 605                 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
 606
 607                 /* set the proper value */
 608                 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
 609
 610                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 611                 break;
 612
 613         case GPMC_CONFIG_DEV_TYPE:
 614                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 615                 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
 616                 if (wval == GPMC_DEVICETYPE_NOR)
 617                         regval |= GPMC_CONFIG1_MUXADDDATA;
 618                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 619                 break;
 620
 621         default:
 622                 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
 623                 err = -EINVAL;
 624         }
 625
 626         return err;
 627 }
 628 EXPORT_SYMBOL(gpmc_cs_configure);
 629
 630 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 631 {
 632         int i;
 633
 634         reg->gpmc_status = gpmc_base + GPMC_STATUS;
 635         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
 636                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
 637         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
 638                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
 639         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
 640                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
 641         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
 642         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
 643         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
 644         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
 645         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
 646         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
 647         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
 648         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
 649
 650         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
 651                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
 652                                            GPMC_BCH_SIZE * i;
 653                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
 654                                            GPMC_BCH_SIZE * i;
 655                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
 656                                            GPMC_BCH_SIZE * i;
 657                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
 658                                            GPMC_BCH_SIZE * i;
 659         }
 660 }
 661
 662 int gpmc_get_client_irq(unsigned irq_config)
 663 {
 664         int i;
 665
 666         if (hweight32(irq_config) > 1)
 667                 return 0;
 668
 669         for (i = 0; i < GPMC_NR_IRQ; i++)
 670                 if (gpmc_client_irq[i].bitmask & irq_config)
 671                         return gpmc_client_irq[i].irq;
 672
 673         return 0;
 674 }
 675
 676 static int gpmc_irq_endis(unsigned irq, bool endis)
 677 {
 678         int i;
 679         u32 regval;
 680
 681         for (i = 0; i < GPMC_NR_IRQ; i++)
 682                 if (irq == gpmc_client_irq[i].irq) {
 683                         regval = gpmc_read_reg(GPMC_IRQENABLE);
 684                         if (endis)
 685                                 regval |= gpmc_client_irq[i].bitmask;
 686                         else
 687                                 regval &= ~gpmc_client_irq[i].bitmask;
 688                         gpmc_write_reg(GPMC_IRQENABLE, regval);
 689                         break;
 690                 }
 691
 692         return 0;
 693 }
 694
 695 static void gpmc_irq_disable(struct irq_data *p)
 696 {
 697         gpmc_irq_endis(p->irq, false);
 698 }
 699
 700 static void gpmc_irq_enable(struct irq_data *p)
 701 {
 702         gpmc_irq_endis(p->irq, true);
 703 }
 704
 705 static void gpmc_irq_noop(struct irq_data *data) { }
 706
 707 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
 708
 709 static int gpmc_setup_irq(void)
 710 {
 711         int i;
 712         u32 regval;
 713
 714         if (!gpmc_irq)
 715                 return -EINVAL;
 716
 717         gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
 718         if (IS_ERR_VALUE(gpmc_irq_start)) {
 719                 pr_err("irq_alloc_descs failed\n");
 720                 return gpmc_irq_start;
 721         }
 722
 723         gpmc_irq_chip.name = "gpmc";
 724         gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
 725         gpmc_irq_chip.irq_enable = gpmc_irq_enable;
 726         gpmc_irq_chip.irq_disable = gpmc_irq_disable;
 727         gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
 728         gpmc_irq_chip.irq_ack = gpmc_irq_noop;
 729         gpmc_irq_chip.irq_mask = gpmc_irq_noop;
 730         gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
 731
 732         gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
 733         gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
 734
 735         for (i = 0; i < GPMC_NR_IRQ; i++) {
 736                 gpmc_client_irq[i].irq = gpmc_irq_start + i;
 737                 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
 738                                         &gpmc_irq_chip, handle_simple_irq);
 739                 set_irq_flags(gpmc_client_irq[i].irq,
 740                                 IRQF_VALID | IRQF_NOAUTOEN);
 741         }
 742
 743         /* Disable interrupts */
 744         gpmc_write_reg(GPMC_IRQENABLE, 0);
 745
 746         /* clear interrupts */
 747         regval = gpmc_read_reg(GPMC_IRQSTATUS);
 748         gpmc_write_reg(GPMC_IRQSTATUS, regval);
 749
 750         return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
 751 }
 752
 753 static int gpmc_free_irq(void)
 754 {
 755         int i;
 756
 757         if (gpmc_irq)
 758                 free_irq(gpmc_irq, NULL);
 759
 760         for (i = 0; i < GPMC_NR_IRQ; i++) {
 761                 irq_set_handler(gpmc_client_irq[i].irq, NULL);
 762                 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
 763                 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
 764         }
 765
 766         irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
 767
 768         return 0;
 769 }
 770
 771 static void gpmc_mem_exit(void)
 772 {
 773         int cs;
 774
 775         for (cs = 0; cs < GPMC_CS_NUM; cs++) {
 776                 if (!gpmc_cs_mem_enabled(cs))
 777                         continue;
 778                 gpmc_cs_delete_mem(cs);
 779         }
 780
 781 }
 782
 783 static int gpmc_mem_init(void)
 784 {
 785         int cs, rc;
 786         unsigned long boot_rom_space = 0;
 787
 788         /* never allocate the first page, to facilitate bug detection;
 789          * even if we didn't boot from ROM.
 790          */
 791         boot_rom_space = BOOT_ROM_SPACE;
 792         /* In apollon the CS0 is mapped as 0x0000 0000 */
 793         if (machine_is_omap_apollon())
 794                 boot_rom_space = 0;
 795         gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
 796         gpmc_mem_root.end = GPMC_MEM_END;
 797
 798         /* Reserve all regions that has been set up by bootloader */
 799         for (cs = 0; cs < GPMC_CS_NUM; cs++) {
 800                 u32 base, size;
 801
 802                 if (!gpmc_cs_mem_enabled(cs))
 803                         continue;
 804                 gpmc_cs_get_memconf(cs, &base, &size);
 805                 rc = gpmc_cs_insert_mem(cs, base, size);
 806                 if (IS_ERR_VALUE(rc)) {
 807                         while (--cs >= 0)
 808                                 if (gpmc_cs_mem_enabled(cs))
 809                                         gpmc_cs_delete_mem(cs);
 810                         return rc;
 811                 }
 812         }
 813
 814         return 0;
 815 }
 816
 817 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
 818 {
 819         u32 temp;
 820         int div;
 821
 822         div = gpmc_calc_divider(sync_clk);
 823         temp = gpmc_ps_to_ticks(time_ps);
 824         temp = (temp + div - 1) / div;
 825         return gpmc_ticks_to_ps(temp * div);
 826 }
 827
 828 /* XXX: can the cycles be avoided ? */
 829 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
 830                                 struct gpmc_device_timings *dev_t)
 831 {
 832         bool mux = dev_t->mux;
 833         u32 temp;
 834
 835         /* adv_rd_off */
 836         temp = dev_t->t_avdp_r;
 837         /* XXX: mux check required ? */
 838         if (mux) {
 839                 /* XXX: t_avdp not to be required for sync, only added for tusb
 840                  * this indirectly necessitates requirement of t_avdp_r and
 841                  * t_avdp_w instead of having a single t_avdp
 842                  */
 843                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
 844                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
 845         }
 846         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
 847
 848         /* oe_on */
 849         temp = dev_t->t_oeasu; /* XXX: remove this ? */
 850         if (mux) {
 851                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
 852                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
 853                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
 854         }
 855         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
 856
 857         /* access */
 858         /* XXX: any scope for improvement ?, by combining oe_on
 859          * and clk_activation, need to check whether
 860          * access = clk_activation + round to sync clk ?
 861          */
 862         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
 863         temp += gpmc_t->clk_activation;
 864         if (dev_t->cyc_oe)
 865                 temp = max_t(u32, temp, gpmc_t->oe_on +
 866                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
 867         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
 868
 869         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
 870         gpmc_t->cs_rd_off = gpmc_t->oe_off;
 871
 872         /* rd_cycle */
 873         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
 874         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
 875                                                         gpmc_t->access;
 876         /* XXX: barter t_ce_rdyz with t_cez_r ? */
 877         if (dev_t->t_ce_rdyz)
 878                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
 879         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
 880
 881         return 0;
 882 }
 883
 884 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
 885                                 struct gpmc_device_timings *dev_t)
 886 {
 887         bool mux = dev_t->mux;
 888         u32 temp;
 889
 890         /* adv_wr_off */
 891         temp = dev_t->t_avdp_w;
 892         if (mux) {
 893                 temp = max_t(u32, temp,
 894                         gpmc_t->clk_activation + dev_t->t_avdh);
 895                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
 896         }
 897         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
 898
 899         /* wr_data_mux_bus */
 900         temp = max_t(u32, dev_t->t_weasu,
 901                         gpmc_t->clk_activation + dev_t->t_rdyo);
 902         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
 903          * and in that case remember to handle we_on properly
 904          */
 905         if (mux) {
 906                 temp = max_t(u32, temp,
 907                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
 908                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
 909                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
 910         }
 911         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
 912
 913         /* we_on */
 914         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 915                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
 916         else
 917                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
 918
 919         /* wr_access */
 920         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
 921         gpmc_t->wr_access = gpmc_t->access;
 922
 923         /* we_off */
 924         temp = gpmc_t->we_on + dev_t->t_wpl;
 925         temp = max_t(u32, temp,
 926                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
 927         temp = max_t(u32, temp,
 928                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
 929         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
 930
 931         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
 932                                                         dev_t->t_wph);
 933
 934         /* wr_cycle */
 935         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
 936         temp += gpmc_t->wr_access;
 937         /* XXX: barter t_ce_rdyz with t_cez_w ? */
 938         if (dev_t->t_ce_rdyz)
 939                 temp = max_t(u32, temp,
 940                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
 941         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
 942
 943         return 0;
 944 }
 945
 946 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
 947                                 struct gpmc_device_timings *dev_t)
 948 {
 949         bool mux = dev_t->mux;
 950         u32 temp;
 951
 952         /* adv_rd_off */
 953         temp = dev_t->t_avdp_r;
 954         if (mux)
 955                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
 956         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
 957
 958         /* oe_on */
 959         temp = dev_t->t_oeasu;
 960         if (mux)
 961                 temp = max_t(u32, temp,
 962                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
 963         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
 964
 965         /* access */
 966         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
 967                                 gpmc_t->oe_on + dev_t->t_oe);
 968         temp = max_t(u32, temp,
 969                                 gpmc_t->cs_on + dev_t->t_ce);
 970         temp = max_t(u32, temp,
 971                                 gpmc_t->adv_on + dev_t->t_aa);
 972         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
 973
 974         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
 975         gpmc_t->cs_rd_off = gpmc_t->oe_off;
 976
 977         /* rd_cycle */
 978         temp = max_t(u32, dev_t->t_rd_cycle,
 979                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
 980         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
 981         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
 982
 983         return 0;
 984 }
 985
 986 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
 987                                 struct gpmc_device_timings *dev_t)
 988 {
 989         bool mux = dev_t->mux;
 990         u32 temp;
 991
 992         /* adv_wr_off */
 993         temp = dev_t->t_avdp_w;
 994         if (mux)
 995                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
 996         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
 997
 998         /* wr_data_mux_bus */
 999         temp = dev_t->t_weasu;
1000         if (mux) {
1001                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1002                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1003                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1004         }
1005         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1006
1007         /* we_on */
1008         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1009                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1010         else
1011                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1012
1013         /* we_off */
1014         temp = gpmc_t->we_on + dev_t->t_wpl;
1015         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1016
1017         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1018                                                         dev_t->t_wph);
1019
1020         /* wr_cycle */
1021         temp = max_t(u32, dev_t->t_wr_cycle,
1022                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1023         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1024
1025         return 0;
1026 }
1027
1028 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1029                         struct gpmc_device_timings *dev_t)
1030 {
1031         u32 temp;
1032
1033         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1034                                                 gpmc_get_fclk_period();
1035
1036         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1037                                         dev_t->t_bacc,
1038                                         gpmc_t->sync_clk);
1039
1040         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1041         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1042
1043         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1044                 return 0;
1045
1046         if (dev_t->ce_xdelay)
1047                 gpmc_t->bool_timings.cs_extra_delay = true;
1048         if (dev_t->avd_xdelay)
1049                 gpmc_t->bool_timings.adv_extra_delay = true;
1050         if (dev_t->oe_xdelay)
1051                 gpmc_t->bool_timings.oe_extra_delay = true;
1052         if (dev_t->we_xdelay)
1053                 gpmc_t->bool_timings.we_extra_delay = true;
1054
1055         return 0;
1056 }
1057
1058 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1059                         struct gpmc_device_timings *dev_t)
1060 {
1061         u32 temp;
1062
1063         /* cs_on */
1064         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1065
1066         /* adv_on */
1067         temp = dev_t->t_avdasu;
1068         if (dev_t->t_ce_avd)
1069                 temp = max_t(u32, temp,
1070                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1071         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1072
1073         if (dev_t->sync_write || dev_t->sync_read)
1074                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1075
1076         return 0;
1077 }
1078
1079 /* TODO: remove this function once all peripherals are confirmed to
1080  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1081  * has to be modified to handle timings in ps instead of ns
1082 */
1083 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1084 {
1085         t->cs_on /= 1000;
1086         t->cs_rd_off /= 1000;
1087         t->cs_wr_off /= 1000;
1088         t->adv_on /= 1000;
1089         t->adv_rd_off /= 1000;
1090         t->adv_wr_off /= 1000;
1091         t->we_on /= 1000;
1092         t->we_off /= 1000;
1093         t->oe_on /= 1000;
1094         t->oe_off /= 1000;
1095         t->page_burst_access /= 1000;
1096         t->access /= 1000;
1097         t->rd_cycle /= 1000;
1098         t->wr_cycle /= 1000;
1099         t->bus_turnaround /= 1000;
1100         t->cycle2cycle_delay /= 1000;
1101         t->wait_monitoring /= 1000;
1102         t->clk_activation /= 1000;
1103         t->wr_access /= 1000;
1104         t->wr_data_mux_bus /= 1000;
1105 }
1106
1107 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1108                         struct gpmc_device_timings *dev_t)
1109 {
1110         memset(gpmc_t, 0, sizeof(*gpmc_t));
1111
1112         gpmc_calc_common_timings(gpmc_t, dev_t);
1113
1114         if (dev_t->sync_read)
1115                 gpmc_calc_sync_read_timings(gpmc_t, dev_t);
1116         else
1117                 gpmc_calc_async_read_timings(gpmc_t, dev_t);
1118
1119         if (dev_t->sync_write)
1120                 gpmc_calc_sync_write_timings(gpmc_t, dev_t);
1121         else
1122                 gpmc_calc_async_write_timings(gpmc_t, dev_t);
1123
1124         /* TODO: remove, see function definition */
1125         gpmc_convert_ps_to_ns(gpmc_t);
1126
1127         /* Now the GPMC is initialised, unreserve the chip-selects */
1128         gpmc_cs_map = 0;
1129
1130         return 0;
1131 }
1132
1133 #ifdef CONFIG_OF
1134 static struct of_device_id gpmc_dt_ids[] = {
1135         { .compatible = "ti,omap2420-gpmc" },
1136         { .compatible = "ti,omap2430-gpmc" },
1137         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1138         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1139         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1140         { }
1141 };
1142 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1143
1144 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1145                                                 struct gpmc_timings *gpmc_t)
1146 {
1147         u32 val;
1148
1149         memset(gpmc_t, 0, sizeof(*gpmc_t));
1150
1151         /* minimum clock period for syncronous mode */
1152         if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
1153                 gpmc_t->sync_clk = val;
1154
1155         /* chip select timtings */
1156         if (!of_property_read_u32(np, "gpmc,cs-on", &val))
1157                 gpmc_t->cs_on = val;
1158
1159         if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
1160                 gpmc_t->cs_rd_off = val;
1161
1162         if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
1163                 gpmc_t->cs_wr_off = val;
1164
1165         /* ADV signal timings */
1166         if (!of_property_read_u32(np, "gpmc,adv-on", &val))
1167                 gpmc_t->adv_on = val;
1168
1169         if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
1170                 gpmc_t->adv_rd_off = val;
1171
1172         if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
1173                 gpmc_t->adv_wr_off = val;
1174
1175         /* WE signal timings */
1176         if (!of_property_read_u32(np, "gpmc,we-on", &val))
1177                 gpmc_t->we_on = val;
1178
1179         if (!of_property_read_u32(np, "gpmc,we-off", &val))
1180                 gpmc_t->we_off = val;
1181
1182         /* OE signal timings */
1183         if (!of_property_read_u32(np, "gpmc,oe-on", &val))
1184                 gpmc_t->oe_on = val;
1185
1186         if (!of_property_read_u32(np, "gpmc,oe-off", &val))
1187                 gpmc_t->oe_off = val;
1188
1189         /* access and cycle timings */
1190         if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
1191                 gpmc_t->page_burst_access = val;
1192
1193         if (!of_property_read_u32(np, "gpmc,access", &val))
1194                 gpmc_t->access = val;
1195
1196         if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
1197                 gpmc_t->rd_cycle = val;
1198
1199         if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
1200                 gpmc_t->wr_cycle = val;
1201
1202         /* only for OMAP3430 */
1203         if (!of_property_read_u32(np, "gpmc,wr-access", &val))
1204                 gpmc_t->wr_access = val;
1205
1206         if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
1207                 gpmc_t->wr_data_mux_bus = val;
1208 }
1209
1210 #ifdef CONFIG_MTD_NAND
1211
1212 static const char * const nand_ecc_opts[] = {
1213         [OMAP_ECC_HAMMING_CODE_DEFAULT]         = "sw",
1214         [OMAP_ECC_HAMMING_CODE_HW]              = "hw",
1215         [OMAP_ECC_HAMMING_CODE_HW_ROMCODE]      = "hw-romcode",
1216         [OMAP_ECC_BCH4_CODE_HW]                 = "bch4",
1217         [OMAP_ECC_BCH8_CODE_HW]                 = "bch8",
1218 };
1219
1220 static int gpmc_probe_nand_child(struct platform_device *pdev,
1221                                  struct device_node *child)
1222 {
1223         u32 val;
1224         const char *s;
1225         struct gpmc_timings gpmc_t;
1226         struct omap_nand_platform_data *gpmc_nand_data;
1227
1228         if (of_property_read_u32(child, "reg", &val) < 0) {
1229                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1230                         child->full_name);
1231                 return -ENODEV;
1232         }
1233
1234         gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1235                                       GFP_KERNEL);
1236         if (!gpmc_nand_data)
1237                 return -ENOMEM;
1238
1239         gpmc_nand_data->cs = val;
1240         gpmc_nand_data->of_node = child;
1241
1242         if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
1243                 for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
1244                         if (!strcasecmp(s, nand_ecc_opts[val])) {
1245                                 gpmc_nand_data->ecc_opt = val;
1246                                 break;
1247                         }
1248
1249         val = of_get_nand_bus_width(child);
1250         if (val == 16)
1251                 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1252
1253         gpmc_read_timings_dt(child, &gpmc_t);
1254         gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1255
1256         return 0;
1257 }
1258 #else
1259 static int gpmc_probe_nand_child(struct platform_device *pdev,
1260                                  struct device_node *child)
1261 {
1262         return 0;
1263 }
1264 #endif
1265
1266 static int gpmc_probe_dt(struct platform_device *pdev)
1267 {
1268         int ret;
1269         struct device_node *child;
1270         const struct of_device_id *of_id =
1271                 of_match_device(gpmc_dt_ids, &pdev->dev);
1272
1273         if (!of_id)
1274                 return 0;
1275
1276         for_each_node_by_name(child, "nand") {
1277                 ret = gpmc_probe_nand_child(pdev, child);
1278                 if (ret < 0) {
1279                         of_node_put(child);
1280                         return ret;
1281                 }
1282         }
1283
1284         return 0;
1285 }
1286 #else
1287 static int gpmc_probe_dt(struct platform_device *pdev)
1288 {
1289         return 0;
1290 }
1291 #endif
1292
1293 static int gpmc_probe(struct platform_device *pdev)
1294 {
1295         int rc;
1296         u32 l;
1297         struct resource *res;
1298
1299         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1300         if (res == NULL)
1301                 return -ENOENT;
1302
1303         phys_base = res->start;
1304         mem_size = resource_size(res);
1305
1306         gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
1307         if (!gpmc_base) {
1308                 dev_err(&pdev->dev, "error: request memory / ioremap\n");
1309                 return -EADDRNOTAVAIL;
1310         }
1311
1312         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1313         if (res == NULL)
1314                 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
1315         else
1316                 gpmc_irq = res->start;
1317
1318         gpmc_l3_clk = clk_get(&pdev->dev, "fck");
1319         if (IS_ERR(gpmc_l3_clk)) {
1320                 dev_err(&pdev->dev, "error: clk_get\n");
1321                 gpmc_irq = 0;
1322                 return PTR_ERR(gpmc_l3_clk);
1323         }
1324
1325         clk_prepare_enable(gpmc_l3_clk);
1326
1327         gpmc_dev = &pdev->dev;
1328
1329         l = gpmc_read_reg(GPMC_REVISION);
1330         if (GPMC_REVISION_MAJOR(l) > 0x4)
1331                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
1332         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
1333                  GPMC_REVISION_MINOR(l));
1334
1335         rc = gpmc_mem_init();
1336         if (IS_ERR_VALUE(rc)) {
1337                 clk_disable_unprepare(gpmc_l3_clk);
1338                 clk_put(gpmc_l3_clk);
1339                 dev_err(gpmc_dev, "failed to reserve memory\n");
1340                 return rc;
1341         }
1342
1343         if (IS_ERR_VALUE(gpmc_setup_irq()))
1344                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1345
1346         rc = gpmc_probe_dt(pdev);
1347         if (rc < 0) {
1348                 clk_disable_unprepare(gpmc_l3_clk);
1349                 clk_put(gpmc_l3_clk);
1350                 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1351                 return rc;
1352         }
1353
1354         return 0;
1355 }
1356
1357 static int gpmc_remove(struct platform_device *pdev)
1358 {
1359         gpmc_free_irq();
1360         gpmc_mem_exit();
1361         gpmc_dev = NULL;
1362         return 0;
1363 }
1364
1365 static struct platform_driver gpmc_driver = {
1366         .probe          = gpmc_probe,
1367         .remove         = gpmc_remove,
1368         .driver         = {
1369                 .name   = DEVICE_NAME,
1370                 .owner  = THIS_MODULE,
1371                 .of_match_table = of_match_ptr(gpmc_dt_ids),
1372         },
1373 };
1374
1375 static __init int gpmc_init(void)
1376 {
1377         return platform_driver_register(&gpmc_driver);
1378 }
1379
1380 static __exit void gpmc_exit(void)
1381 {
1382         platform_driver_unregister(&gpmc_driver);
1383
1384 }
1385
1386 postcore_initcall(gpmc_init);
1387 module_exit(gpmc_exit);
1388
1389 static int __init omap_gpmc_init(void)
1390 {
1391         struct omap_hwmod *oh;
1392         struct platform_device *pdev;
1393         char *oh_name = "gpmc";
1394
1395         /*
1396          * if the board boots up with a populated DT, do not
1397          * manually add the device from this initcall
1398          */
1399         if (of_have_populated_dt())
1400                 return -ENODEV;
1401
1402         oh = omap_hwmod_lookup(oh_name);
1403         if (!oh) {
1404                 pr_err("Could not look up %s\n", oh_name);
1405                 return -ENODEV;
1406         }
1407
1408         pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
1409         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
1410
1411         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
1412 }
1413 postcore_initcall(omap_gpmc_init);
1414
1415 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1416 {
1417         int i;
1418         u32 regval;
1419
1420         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1421
1422         if (!regval)
1423                 return IRQ_NONE;
1424
1425         for (i = 0; i < GPMC_NR_IRQ; i++)
1426                 if (regval & gpmc_client_irq[i].bitmask)
1427                         generic_handle_irq(gpmc_client_irq[i].irq);
1428
1429         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1430
1431         return IRQ_HANDLED;
1432 }
1433
1434 #ifdef CONFIG_ARCH_OMAP3
1435 static struct omap3_gpmc_regs gpmc_context;
1436
1437 void omap3_gpmc_save_context(void)
1438 {
1439         int i;
1440
1441         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
1442         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
1443         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
1444         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
1445         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
1446         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
1447         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
1448         for (i = 0; i < GPMC_CS_NUM; i++) {
1449                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
1450                 if (gpmc_context.cs_context[i].is_valid) {
1451                         gpmc_context.cs_context[i].config1 =
1452                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
1453                         gpmc_context.cs_context[i].config2 =
1454                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
1455                         gpmc_context.cs_context[i].config3 =
1456                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
1457                         gpmc_context.cs_context[i].config4 =
1458                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
1459                         gpmc_context.cs_context[i].config5 =
1460                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
1461                         gpmc_context.cs_context[i].config6 =
1462                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
1463                         gpmc_context.cs_context[i].config7 =
1464                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
1465                 }
1466         }
1467 }
1468
1469 void omap3_gpmc_restore_context(void)
1470 {
1471         int i;
1472
1473         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
1474         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
1475         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
1476         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
1477         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
1478         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
1479         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
1480         for (i = 0; i < GPMC_CS_NUM; i++) {
1481                 if (gpmc_context.cs_context[i].is_valid) {
1482                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
1483                                 gpmc_context.cs_context[i].config1);
1484                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
1485                                 gpmc_context.cs_context[i].config2);
1486                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
1487                                 gpmc_context.cs_context[i].config3);
1488                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
1489                                 gpmc_context.cs_context[i].config4);
1490                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
1491                                 gpmc_context.cs_context[i].config5);
1492                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
1493                                 gpmc_context.cs_context[i].config6);
1494                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
1495                                 gpmc_context.cs_context[i].config7);
1496                 }
1497         }
1498 }
1499 #endif /* CONFIG_ARCH_OMAP3 */