arch/arm/mach-omap2/gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #undef DEBUG
  16
  17 #include <linux/irq.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/ioport.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/io.h>
  25 #include <linux/module.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28
  29 #include <linux/platform_data/mtd-nand-omap2.h>
  30
  31 #include <asm/mach-types.h>
  32 #include <plat/gpmc.h>
  33
  34 #include <plat/cpu.h>
  35 #include <plat/gpmc.h>
  36 #include <plat/sdrc.h>
  37 #include <plat/omap_device.h>
  38
  39 #include "soc.h"
  40 #include "common.h"
  41
  42 #define DEVICE_NAME             "omap-gpmc"
  43
  44 /* GPMC register offsets */
  45 #define GPMC_REVISION           0x00
  46 #define GPMC_SYSCONFIG          0x10
  47 #define GPMC_SYSSTATUS          0x14
  48 #define GPMC_IRQSTATUS          0x18
  49 #define GPMC_IRQENABLE          0x1c
  50 #define GPMC_TIMEOUT_CONTROL    0x40
  51 #define GPMC_ERR_ADDRESS        0x44
  52 #define GPMC_ERR_TYPE           0x48
  53 #define GPMC_CONFIG             0x50
  54 #define GPMC_STATUS             0x54
  55 #define GPMC_PREFETCH_CONFIG1   0x1e0
  56 #define GPMC_PREFETCH_CONFIG2   0x1e4
  57 #define GPMC_PREFETCH_CONTROL   0x1ec
  58 #define GPMC_PREFETCH_STATUS    0x1f0
  59 #define GPMC_ECC_CONFIG         0x1f4
  60 #define GPMC_ECC_CONTROL        0x1f8
  61 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  62 #define GPMC_ECC1_RESULT        0x200
  63 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  64
  65 /* GPMC ECC control settings */
  66 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  67 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  68 #define GPMC_ECC_CTRL_ECCREG1           0x001
  69 #define GPMC_ECC_CTRL_ECCREG2           0x002
  70 #define GPMC_ECC_CTRL_ECCREG3           0x003
  71 #define GPMC_ECC_CTRL_ECCREG4           0x004
  72 #define GPMC_ECC_CTRL_ECCREG5           0x005
  73 #define GPMC_ECC_CTRL_ECCREG6           0x006
  74 #define GPMC_ECC_CTRL_ECCREG7           0x007
  75 #define GPMC_ECC_CTRL_ECCREG8           0x008
  76 #define GPMC_ECC_CTRL_ECCREG9           0x009
  77
  78 #define GPMC_CS0_OFFSET         0x60
  79 #define GPMC_CS_SIZE            0x30
  80
  81 #define GPMC_MEM_START          0x00000000
  82 #define GPMC_MEM_END            0x3FFFFFFF
  83 #define BOOT_ROM_SPACE          0x100000        /* 1MB */
  84
  85 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
  86 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
  87
  88 #define CS_NUM_SHIFT            24
  89 #define ENABLE_PREFETCH         (0x1 << 7)
  90 #define DMA_MPU_MODE            2
  91
  92 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
  93 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
  94
  95 #define GPMC_HAS_WR_ACCESS              0x1
  96 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
  97
  98 /* XXX: Only NAND irq has been considered,currently these are the only ones used
  99  */
 100 #define GPMC_NR_IRQ             2
 101
 102 struct gpmc_client_irq  {
 103         unsigned                irq;
 104         u32                     bitmask;
 105 };
 106
 107 /* Structure to save gpmc cs context */
 108 struct gpmc_cs_config {
 109         u32 config1;
 110         u32 config2;
 111         u32 config3;
 112         u32 config4;
 113         u32 config5;
 114         u32 config6;
 115         u32 config7;
 116         int is_valid;
 117 };
 118
 119 /*
 120  * Structure to save/restore gpmc context
 121  * to support core off on OMAP3
 122  */
 123 struct omap3_gpmc_regs {
 124         u32 sysconfig;
 125         u32 irqenable;
 126         u32 timeout_ctrl;
 127         u32 config;
 128         u32 prefetch_config1;
 129         u32 prefetch_config2;
 130         u32 prefetch_control;
 131         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 132 };
 133
 134 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
 135 static struct irq_chip gpmc_irq_chip;
 136 static unsigned gpmc_irq_start;
 137
 138 static struct resource  gpmc_mem_root;
 139 static struct resource  gpmc_cs_mem[GPMC_CS_NUM];
 140 static DEFINE_SPINLOCK(gpmc_mem_lock);
 141 static unsigned int gpmc_cs_map;        /* flag for cs which are initialized */
 142 static int gpmc_ecc_used = -EINVAL;     /* cs using ecc engine */
 143 static struct device *gpmc_dev;
 144 static int gpmc_irq;
 145 static resource_size_t phys_base, mem_size;
 146 static unsigned gpmc_capability;
 147 static void __iomem *gpmc_base;
 148
 149 static struct clk *gpmc_l3_clk;
 150
 151 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 152
 153 static void gpmc_write_reg(int idx, u32 val)
 154 {
 155         __raw_writel(val, gpmc_base + idx);
 156 }
 157
 158 static u32 gpmc_read_reg(int idx)
 159 {
 160         return __raw_readl(gpmc_base + idx);
 161 }
 162
 163 static void gpmc_cs_write_byte(int cs, int idx, u8 val)
 164 {
 165         void __iomem *reg_addr;
 166
 167         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 168         __raw_writeb(val, reg_addr);
 169 }
 170
 171 static u8 gpmc_cs_read_byte(int cs, int idx)
 172 {
 173         void __iomem *reg_addr;
 174
 175         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 176         return __raw_readb(reg_addr);
 177 }
 178
 179 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 180 {
 181         void __iomem *reg_addr;
 182
 183         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 184         __raw_writel(val, reg_addr);
 185 }
 186
 187 u32 gpmc_cs_read_reg(int cs, int idx)
 188 {
 189         void __iomem *reg_addr;
 190
 191         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 192         return __raw_readl(reg_addr);
 193 }
 194
 195 /* TODO: Add support for gpmc_fck to clock framework and use it */
 196 unsigned long gpmc_get_fclk_period(void)
 197 {
 198         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 199
 200         if (rate == 0) {
 201                 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
 202                 return 0;
 203         }
 204
 205         rate /= 1000;
 206         rate = 1000000000 / rate;       /* In picoseconds */
 207
 208         return rate;
 209 }
 210
 211 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 212 {
 213         unsigned long tick_ps;
 214
 215         /* Calculate in picosecs to yield more exact results */
 216         tick_ps = gpmc_get_fclk_period();
 217
 218         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 219 }
 220
 221 unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 222 {
 223         unsigned long tick_ps;
 224
 225         /* Calculate in picosecs to yield more exact results */
 226         tick_ps = gpmc_get_fclk_period();
 227
 228         return (time_ps + tick_ps - 1) / tick_ps;
 229 }
 230
 231 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 232 {
 233         return ticks * gpmc_get_fclk_period() / 1000;
 234 }
 235
 236 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
 237 {
 238         unsigned long ticks = gpmc_ns_to_ticks(time_ns);
 239
 240         return ticks * gpmc_get_fclk_period() / 1000;
 241 }
 242
 243 #ifdef DEBUG
 244 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 245                                int time, const char *name)
 246 #else
 247 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 248                                int time)
 249 #endif
 250 {
 251         u32 l;
 252         int ticks, mask, nr_bits;
 253
 254         if (time == 0)
 255                 ticks = 0;
 256         else
 257                 ticks = gpmc_ns_to_ticks(time);
 258         nr_bits = end_bit - st_bit + 1;
 259         if (ticks >= 1 << nr_bits) {
 260 #ifdef DEBUG
 261                 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
 262                                 cs, name, time, ticks, 1 << nr_bits);
 263 #endif
 264                 return -1;
 265         }
 266
 267         mask = (1 << nr_bits) - 1;
 268         l = gpmc_cs_read_reg(cs, reg);
 269 #ifdef DEBUG
 270         printk(KERN_INFO
 271                 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 272                cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
 273                         (l >> st_bit) & mask, time);
 274 #endif
 275         l &= ~(mask << st_bit);
 276         l |= ticks << st_bit;
 277         gpmc_cs_write_reg(cs, reg, l);
 278
 279         return 0;
 280 }
 281
 282 #ifdef DEBUG
 283 #define GPMC_SET_ONE(reg, st, end, field) \
 284         if (set_gpmc_timing_reg(cs, (reg), (st), (end),         \
 285                         t->field, #field) < 0)                  \
 286                 return -1
 287 #else
 288 #define GPMC_SET_ONE(reg, st, end, field) \
 289         if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
 290                 return -1
 291 #endif
 292
 293 int gpmc_calc_divider(unsigned int sync_clk)
 294 {
 295         int div;
 296         u32 l;
 297
 298         l = sync_clk + (gpmc_get_fclk_period() - 1);
 299         div = l / gpmc_get_fclk_period();
 300         if (div > 4)
 301                 return -1;
 302         if (div <= 0)
 303                 div = 1;
 304
 305         return div;
 306 }
 307
 308 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 309 {
 310         int div;
 311         u32 l;
 312
 313         div = gpmc_calc_divider(t->sync_clk);
 314         if (div < 0)
 315                 return div;
 316
 317         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 318         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 319         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 320
 321         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 322         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 323         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 324
 325         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 326         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 327         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 328         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 329
 330         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 331         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 332         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 333
 334         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 335
 336         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 337                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 338         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 339                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 340
 341         /* caller is expected to have initialized CONFIG1 to cover
 342          * at least sync vs async
 343          */
 344         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 345         if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
 346 #ifdef DEBUG
 347                 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
 348                                 cs, (div * gpmc_get_fclk_period()) / 1000, div);
 349 #endif
 350                 l &= ~0x03;
 351                 l |= (div - 1);
 352                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 353         }
 354
 355         return 0;
 356 }
 357
 358 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
 359 {
 360         u32 l;
 361         u32 mask;
 362
 363         mask = (1 << GPMC_SECTION_SHIFT) - size;
 364         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 365         l &= ~0x3f;
 366         l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
 367         l &= ~(0x0f << 8);
 368         l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
 369         l |= GPMC_CONFIG7_CSVALID;
 370         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 371 }
 372
 373 static void gpmc_cs_disable_mem(int cs)
 374 {
 375         u32 l;
 376
 377         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 378         l &= ~GPMC_CONFIG7_CSVALID;
 379         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 380 }
 381
 382 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 383 {
 384         u32 l;
 385         u32 mask;
 386
 387         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 388         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 389         mask = (l >> 8) & 0x0f;
 390         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 391 }
 392
 393 static int gpmc_cs_mem_enabled(int cs)
 394 {
 395         u32 l;
 396
 397         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 398         return l & GPMC_CONFIG7_CSVALID;
 399 }
 400
 401 int gpmc_cs_set_reserved(int cs, int reserved)
 402 {
 403         if (cs > GPMC_CS_NUM)
 404                 return -ENODEV;
 405
 406         gpmc_cs_map &= ~(1 << cs);
 407         gpmc_cs_map |= (reserved ? 1 : 0) << cs;
 408
 409         return 0;
 410 }
 411
 412 int gpmc_cs_reserved(int cs)
 413 {
 414         if (cs > GPMC_CS_NUM)
 415                 return -ENODEV;
 416
 417         return gpmc_cs_map & (1 << cs);
 418 }
 419
 420 static unsigned long gpmc_mem_align(unsigned long size)
 421 {
 422         int order;
 423
 424         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 425         order = GPMC_CHUNK_SHIFT - 1;
 426         do {
 427                 size >>= 1;
 428                 order++;
 429         } while (size);
 430         size = 1 << order;
 431         return size;
 432 }
 433
 434 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 435 {
 436         struct resource *res = &gpmc_cs_mem[cs];
 437         int r;
 438
 439         size = gpmc_mem_align(size);
 440         spin_lock(&gpmc_mem_lock);
 441         res->start = base;
 442         res->end = base + size - 1;
 443         r = request_resource(&gpmc_mem_root, res);
 444         spin_unlock(&gpmc_mem_lock);
 445
 446         return r;
 447 }
 448
 449 static int gpmc_cs_delete_mem(int cs)
 450 {
 451         struct resource *res = &gpmc_cs_mem[cs];
 452         int r;
 453
 454         spin_lock(&gpmc_mem_lock);
 455         r = release_resource(&gpmc_cs_mem[cs]);
 456         res->start = 0;
 457         res->end = 0;
 458         spin_unlock(&gpmc_mem_lock);
 459
 460         return r;
 461 }
 462
 463 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 464 {
 465         struct resource *res = &gpmc_cs_mem[cs];
 466         int r = -1;
 467
 468         if (cs > GPMC_CS_NUM)
 469                 return -ENODEV;
 470
 471         size = gpmc_mem_align(size);
 472         if (size > (1 << GPMC_SECTION_SHIFT))
 473                 return -ENOMEM;
 474
 475         spin_lock(&gpmc_mem_lock);
 476         if (gpmc_cs_reserved(cs)) {
 477                 r = -EBUSY;
 478                 goto out;
 479         }
 480         if (gpmc_cs_mem_enabled(cs))
 481                 r = adjust_resource(res, res->start & ~(size - 1), size);
 482         if (r < 0)
 483                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
 484                                       size, NULL, NULL);
 485         if (r < 0)
 486                 goto out;
 487
 488         gpmc_cs_enable_mem(cs, res->start, resource_size(res));
 489         *base = res->start;
 490         gpmc_cs_set_reserved(cs, 1);
 491 out:
 492         spin_unlock(&gpmc_mem_lock);
 493         return r;
 494 }
 495 EXPORT_SYMBOL(gpmc_cs_request);
 496
 497 void gpmc_cs_free(int cs)
 498 {
 499         spin_lock(&gpmc_mem_lock);
 500         if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
 501                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
 502                 BUG();
 503                 spin_unlock(&gpmc_mem_lock);
 504                 return;
 505         }
 506         gpmc_cs_disable_mem(cs);
 507         release_resource(&gpmc_cs_mem[cs]);
 508         gpmc_cs_set_reserved(cs, 0);
 509         spin_unlock(&gpmc_mem_lock);
 510 }
 511 EXPORT_SYMBOL(gpmc_cs_free);
 512
 513 /**
 514  * gpmc_read_status - read access request to get the different gpmc status
 515  * @cmd: command type
 516  * @return status
 517  */
 518 int gpmc_read_status(int cmd)
 519 {
 520         int     status = -EINVAL;
 521         u32     regval = 0;
 522
 523         switch (cmd) {
 524         case GPMC_GET_IRQ_STATUS:
 525                 status = gpmc_read_reg(GPMC_IRQSTATUS);
 526                 break;
 527
 528         case GPMC_PREFETCH_FIFO_CNT:
 529                 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
 530                 status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
 531                 break;
 532
 533         case GPMC_PREFETCH_COUNT:
 534                 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
 535                 status = GPMC_PREFETCH_STATUS_COUNT(regval);
 536                 break;
 537
 538         case GPMC_STATUS_BUFFER:
 539                 regval = gpmc_read_reg(GPMC_STATUS);
 540                 /* 1 : buffer is available to write */
 541                 status = regval & GPMC_STATUS_BUFF_EMPTY;
 542                 break;
 543
 544         default:
 545                 printk(KERN_ERR "gpmc_read_status: Not supported\n");
 546         }
 547         return status;
 548 }
 549 EXPORT_SYMBOL(gpmc_read_status);
 550
 551 /**
 552  * gpmc_cs_configure - write request to configure gpmc
 553  * @cs: chip select number
 554  * @cmd: command type
 555  * @wval: value to write
 556  * @return status of the operation
 557  */
 558 int gpmc_cs_configure(int cs, int cmd, int wval)
 559 {
 560         int err = 0;
 561         u32 regval = 0;
 562
 563         switch (cmd) {
 564         case GPMC_ENABLE_IRQ:
 565                 gpmc_write_reg(GPMC_IRQENABLE, wval);
 566                 break;
 567
 568         case GPMC_SET_IRQ_STATUS:
 569                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
 570                 break;
 571
 572         case GPMC_CONFIG_WP:
 573                 regval = gpmc_read_reg(GPMC_CONFIG);
 574                 if (wval)
 575                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
 576                 else
 577                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
 578                 gpmc_write_reg(GPMC_CONFIG, regval);
 579                 break;
 580
 581         case GPMC_CONFIG_RDY_BSY:
 582                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 583                 if (wval)
 584                         regval |= WR_RD_PIN_MONITORING;
 585                 else
 586                         regval &= ~WR_RD_PIN_MONITORING;
 587                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 588                 break;
 589
 590         case GPMC_CONFIG_DEV_SIZE:
 591                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 592
 593                 /* clear 2 target bits */
 594                 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
 595
 596                 /* set the proper value */
 597                 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
 598
 599                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 600                 break;
 601
 602         case GPMC_CONFIG_DEV_TYPE:
 603                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 604                 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
 605                 if (wval == GPMC_DEVICETYPE_NOR)
 606                         regval |= GPMC_CONFIG1_MUXADDDATA;
 607                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 608                 break;
 609
 610         default:
 611                 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
 612                 err = -EINVAL;
 613         }
 614
 615         return err;
 616 }
 617 EXPORT_SYMBOL(gpmc_cs_configure);
 618
 619 /**
 620  * gpmc_nand_read - nand specific read access request
 621  * @cs: chip select number
 622  * @cmd: command type
 623  */
 624 int gpmc_nand_read(int cs, int cmd)
 625 {
 626         int rval = -EINVAL;
 627
 628         switch (cmd) {
 629         case GPMC_NAND_DATA:
 630                 rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
 631                 break;
 632
 633         default:
 634                 printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
 635         }
 636         return rval;
 637 }
 638 EXPORT_SYMBOL(gpmc_nand_read);
 639
 640 /**
 641  * gpmc_nand_write - nand specific write request
 642  * @cs: chip select number
 643  * @cmd: command type
 644  * @wval: value to write
 645  */
 646 int gpmc_nand_write(int cs, int cmd, int wval)
 647 {
 648         int err = 0;
 649
 650         switch (cmd) {
 651         case GPMC_NAND_COMMAND:
 652                 gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
 653                 break;
 654
 655         case GPMC_NAND_ADDRESS:
 656                 gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
 657                 break;
 658
 659         case GPMC_NAND_DATA:
 660                 gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
 661
 662         default:
 663                 printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
 664                 err = -EINVAL;
 665         }
 666         return err;
 667 }
 668 EXPORT_SYMBOL(gpmc_nand_write);
 669
 670
 671
 672 /**
 673  * gpmc_prefetch_enable - configures and starts prefetch transfer
 674  * @cs: cs (chip select) number
 675  * @fifo_th: fifo threshold to be used for read/ write
 676  * @dma_mode: dma mode enable (1) or disable (0)
 677  * @u32_count: number of bytes to be transferred
 678  * @is_write: prefetch read(0) or write post(1) mode
 679  */
 680 int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
 681                                 unsigned int u32_count, int is_write)
 682 {
 683
 684         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
 685                 pr_err("gpmc: fifo threshold is not supported\n");
 686                 return -1;
 687         } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
 688                 /* Set the amount of bytes to be prefetched */
 689                 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
 690
 691                 /* Set dma/mpu mode, the prefetch read / post write and
 692                  * enable the engine. Set which cs is has requested for.
 693                  */
 694                 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
 695                                         PREFETCH_FIFOTHRESHOLD(fifo_th) |
 696                                         ENABLE_PREFETCH |
 697                                         (dma_mode << DMA_MPU_MODE) |
 698                                         (0x1 & is_write)));
 699
 700                 /*  Start the prefetch engine */
 701                 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
 702         } else {
 703                 return -EBUSY;
 704         }
 705
 706         return 0;
 707 }
 708 EXPORT_SYMBOL(gpmc_prefetch_enable);
 709
 710 /**
 711  * gpmc_prefetch_reset - disables and stops the prefetch engine
 712  */
 713 int gpmc_prefetch_reset(int cs)
 714 {
 715         u32 config1;
 716
 717         /* check if the same module/cs is trying to reset */
 718         config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
 719         if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
 720                 return -EINVAL;
 721
 722         /* Stop the PFPW engine */
 723         gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
 724
 725         /* Reset/disable the PFPW engine */
 726         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
 727
 728         return 0;
 729 }
 730 EXPORT_SYMBOL(gpmc_prefetch_reset);
 731
 732 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 733 {
 734         reg->gpmc_status = gpmc_base + GPMC_STATUS;
 735         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
 736                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
 737         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
 738                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
 739         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
 740                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
 741         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
 742         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
 743         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
 744         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
 745         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
 746         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
 747         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
 748         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
 749         reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0;
 750 }
 751
 752 int gpmc_get_client_irq(unsigned irq_config)
 753 {
 754         int i;
 755
 756         if (hweight32(irq_config) > 1)
 757                 return 0;
 758
 759         for (i = 0; i < GPMC_NR_IRQ; i++)
 760                 if (gpmc_client_irq[i].bitmask & irq_config)
 761                         return gpmc_client_irq[i].irq;
 762
 763         return 0;
 764 }
 765
 766 static int gpmc_irq_endis(unsigned irq, bool endis)
 767 {
 768         int i;
 769         u32 regval;
 770
 771         for (i = 0; i < GPMC_NR_IRQ; i++)
 772                 if (irq == gpmc_client_irq[i].irq) {
 773                         regval = gpmc_read_reg(GPMC_IRQENABLE);
 774                         if (endis)
 775                                 regval |= gpmc_client_irq[i].bitmask;
 776                         else
 777                                 regval &= ~gpmc_client_irq[i].bitmask;
 778                         gpmc_write_reg(GPMC_IRQENABLE, regval);
 779                         break;
 780                 }
 781
 782         return 0;
 783 }
 784
 785 static void gpmc_irq_disable(struct irq_data *p)
 786 {
 787         gpmc_irq_endis(p->irq, false);
 788 }
 789
 790 static void gpmc_irq_enable(struct irq_data *p)
 791 {
 792         gpmc_irq_endis(p->irq, true);
 793 }
 794
 795 static void gpmc_irq_noop(struct irq_data *data) { }
 796
 797 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
 798
 799 static int gpmc_setup_irq(void)
 800 {
 801         int i;
 802         u32 regval;
 803
 804         if (!gpmc_irq)
 805                 return -EINVAL;
 806
 807         gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
 808         if (IS_ERR_VALUE(gpmc_irq_start)) {
 809                 pr_err("irq_alloc_descs failed\n");
 810                 return gpmc_irq_start;
 811         }
 812
 813         gpmc_irq_chip.name = "gpmc";
 814         gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
 815         gpmc_irq_chip.irq_enable = gpmc_irq_enable;
 816         gpmc_irq_chip.irq_disable = gpmc_irq_disable;
 817         gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
 818         gpmc_irq_chip.irq_ack = gpmc_irq_noop;
 819         gpmc_irq_chip.irq_mask = gpmc_irq_noop;
 820         gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
 821
 822         gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
 823         gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
 824
 825         for (i = 0; i < GPMC_NR_IRQ; i++) {
 826                 gpmc_client_irq[i].irq = gpmc_irq_start + i;
 827                 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
 828                                         &gpmc_irq_chip, handle_simple_irq);
 829                 set_irq_flags(gpmc_client_irq[i].irq,
 830                                 IRQF_VALID | IRQF_NOAUTOEN);
 831         }
 832
 833         /* Disable interrupts */
 834         gpmc_write_reg(GPMC_IRQENABLE, 0);
 835
 836         /* clear interrupts */
 837         regval = gpmc_read_reg(GPMC_IRQSTATUS);
 838         gpmc_write_reg(GPMC_IRQSTATUS, regval);
 839
 840         return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
 841 }
 842
 843 static __devexit int gpmc_free_irq(void)
 844 {
 845         int i;
 846
 847         if (gpmc_irq)
 848                 free_irq(gpmc_irq, NULL);
 849
 850         for (i = 0; i < GPMC_NR_IRQ; i++) {
 851                 irq_set_handler(gpmc_client_irq[i].irq, NULL);
 852                 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
 853                 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
 854         }
 855
 856         irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
 857
 858         return 0;
 859 }
 860
 861 static void __devexit gpmc_mem_exit(void)
 862 {
 863         int cs;
 864
 865         for (cs = 0; cs < GPMC_CS_NUM; cs++) {
 866                 if (!gpmc_cs_mem_enabled(cs))
 867                         continue;
 868                 gpmc_cs_delete_mem(cs);
 869         }
 870
 871 }
 872
 873 static void __devinit gpmc_mem_init(void)
 874 {
 875         int cs;
 876         unsigned long boot_rom_space = 0;
 877
 878         /* never allocate the first page, to facilitate bug detection;
 879          * even if we didn't boot from ROM.
 880          */
 881         boot_rom_space = BOOT_ROM_SPACE;
 882         /* In apollon the CS0 is mapped as 0x0000 0000 */
 883         if (machine_is_omap_apollon())
 884                 boot_rom_space = 0;
 885         gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
 886         gpmc_mem_root.end = GPMC_MEM_END;
 887
 888         /* Reserve all regions that has been set up by bootloader */
 889         for (cs = 0; cs < GPMC_CS_NUM; cs++) {
 890                 u32 base, size;
 891
 892                 if (!gpmc_cs_mem_enabled(cs))
 893                         continue;
 894                 gpmc_cs_get_memconf(cs, &base, &size);
 895                 if (gpmc_cs_insert_mem(cs, base, size) < 0)
 896                         BUG();
 897         }
 898 }
 899
 900 static __devinit int gpmc_probe(struct platform_device *pdev)
 901 {
 902         u32 l;
 903         struct resource *res;
 904
 905         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 906         if (res == NULL)
 907                 return -ENOENT;
 908
 909         phys_base = res->start;
 910         mem_size = resource_size(res);
 911
 912         gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
 913         if (!gpmc_base) {
 914                 dev_err(&pdev->dev, "error: request memory / ioremap\n");
 915                 return -EADDRNOTAVAIL;
 916         }
 917
 918         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 919         if (res == NULL)
 920                 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
 921         else
 922                 gpmc_irq = res->start;
 923
 924         gpmc_l3_clk = clk_get(&pdev->dev, "fck");
 925         if (IS_ERR(gpmc_l3_clk)) {
 926                 dev_err(&pdev->dev, "error: clk_get\n");
 927                 gpmc_irq = 0;
 928                 return PTR_ERR(gpmc_l3_clk);
 929         }
 930
 931         clk_prepare_enable(gpmc_l3_clk);
 932
 933         gpmc_dev = &pdev->dev;
 934
 935         l = gpmc_read_reg(GPMC_REVISION);
 936         if (GPMC_REVISION_MAJOR(l) > 0x4)
 937                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
 938         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
 939                  GPMC_REVISION_MINOR(l));
 940
 941         gpmc_mem_init();
 942
 943         if (IS_ERR_VALUE(gpmc_setup_irq()))
 944                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
 945
 946         return 0;
 947 }
 948
 949 static __devexit int gpmc_remove(struct platform_device *pdev)
 950 {
 951         gpmc_free_irq();
 952         gpmc_mem_exit();
 953         gpmc_dev = NULL;
 954         return 0;
 955 }
 956
 957 static struct platform_driver gpmc_driver = {
 958         .probe          = gpmc_probe,
 959         .remove         = __devexit_p(gpmc_remove),
 960         .driver         = {
 961                 .name   = DEVICE_NAME,
 962                 .owner  = THIS_MODULE,
 963         },
 964 };
 965
 966 static __init int gpmc_init(void)
 967 {
 968         return platform_driver_register(&gpmc_driver);
 969 }
 970
 971 static __exit void gpmc_exit(void)
 972 {
 973         platform_driver_unregister(&gpmc_driver);
 974
 975 }
 976
 977 postcore_initcall(gpmc_init);
 978 module_exit(gpmc_exit);
 979
 980 static int __init omap_gpmc_init(void)
 981 {
 982         struct omap_hwmod *oh;
 983         struct platform_device *pdev;
 984         char *oh_name = "gpmc";
 985
 986         oh = omap_hwmod_lookup(oh_name);
 987         if (!oh) {
 988                 pr_err("Could not look up %s\n", oh_name);
 989                 return -ENODEV;
 990         }
 991
 992         pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
 993         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
 994
 995         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
 996 }
 997 postcore_initcall(omap_gpmc_init);
 998
 999 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1000 {
1001         int i;
1002         u32 regval;
1003
1004         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1005
1006         if (!regval)
1007                 return IRQ_NONE;
1008
1009         for (i = 0; i < GPMC_NR_IRQ; i++)
1010                 if (regval & gpmc_client_irq[i].bitmask)
1011                         generic_handle_irq(gpmc_client_irq[i].irq);
1012
1013         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1014
1015         return IRQ_HANDLED;
1016 }
1017
1018 #ifdef CONFIG_ARCH_OMAP3
1019 static struct omap3_gpmc_regs gpmc_context;
1020
1021 void omap3_gpmc_save_context(void)
1022 {
1023         int i;
1024
1025         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
1026         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
1027         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
1028         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
1029         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
1030         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
1031         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
1032         for (i = 0; i < GPMC_CS_NUM; i++) {
1033                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
1034                 if (gpmc_context.cs_context[i].is_valid) {
1035                         gpmc_context.cs_context[i].config1 =
1036                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
1037                         gpmc_context.cs_context[i].config2 =
1038                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
1039                         gpmc_context.cs_context[i].config3 =
1040                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
1041                         gpmc_context.cs_context[i].config4 =
1042                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
1043                         gpmc_context.cs_context[i].config5 =
1044                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
1045                         gpmc_context.cs_context[i].config6 =
1046                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
1047                         gpmc_context.cs_context[i].config7 =
1048                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
1049                 }
1050         }
1051 }
1052
1053 void omap3_gpmc_restore_context(void)
1054 {
1055         int i;
1056
1057         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
1058         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
1059         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
1060         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
1061         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
1062         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
1063         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
1064         for (i = 0; i < GPMC_CS_NUM; i++) {
1065                 if (gpmc_context.cs_context[i].is_valid) {
1066                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
1067                                 gpmc_context.cs_context[i].config1);
1068                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
1069                                 gpmc_context.cs_context[i].config2);
1070                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
1071                                 gpmc_context.cs_context[i].config3);
1072                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
1073                                 gpmc_context.cs_context[i].config4);
1074                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
1075                                 gpmc_context.cs_context[i].config5);
1076                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
1077                                 gpmc_context.cs_context[i].config6);
1078                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
1079                                 gpmc_context.cs_context[i].config7);
1080                 }
1081         }
1082 }
1083 #endif /* CONFIG_ARCH_OMAP3 */
1084
1085 /**
1086  * gpmc_enable_hwecc - enable hardware ecc functionality
1087  * @cs: chip select number
1088  * @mode: read/write mode
1089  * @dev_width: device bus width(1 for x16, 0 for x8)
1090  * @ecc_size: bytes for which ECC will be generated
1091  */
1092 int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
1093 {
1094         unsigned int val;
1095
1096         /* check if ecc module is in used */
1097         if (gpmc_ecc_used != -EINVAL)
1098                 return -EINVAL;
1099
1100         gpmc_ecc_used = cs;
1101
1102         /* clear ecc and enable bits */
1103         gpmc_write_reg(GPMC_ECC_CONTROL,
1104                         GPMC_ECC_CTRL_ECCCLEAR |
1105                         GPMC_ECC_CTRL_ECCREG1);
1106
1107         /* program ecc and result sizes */
1108         val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
1109         gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
1110
1111         switch (mode) {
1112         case GPMC_ECC_READ:
1113         case GPMC_ECC_WRITE:
1114                 gpmc_write_reg(GPMC_ECC_CONTROL,
1115                                 GPMC_ECC_CTRL_ECCCLEAR |
1116                                 GPMC_ECC_CTRL_ECCREG1);
1117                 break;
1118         case GPMC_ECC_READSYN:
1119                 gpmc_write_reg(GPMC_ECC_CONTROL,
1120                                 GPMC_ECC_CTRL_ECCCLEAR |
1121                                 GPMC_ECC_CTRL_ECCDISABLE);
1122                 break;
1123         default:
1124                 printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
1125                 break;
1126         }
1127
1128         /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
1129         val = (dev_width << 7) | (cs << 1) | (0x1);
1130         gpmc_write_reg(GPMC_ECC_CONFIG, val);
1131         return 0;
1132 }
1133 EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
1134
1135 /**
1136  * gpmc_calculate_ecc - generate non-inverted ecc bytes
1137  * @cs: chip select number
1138  * @dat: data pointer over which ecc is computed
1139  * @ecc_code: ecc code buffer
1140  *
1141  * Using non-inverted ECC is considered ugly since writing a blank
1142  * page (padding) will clear the ECC bytes. This is not a problem as long
1143  * no one is trying to write data on the seemingly unused page. Reading
1144  * an erased page will produce an ECC mismatch between generated and read
1145  * ECC bytes that has to be dealt with separately.
1146  */
1147 int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
1148 {
1149         unsigned int val = 0x0;
1150
1151         if (gpmc_ecc_used != cs)
1152                 return -EINVAL;
1153
1154         /* read ecc result */
1155         val = gpmc_read_reg(GPMC_ECC1_RESULT);
1156         *ecc_code++ = val;          /* P128e, ..., P1e */
1157         *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
1158         /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
1159         *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
1160
1161         gpmc_ecc_used = -EINVAL;
1162         return 0;
1163 }
1164 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
1165
1166 #ifdef CONFIG_ARCH_OMAP3
1167
1168 /**
1169  * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality
1170  * @cs: chip select number
1171  * @nsectors: how many 512-byte sectors to process
1172  * @nerrors: how many errors to correct per sector (4 or 8)
1173  *
1174  * This function must be executed before any call to gpmc_enable_hwecc_bch.
1175  */
1176 int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors)
1177 {
1178         /* check if ecc module is in use */
1179         if (gpmc_ecc_used != -EINVAL)
1180                 return -EINVAL;
1181
1182         /* support only OMAP3 class */
1183         if (!cpu_is_omap34xx()) {
1184                 printk(KERN_ERR "BCH ecc is not supported on this CPU\n");
1185                 return -EINVAL;
1186         }
1187
1188         /*
1189          * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
1190          * Other chips may be added if confirmed to work.
1191          */
1192         if ((nerrors == 4) &&
1193             (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
1194                 printk(KERN_ERR "BCH 4-bit mode is not supported on this CPU\n");
1195                 return -EINVAL;
1196         }
1197
1198         /* sanity check */
1199         if (nsectors > 8) {
1200                 printk(KERN_ERR "BCH cannot process %d sectors (max is 8)\n",
1201                        nsectors);
1202                 return -EINVAL;
1203         }
1204
1205         return 0;
1206 }
1207 EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch);
1208
1209 /**
1210  * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality
1211  * @cs: chip select number
1212  * @mode: read/write mode
1213  * @dev_width: device bus width(1 for x16, 0 for x8)
1214  * @nsectors: how many 512-byte sectors to process
1215  * @nerrors: how many errors to correct per sector (4 or 8)
1216  */
1217 int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
1218                           int nerrors)
1219 {
1220         unsigned int val;
1221
1222         /* check if ecc module is in use */
1223         if (gpmc_ecc_used != -EINVAL)
1224                 return -EINVAL;
1225
1226         gpmc_ecc_used = cs;
1227
1228         /* clear ecc and enable bits */
1229         gpmc_write_reg(GPMC_ECC_CONTROL, 0x1);
1230
1231         /*
1232          * When using BCH, sector size is hardcoded to 512 bytes.
1233          * Here we are using wrapping mode 6 both for reading and writing, with:
1234          *  size0 = 0  (no additional protected byte in spare area)
1235          *  size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1236          */
1237         gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, (32 << 22) | (0 << 12));
1238
1239         /* BCH configuration */
1240         val = ((1                        << 16) | /* enable BCH */
1241                (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1242                (0x06                     <<  8) | /* wrap mode = 6 */
1243                (dev_width                <<  7) | /* bus width */
1244                (((nsectors-1) & 0x7)     <<  4) | /* number of sectors */
1245                (cs                       <<  1) | /* ECC CS */
1246                (0x1));                            /* enable ECC */
1247
1248         gpmc_write_reg(GPMC_ECC_CONFIG, val);
1249         gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
1250         return 0;
1251 }
1252 EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch);
1253
1254 /**
1255  * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes
1256  * @cs:  chip select number
1257  * @dat: The pointer to data on which ecc is computed
1258  * @ecc: The ecc output buffer
1259  */
1260 int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc)
1261 {
1262         int i;
1263         unsigned long nsectors, reg, val1, val2;
1264
1265         if (gpmc_ecc_used != cs)
1266                 return -EINVAL;
1267
1268         nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1269
1270         for (i = 0; i < nsectors; i++) {
1271
1272                 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1273
1274                 /* Read hw-computed remainder */
1275                 val1 = gpmc_read_reg(reg + 0);
1276                 val2 = gpmc_read_reg(reg + 4);
1277
1278                 /*
1279                  * Add constant polynomial to remainder, in order to get an ecc
1280                  * sequence of 0xFFs for a buffer filled with 0xFFs; and
1281                  * left-justify the resulting polynomial.
1282                  */
1283                 *ecc++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1284                 *ecc++ = 0x13 ^ ((val2 >>  4) & 0xFF);
1285                 *ecc++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1286                 *ecc++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1287                 *ecc++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1288                 *ecc++ = 0xac ^ ((val1 >> 4) & 0xFF);
1289                 *ecc++ = 0x7f ^ ((val1 & 0xF) << 4);
1290         }
1291
1292         gpmc_ecc_used = -EINVAL;
1293         return 0;
1294 }
1295 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4);
1296
1297 /**
1298  * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes
1299  * @cs:  chip select number
1300  * @dat: The pointer to data on which ecc is computed
1301  * @ecc: The ecc output buffer
1302  */
1303 int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc)
1304 {
1305         int i;
1306         unsigned long nsectors, reg, val1, val2, val3, val4;
1307
1308         if (gpmc_ecc_used != cs)
1309                 return -EINVAL;
1310
1311         nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1312
1313         for (i = 0; i < nsectors; i++) {
1314
1315                 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1316
1317                 /* Read hw-computed remainder */
1318                 val1 = gpmc_read_reg(reg + 0);
1319                 val2 = gpmc_read_reg(reg + 4);
1320                 val3 = gpmc_read_reg(reg + 8);
1321                 val4 = gpmc_read_reg(reg + 12);
1322
1323                 /*
1324                  * Add constant polynomial to remainder, in order to get an ecc
1325                  * sequence of 0xFFs for a buffer filled with 0xFFs.
1326                  */
1327                 *ecc++ = 0xef ^ (val4 & 0xFF);
1328                 *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1329                 *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1330                 *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1331                 *ecc++ = 0xed ^ (val3 & 0xFF);
1332                 *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1333                 *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1334                 *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1335                 *ecc++ = 0x97 ^ (val2 & 0xFF);
1336                 *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1337                 *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1338                 *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1339                 *ecc++ = 0xb5 ^ (val1 & 0xFF);
1340         }
1341
1342         gpmc_ecc_used = -EINVAL;
1343         return 0;
1344 }
1345 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8);
1346
1347 #endif /* CONFIG_ARCH_OMAP3 */