arch/arm/mach-omap2/id.c

   1 /*
   2  * linux/arch/arm/mach-omap2/id.c
   3  *
   4  * OMAP2 CPU identification code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009-11 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/cputype.h>
  23
  24 #include "common.h"
  25 #include <plat/cpu.h>
  26
  27 #include <mach/id.h>
  28
  29 #include "control.h"
  30
  31 static unsigned int omap_revision;
  32 static const char *cpu_rev;
  33 u32 omap_features;
  34
  35 unsigned int omap_rev(void)
  36 {
  37         return omap_revision;
  38 }
  39 EXPORT_SYMBOL(omap_rev);
  40
  41 int omap_type(void)
  42 {
  43         u32 val = 0;
  44
  45         if (cpu_is_omap24xx()) {
  46                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
  47         } else if (soc_is_am33xx()) {
  48                 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
  49         } else if (cpu_is_omap34xx()) {
  50                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
  51         } else if (cpu_is_omap44xx()) {
  52                 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
  53         } else if (soc_is_omap54xx()) {
  54                 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
  55                 val &= OMAP5_DEVICETYPE_MASK;
  56                 val >>= 6;
  57                 goto out;
  58         } else {
  59                 pr_err("Cannot detect omap type!\n");
  60                 goto out;
  61         }
  62
  63         val &= OMAP2_DEVICETYPE_MASK;
  64         val >>= 8;
  65
  66 out:
  67         return val;
  68 }
  69 EXPORT_SYMBOL(omap_type);
  70
  71
  72 /*----------------------------------------------------------------------------*/
  73
  74 #define OMAP_TAP_IDCODE         0x0204
  75 #define OMAP_TAP_DIE_ID_0       0x0218
  76 #define OMAP_TAP_DIE_ID_1       0x021C
  77 #define OMAP_TAP_DIE_ID_2       0x0220
  78 #define OMAP_TAP_DIE_ID_3       0x0224
  79
  80 #define OMAP_TAP_DIE_ID_44XX_0  0x0200
  81 #define OMAP_TAP_DIE_ID_44XX_1  0x0208
  82 #define OMAP_TAP_DIE_ID_44XX_2  0x020c
  83 #define OMAP_TAP_DIE_ID_44XX_3  0x0210
  84
  85 #define read_tap_reg(reg)       __raw_readl(tap_base  + (reg))
  86
  87 struct omap_id {
  88         u16     hawkeye;        /* Silicon type (Hawkeye id) */
  89         u8      dev;            /* Device type from production_id reg */
  90         u32     type;           /* Combined type id copied to omap_revision */
  91 };
  92
  93 /* Register values to detect the OMAP version */
  94 static struct omap_id omap_ids[] __initdata = {
  95         { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
  96         { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
  97         { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
  98         { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
  99         { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
 100         { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
 101 };
 102
 103 static void __iomem *tap_base;
 104 static u16 tap_prod_id;
 105
 106 void omap_get_die_id(struct omap_die_id *odi)
 107 {
 108         if (cpu_is_omap44xx() || soc_is_omap54xx()) {
 109                 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
 110                 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
 111                 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
 112                 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
 113
 114                 return;
 115         }
 116         odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
 117         odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
 118         odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
 119         odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
 120 }
 121
 122 void __init omap2xxx_check_revision(void)
 123 {
 124         int i, j;
 125         u32 idcode, prod_id;
 126         u16 hawkeye;
 127         u8  dev_type, rev;
 128         struct omap_die_id odi;
 129
 130         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 131         prod_id = read_tap_reg(tap_prod_id);
 132         hawkeye = (idcode >> 12) & 0xffff;
 133         rev = (idcode >> 28) & 0x0f;
 134         dev_type = (prod_id >> 16) & 0x0f;
 135         omap_get_die_id(&odi);
 136
 137         pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
 138                  idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
 139         pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
 140         pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
 141                  odi.id_1, (odi.id_1 >> 28) & 0xf);
 142         pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
 143         pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
 144         pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
 145                  prod_id, dev_type);
 146
 147         /* Check hawkeye ids */
 148         for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
 149                 if (hawkeye == omap_ids[i].hawkeye)
 150                         break;
 151         }
 152
 153         if (i == ARRAY_SIZE(omap_ids)) {
 154                 printk(KERN_ERR "Unknown OMAP CPU id\n");
 155                 return;
 156         }
 157
 158         for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
 159                 if (dev_type == omap_ids[j].dev)
 160                         break;
 161         }
 162
 163         if (j == ARRAY_SIZE(omap_ids)) {
 164                 printk(KERN_ERR "Unknown OMAP device type. "
 165                                 "Handling it as OMAP%04x\n",
 166                                 omap_ids[i].type >> 16);
 167                 j = i;
 168         }
 169
 170         pr_info("OMAP%04x", omap_rev() >> 16);
 171         if ((omap_rev() >> 8) & 0x0f)
 172                 pr_info("ES%x", (omap_rev() >> 12) & 0xf);
 173         pr_info("\n");
 174 }
 175
 176 #define OMAP3_SHOW_FEATURE(feat)                \
 177         if (omap3_has_ ##feat())                \
 178                 printk(#feat" ");
 179
 180 static void __init omap3_cpuinfo(void)
 181 {
 182         const char *cpu_name;
 183
 184         /*
 185          * OMAP3430 and OMAP3530 are assumed to be same.
 186          *
 187          * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
 188          * on available features. Upon detection, update the CPU id
 189          * and CPU class bits.
 190          */
 191         if (cpu_is_omap3630()) {
 192                 cpu_name = "OMAP3630";
 193         } else if (soc_is_am35xx()) {
 194                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
 195         } else if (cpu_is_ti816x()) {
 196                 cpu_name = "TI816X";
 197         } else if (soc_is_am335x()) {
 198                 cpu_name =  "AM335X";
 199         } else if (cpu_is_ti814x()) {
 200                 cpu_name = "TI814X";
 201         } else if (omap3_has_iva() && omap3_has_sgx()) {
 202                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
 203                 cpu_name = "OMAP3430/3530";
 204         } else if (omap3_has_iva()) {
 205                 cpu_name = "OMAP3525";
 206         } else if (omap3_has_sgx()) {
 207                 cpu_name = "OMAP3515";
 208         } else {
 209                 cpu_name = "OMAP3503";
 210         }
 211
 212         /* Print verbose information */
 213         pr_info("%s ES%s (", cpu_name, cpu_rev);
 214
 215         OMAP3_SHOW_FEATURE(l2cache);
 216         OMAP3_SHOW_FEATURE(iva);
 217         OMAP3_SHOW_FEATURE(sgx);
 218         OMAP3_SHOW_FEATURE(neon);
 219         OMAP3_SHOW_FEATURE(isp);
 220         OMAP3_SHOW_FEATURE(192mhz_clk);
 221
 222         printk(")\n");
 223 }
 224
 225 #define OMAP3_CHECK_FEATURE(status,feat)                                \
 226         if (((status & OMAP3_ ##feat## _MASK)                           \
 227                 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
 228                 omap_features |= OMAP3_HAS_ ##feat;                     \
 229         }
 230
 231 void __init omap3xxx_check_features(void)
 232 {
 233         u32 status;
 234
 235         omap_features = 0;
 236
 237         status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
 238
 239         OMAP3_CHECK_FEATURE(status, L2CACHE);
 240         OMAP3_CHECK_FEATURE(status, IVA);
 241         OMAP3_CHECK_FEATURE(status, SGX);
 242         OMAP3_CHECK_FEATURE(status, NEON);
 243         OMAP3_CHECK_FEATURE(status, ISP);
 244         if (cpu_is_omap3630())
 245                 omap_features |= OMAP3_HAS_192MHZ_CLK;
 246         if (cpu_is_omap3430() || cpu_is_omap3630())
 247                 omap_features |= OMAP3_HAS_IO_WAKEUP;
 248         if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
 249             omap_rev() == OMAP3430_REV_ES3_1_2)
 250                 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
 251
 252         omap_features |= OMAP3_HAS_SDRC;
 253
 254         /*
 255          * am35x fixups:
 256          * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
 257          *   reserved and therefore return 0 when read.  Unfortunately,
 258          *   OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
 259          *   mean that a feature is present even though it isn't so clear
 260          *   the incorrectly set feature bits.
 261          */
 262         if (soc_is_am35xx())
 263                 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
 264
 265         /*
 266          * TODO: Get additional info (where applicable)
 267          *       e.g. Size of L2 cache.
 268          */
 269
 270         omap3_cpuinfo();
 271 }
 272
 273 void __init omap4xxx_check_features(void)
 274 {
 275         u32 si_type;
 276
 277         if (cpu_is_omap443x())
 278                 omap_features |= OMAP4_HAS_MPU_1GHZ;
 279
 280
 281         if (cpu_is_omap446x()) {
 282                 si_type =
 283                         read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
 284                 switch ((si_type & (3 << 16)) >> 16) {
 285                 case 2:
 286                         /* High performance device */
 287                         omap_features |= OMAP4_HAS_MPU_1_5GHZ;
 288                         break;
 289                 case 1:
 290                 default:
 291                         /* Standard device */
 292                         omap_features |= OMAP4_HAS_MPU_1_2GHZ;
 293                         break;
 294                 }
 295         }
 296 }
 297
 298 void __init ti81xx_check_features(void)
 299 {
 300         omap_features = OMAP3_HAS_NEON;
 301         omap3_cpuinfo();
 302 }
 303
 304 void __init omap3xxx_check_revision(void)
 305 {
 306         u32 cpuid, idcode;
 307         u16 hawkeye;
 308         u8 rev;
 309
 310         /*
 311          * We cannot access revision registers on ES1.0.
 312          * If the processor type is Cortex-A8 and the revision is 0x0
 313          * it means its Cortex r0p0 which is 3430 ES1.0.
 314          */
 315         cpuid = read_cpuid(CPUID_ID);
 316         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
 317                 omap_revision = OMAP3430_REV_ES1_0;
 318                 cpu_rev = "1.0";
 319                 return;
 320         }
 321
 322         /*
 323          * Detection for 34xx ES2.0 and above can be done with just
 324          * hawkeye and rev. See TRM 1.5.2 Device Identification.
 325          * Note that rev does not map directly to our defined processor
 326          * revision numbers as ES1.0 uses value 0.
 327          */
 328         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 329         hawkeye = (idcode >> 12) & 0xffff;
 330         rev = (idcode >> 28) & 0xff;
 331
 332         switch (hawkeye) {
 333         case 0xb7ae:
 334                 /* Handle 34xx/35xx devices */
 335                 switch (rev) {
 336                 case 0: /* Take care of early samples */
 337                 case 1:
 338                         omap_revision = OMAP3430_REV_ES2_0;
 339                         cpu_rev = "2.0";
 340                         break;
 341                 case 2:
 342                         omap_revision = OMAP3430_REV_ES2_1;
 343                         cpu_rev = "2.1";
 344                         break;
 345                 case 3:
 346                         omap_revision = OMAP3430_REV_ES3_0;
 347                         cpu_rev = "3.0";
 348                         break;
 349                 case 4:
 350                         omap_revision = OMAP3430_REV_ES3_1;
 351                         cpu_rev = "3.1";
 352                         break;
 353                 case 7:
 354                 /* FALLTHROUGH */
 355                 default:
 356                         /* Use the latest known revision as default */
 357                         omap_revision = OMAP3430_REV_ES3_1_2;
 358                         cpu_rev = "3.1.2";
 359                 }
 360                 break;
 361         case 0xb868:
 362                 /*
 363                  * Handle OMAP/AM 3505/3517 devices
 364                  *
 365                  * Set the device to be OMAP3517 here. Actual device
 366                  * is identified later based on the features.
 367                  */
 368                 switch (rev) {
 369                 case 0:
 370                         omap_revision = AM35XX_REV_ES1_0;
 371                         cpu_rev = "1.0";
 372                         break;
 373                 case 1:
 374                 /* FALLTHROUGH */
 375                 default:
 376                         omap_revision = AM35XX_REV_ES1_1;
 377                         cpu_rev = "1.1";
 378                 }
 379                 break;
 380         case 0xb891:
 381                 /* Handle 36xx devices */
 382
 383                 switch(rev) {
 384                 case 0: /* Take care of early samples */
 385                         omap_revision = OMAP3630_REV_ES1_0;
 386                         cpu_rev = "1.0";
 387                         break;
 388                 case 1:
 389                         omap_revision = OMAP3630_REV_ES1_1;
 390                         cpu_rev = "1.1";
 391                         break;
 392                 case 2:
 393                 /* FALLTHROUGH */
 394                 default:
 395                         omap_revision = OMAP3630_REV_ES1_2;
 396                         cpu_rev = "1.2";
 397                 }
 398                 break;
 399         case 0xb81e:
 400                 switch (rev) {
 401                 case 0:
 402                         omap_revision = TI8168_REV_ES1_0;
 403                         cpu_rev = "1.0";
 404                         break;
 405                 case 1:
 406                 /* FALLTHROUGH */
 407                 default:
 408                         omap_revision = TI8168_REV_ES1_1;
 409                         cpu_rev = "1.1";
 410                         break;
 411                 }
 412                 break;
 413         case 0xb944:
 414                 omap_revision = AM335X_REV_ES1_0;
 415                 cpu_rev = "1.0";
 416                 break;
 417         case 0xb8f2:
 418                 switch (rev) {
 419                 case 0:
 420                 /* FALLTHROUGH */
 421                 case 1:
 422                         omap_revision = TI8148_REV_ES1_0;
 423                         cpu_rev = "1.0";
 424                         break;
 425                 case 2:
 426                         omap_revision = TI8148_REV_ES2_0;
 427                         cpu_rev = "2.0";
 428                         break;
 429                 case 3:
 430                 /* FALLTHROUGH */
 431                 default:
 432                         omap_revision = TI8148_REV_ES2_1;
 433                         cpu_rev = "2.1";
 434                         break;
 435                 }
 436                 break;
 437         default:
 438                 /* Unknown default to latest silicon rev as default */
 439                 omap_revision = OMAP3630_REV_ES1_2;
 440                 cpu_rev = "1.2";
 441                 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
 442         }
 443 }
 444
 445 void __init omap4xxx_check_revision(void)
 446 {
 447         u32 idcode;
 448         u16 hawkeye;
 449         u8 rev;
 450
 451         /*
 452          * The IC rev detection is done with hawkeye and rev.
 453          * Note that rev does not map directly to defined processor
 454          * revision numbers as ES1.0 uses value 0.
 455          */
 456         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 457         hawkeye = (idcode >> 12) & 0xffff;
 458         rev = (idcode >> 28) & 0xf;
 459
 460         /*
 461          * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
 462          * Use ARM register to detect the correct ES version
 463          */
 464         if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
 465                 idcode = read_cpuid(CPUID_ID);
 466                 rev = (idcode & 0xf) - 1;
 467         }
 468
 469         switch (hawkeye) {
 470         case 0xb852:
 471                 switch (rev) {
 472                 case 0:
 473                         omap_revision = OMAP4430_REV_ES1_0;
 474                         break;
 475                 case 1:
 476                 default:
 477                         omap_revision = OMAP4430_REV_ES2_0;
 478                 }
 479                 break;
 480         case 0xb95c:
 481                 switch (rev) {
 482                 case 3:
 483                         omap_revision = OMAP4430_REV_ES2_1;
 484                         break;
 485                 case 4:
 486                         omap_revision = OMAP4430_REV_ES2_2;
 487                         break;
 488                 case 6:
 489                 default:
 490                         omap_revision = OMAP4430_REV_ES2_3;
 491                 }
 492                 break;
 493         case 0xb94e:
 494                 switch (rev) {
 495                 case 0:
 496                         omap_revision = OMAP4460_REV_ES1_0;
 497                         break;
 498                 case 2:
 499                 default:
 500                         omap_revision = OMAP4460_REV_ES1_1;
 501                         break;
 502                 }
 503                 break;
 504         case 0xb975:
 505                 switch (rev) {
 506                 case 0:
 507                 default:
 508                         omap_revision = OMAP4470_REV_ES1_0;
 509                         break;
 510                 }
 511                 break;
 512         default:
 513                 /* Unknown default to latest silicon rev as default */
 514                 omap_revision = OMAP4430_REV_ES2_3;
 515         }
 516
 517         pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
 518                 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
 519 }
 520
 521 void __init omap5xxx_check_revision(void)
 522 {
 523         u32 idcode;
 524         u16 hawkeye;
 525         u8 rev;
 526
 527         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 528         hawkeye = (idcode >> 12) & 0xffff;
 529         rev = (idcode >> 28) & 0xff;
 530         switch (hawkeye) {
 531         case 0xb942:
 532                 switch (rev) {
 533                 case 0:
 534                 default:
 535                         omap_revision = OMAP5430_REV_ES1_0;
 536                 }
 537                 break;
 538
 539         case 0xb998:
 540                 switch (rev) {
 541                 case 0:
 542                 default:
 543                         omap_revision = OMAP5432_REV_ES1_0;
 544                 }
 545                 break;
 546
 547         default:
 548                 /* Unknown default to latest silicon rev as default*/
 549                 omap_revision = OMAP5430_REV_ES1_0;
 550         }
 551
 552         pr_info("OMAP%04x ES%d.0\n",
 553                         omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
 554 }
 555
 556 /*
 557  * Set up things for map_io and processor detection later on. Gets called
 558  * pretty much first thing from board init. For multi-omap, this gets
 559  * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 560  * detect the exact revision later on in omap2_detect_revision() once map_io
 561  * is done.
 562  */
 563 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
 564 {
 565         omap_revision = omap2_globals->class;
 566         tap_base = omap2_globals->tap;
 567
 568         if (cpu_is_omap34xx())
 569                 tap_prod_id = 0x0210;
 570         else
 571                 tap_prod_id = 0x0208;
 572 }