2 * omap iommu: omap2/3 architecture specific functions
4 * Copyright (C) 2008-2009 Nokia Corporation
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/err.h>
15 #include <linux/device.h>
16 #include <linux/jiffies.h>
17 #include <linux/module.h>
18 #include <linux/omap-iommu.h>
19 #include <linux/slab.h>
20 #include <linux/stringify.h>
22 #include <plat/iommu.h>
25 * omap2 architecture specific register bit definitions
27 #define IOMMU_ARCH_VERSION 0x00000011
30 #define MMU_SYS_IDLE_SHIFT 3
31 #define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT)
32 #define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT)
33 #define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT)
34 #define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT)
36 #define MMU_SYS_SOFTRESET (1 << 1)
37 #define MMU_SYS_AUTOIDLE 1
40 #define MMU_SYS_RESETDONE 1
42 /* IRQSTATUS & IRQENABLE */
43 #define MMU_IRQ_MULTIHITFAULT (1 << 4)
44 #define MMU_IRQ_TABLEWALKFAULT (1 << 3)
45 #define MMU_IRQ_EMUMISS (1 << 2)
46 #define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
47 #define MMU_IRQ_TLBMISS (1 << 0)
49 #define __MMU_IRQ_FAULT \
50 (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
51 #define MMU_IRQ_MASK \
52 (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
53 #define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
54 #define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
57 #define MMU_CNTL_SHIFT 1
58 #define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
59 #define MMU_CNTL_EML_TLB (1 << 3)
60 #define MMU_CNTL_TWL_EN (1 << 2)
61 #define MMU_CNTL_MMU_EN (1 << 1)
63 #define get_cam_va_mask(pgsz) \
64 (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
65 ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
66 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
67 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
70 static void __iommu_set_twl(struct omap_iommu *obj, bool on)
72 u32 l = iommu_read_reg(obj, MMU_CNTL);
75 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
77 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
81 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
83 l |= (MMU_CNTL_MMU_EN);
85 iommu_write_reg(obj, l, MMU_CNTL);
89 static int omap2_iommu_enable(struct omap_iommu *obj)
92 unsigned long timeout;
94 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
97 pa = virt_to_phys(obj->iopgd);
98 if (!IS_ALIGNED(pa, SZ_16K))
101 iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
103 timeout = jiffies + msecs_to_jiffies(20);
105 l = iommu_read_reg(obj, MMU_SYSSTATUS);
106 if (l & MMU_SYS_RESETDONE)
108 } while (!time_after(jiffies, timeout));
110 if (!(l & MMU_SYS_RESETDONE)) {
111 dev_err(obj->dev, "can't take mmu out of reset\n");
115 l = iommu_read_reg(obj, MMU_REVISION);
116 dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
117 (l >> 4) & 0xf, l & 0xf);
119 l = iommu_read_reg(obj, MMU_SYSCONFIG);
120 l &= ~MMU_SYS_IDLE_MASK;
121 l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
122 iommu_write_reg(obj, l, MMU_SYSCONFIG);
124 iommu_write_reg(obj, pa, MMU_TTB);
126 __iommu_set_twl(obj, true);
131 static void omap2_iommu_disable(struct omap_iommu *obj)
133 u32 l = iommu_read_reg(obj, MMU_CNTL);
136 iommu_write_reg(obj, l, MMU_CNTL);
137 iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
139 dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
142 static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
144 __iommu_set_twl(obj, false);
147 static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra)
152 stat = iommu_read_reg(obj, MMU_IRQSTATUS);
153 stat &= MMU_IRQ_MASK;
159 da = iommu_read_reg(obj, MMU_FAULT_AD);
162 if (stat & MMU_IRQ_TLBMISS)
163 errs |= OMAP_IOMMU_ERR_TLB_MISS;
164 if (stat & MMU_IRQ_TRANSLATIONFAULT)
165 errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
166 if (stat & MMU_IRQ_EMUMISS)
167 errs |= OMAP_IOMMU_ERR_EMU_MISS;
168 if (stat & MMU_IRQ_TABLEWALKFAULT)
169 errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
170 if (stat & MMU_IRQ_MULTIHITFAULT)
171 errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
172 iommu_write_reg(obj, stat, MMU_IRQSTATUS);
177 static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
179 cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
180 cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
183 static void omap2_tlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
185 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
186 iommu_write_reg(obj, cr->ram, MMU_RAM);
189 static u32 omap2_cr_to_virt(struct cr_regs *cr)
191 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
192 u32 mask = get_cam_va_mask(cr->cam & page_size);
194 return cr->cam & mask;
197 static struct cr_regs *omap2_alloc_cr(struct omap_iommu *obj,
198 struct iotlb_entry *e)
202 if (e->da & ~(get_cam_va_mask(e->pgsz))) {
203 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
205 return ERR_PTR(-EINVAL);
208 cr = kmalloc(sizeof(*cr), GFP_KERNEL);
210 return ERR_PTR(-ENOMEM);
212 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
213 cr->ram = e->pa | e->endian | e->elsz | e->mixed;
218 static inline int omap2_cr_valid(struct cr_regs *cr)
220 return cr->cam & MMU_CAM_V;
223 static u32 omap2_get_pte_attr(struct iotlb_entry *e)
227 attr = e->mixed << 5;
229 attr |= e->elsz >> 3;
230 attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
231 (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
236 omap2_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, char *buf)
240 /* FIXME: Need more detail analysis of cam/ram */
241 p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
242 (cr->cam & MMU_CAM_P) ? 1 : 0);
247 #define pr_reg(name) \
250 const char *str = "%20s: %08x\n"; \
251 const int maxcol = 32; \
252 bytes = snprintf(p, maxcol, str, __stringify(name), \
253 iommu_read_reg(obj, MMU_##name)); \
261 omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len)
282 pr_reg(EMU_FAULT_AD);
287 static void omap2_iommu_save_ctx(struct omap_iommu *obj)
292 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
293 p[i] = iommu_read_reg(obj, i * sizeof(u32));
294 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
297 BUG_ON(p[0] != IOMMU_ARCH_VERSION);
300 static void omap2_iommu_restore_ctx(struct omap_iommu *obj)
305 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
306 iommu_write_reg(obj, p[i], i * sizeof(u32));
307 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
310 BUG_ON(p[0] != IOMMU_ARCH_VERSION);
313 static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
315 e->da = cr->cam & MMU_CAM_VATAG_MASK;
316 e->pa = cr->ram & MMU_RAM_PADDR_MASK;
317 e->valid = cr->cam & MMU_CAM_V;
318 e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK;
319 e->endian = cr->ram & MMU_RAM_ENDIAN_MASK;
320 e->elsz = cr->ram & MMU_RAM_ELSZ_MASK;
321 e->mixed = cr->ram & MMU_RAM_MIXED;
324 static const struct iommu_functions omap2_iommu_ops = {
325 .version = IOMMU_ARCH_VERSION,
327 .enable = omap2_iommu_enable,
328 .disable = omap2_iommu_disable,
329 .set_twl = omap2_iommu_set_twl,
330 .fault_isr = omap2_iommu_fault_isr,
332 .tlb_read_cr = omap2_tlb_read_cr,
333 .tlb_load_cr = omap2_tlb_load_cr,
335 .cr_to_e = omap2_cr_to_e,
336 .cr_to_virt = omap2_cr_to_virt,
337 .alloc_cr = omap2_alloc_cr,
338 .cr_valid = omap2_cr_valid,
339 .dump_cr = omap2_dump_cr,
341 .get_pte_attr = omap2_get_pte_attr,
343 .save_ctx = omap2_iommu_save_ctx,
344 .restore_ctx = omap2_iommu_restore_ctx,
345 .dump_ctx = omap2_iommu_dump_ctx,
348 static int __init omap2_iommu_init(void)
350 return omap_install_iommu_arch(&omap2_iommu_ops);
352 module_init(omap2_iommu_init);
354 static void __exit omap2_iommu_exit(void)
356 omap_uninstall_iommu_arch(&omap2_iommu_ops);
358 module_exit(omap2_iommu_exit);
360 MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
361 MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
362 MODULE_LICENSE("GPL v2");