2 * Mailbox reservation modules for OMAP2/3
4 * Copyright (C) 2006-2009 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/kernel.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/platform_device.h>
18 #include <plat/mailbox.h>
19 #include <mach/irqs.h>
21 #define MAILBOX_REVISION 0x000
22 #define MAILBOX_SYSCONFIG 0x010
23 #define MAILBOX_SYSSTATUS 0x014
24 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
25 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
26 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
27 #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
28 #define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
30 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
31 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
32 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
34 #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
35 #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
37 /* SYSCONFIG: register bit definition */
38 #define AUTOIDLE (1 << 0)
39 #define SOFTRESET (1 << 1)
40 #define SMARTIDLE (2 << 3)
41 #define OMAP4_SOFTRESET (1 << 0)
42 #define OMAP4_NOIDLE (1 << 2)
43 #define OMAP4_SMARTIDLE (2 << 2)
45 /* SYSSTATUS: register bit definition */
46 #define RESETDONE (1 << 0)
48 #define MBOX_REG_SIZE 0x120
50 #define OMAP4_MBOX_REG_SIZE 0x130
52 #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
53 #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
55 static void __iomem *mbox_base;
57 struct omap_mbox2_fifo {
59 unsigned long fifo_stat;
60 unsigned long msg_stat;
63 struct omap_mbox2_priv {
64 struct omap_mbox2_fifo tx_fifo;
65 struct omap_mbox2_fifo rx_fifo;
66 unsigned long irqenable;
67 unsigned long irqstatus;
70 u32 ctx[OMAP4_MBOX_NR_REGS];
71 unsigned long irqdisable;
74 static struct clk *mbox_ick_handle;
76 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
77 omap_mbox_type_t irq);
79 static inline unsigned int mbox_read_reg(size_t ofs)
81 return __raw_readl(mbox_base + ofs);
84 static inline void mbox_write_reg(u32 val, size_t ofs)
86 __raw_writel(val, mbox_base + ofs);
89 /* Mailbox H/W preparations */
90 static int omap2_mbox_startup(struct omap_mbox *mbox)
93 unsigned long timeout;
95 mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
96 if (IS_ERR(mbox_ick_handle)) {
97 printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
98 PTR_ERR(mbox_ick_handle));
99 return PTR_ERR(mbox_ick_handle);
101 clk_enable(mbox_ick_handle);
103 if (cpu_is_omap44xx()) {
104 mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
105 timeout = jiffies + msecs_to_jiffies(20);
107 l = mbox_read_reg(MAILBOX_SYSCONFIG);
108 if (!(l & OMAP4_SOFTRESET))
110 } while (!time_after(jiffies, timeout));
112 if (l & OMAP4_SOFTRESET) {
113 pr_err("Can't take mailbox out of reset\n");
117 mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
118 timeout = jiffies + msecs_to_jiffies(20);
120 l = mbox_read_reg(MAILBOX_SYSSTATUS);
123 } while (!time_after(jiffies, timeout));
125 if (!(l & RESETDONE)) {
126 pr_err("Can't take mailbox out of reset\n");
131 l = mbox_read_reg(MAILBOX_REVISION);
132 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
134 if (cpu_is_omap44xx())
137 l = SMARTIDLE | AUTOIDLE;
138 mbox_write_reg(l, MAILBOX_SYSCONFIG);
140 omap2_mbox_enable_irq(mbox, IRQ_RX);
145 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
147 clk_disable(mbox_ick_handle);
148 clk_put(mbox_ick_handle);
149 mbox_ick_handle = NULL;
152 /* Mailbox FIFO handle functions */
153 static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
155 struct omap_mbox2_fifo *fifo =
156 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
157 return (mbox_msg_t) mbox_read_reg(fifo->msg);
160 static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
162 struct omap_mbox2_fifo *fifo =
163 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
164 mbox_write_reg(msg, fifo->msg);
167 static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
169 struct omap_mbox2_fifo *fifo =
170 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
171 return (mbox_read_reg(fifo->msg_stat) == 0);
174 static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
176 struct omap_mbox2_fifo *fifo =
177 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
178 return mbox_read_reg(fifo->fifo_stat);
181 /* Mailbox IRQ handle functions */
182 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
183 omap_mbox_type_t irq)
185 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
186 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
188 l = mbox_read_reg(p->irqenable);
190 mbox_write_reg(l, p->irqenable);
193 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
194 omap_mbox_type_t irq)
196 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
197 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
198 l = mbox_read_reg(p->irqdisable);
200 mbox_write_reg(l, p->irqdisable);
203 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
204 omap_mbox_type_t irq)
206 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
207 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
209 mbox_write_reg(bit, p->irqstatus);
211 /* Flush posted write for irq status to avoid spurious interrupts */
212 mbox_read_reg(p->irqstatus);
215 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
216 omap_mbox_type_t irq)
218 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
219 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
220 u32 enable = mbox_read_reg(p->irqenable);
221 u32 status = mbox_read_reg(p->irqstatus);
223 return (int)(enable & status & bit);
226 static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
229 struct omap_mbox2_priv *p = mbox->priv;
231 if (cpu_is_omap44xx())
232 nr_regs = OMAP4_MBOX_NR_REGS;
234 nr_regs = MBOX_NR_REGS;
235 for (i = 0; i < nr_regs; i++) {
236 p->ctx[i] = mbox_read_reg(i * sizeof(u32));
238 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
243 static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
246 struct omap_mbox2_priv *p = mbox->priv;
248 if (cpu_is_omap44xx())
249 nr_regs = OMAP4_MBOX_NR_REGS;
251 nr_regs = MBOX_NR_REGS;
252 for (i = 0; i < nr_regs; i++) {
253 mbox_write_reg(p->ctx[i], i * sizeof(u32));
255 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
260 static struct omap_mbox_ops omap2_mbox_ops = {
261 .type = OMAP_MBOX_TYPE2,
262 .startup = omap2_mbox_startup,
263 .shutdown = omap2_mbox_shutdown,
264 .fifo_read = omap2_mbox_fifo_read,
265 .fifo_write = omap2_mbox_fifo_write,
266 .fifo_empty = omap2_mbox_fifo_empty,
267 .fifo_full = omap2_mbox_fifo_full,
268 .enable_irq = omap2_mbox_enable_irq,
269 .disable_irq = omap2_mbox_disable_irq,
270 .ack_irq = omap2_mbox_ack_irq,
271 .is_irq = omap2_mbox_is_irq,
272 .save_ctx = omap2_mbox_save_ctx,
273 .restore_ctx = omap2_mbox_restore_ctx,
277 * MAILBOX 0: ARM -> DSP,
278 * MAILBOX 1: ARM <- DSP.
279 * MAILBOX 2: ARM -> IVA,
280 * MAILBOX 3: ARM <- IVA.
283 /* FIXME: the following structs should be filled automatically by the user id */
285 #if defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_ARCH_OMAP2420)
287 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
289 .msg = MAILBOX_MESSAGE(0),
290 .fifo_stat = MAILBOX_FIFOSTATUS(0),
293 .msg = MAILBOX_MESSAGE(1),
294 .msg_stat = MAILBOX_MSGSTATUS(1),
296 .irqenable = MAILBOX_IRQENABLE(0),
297 .irqstatus = MAILBOX_IRQSTATUS(0),
298 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
299 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
300 .irqdisable = MAILBOX_IRQENABLE(0),
303 struct omap_mbox mbox_dsp_info = {
305 .ops = &omap2_mbox_ops,
306 .priv = &omap2_mbox_dsp_priv,
310 #if defined(CONFIG_ARCH_OMAP3430)
311 struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
314 #if defined(CONFIG_ARCH_OMAP2420)
316 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
318 .msg = MAILBOX_MESSAGE(2),
319 .fifo_stat = MAILBOX_FIFOSTATUS(2),
322 .msg = MAILBOX_MESSAGE(3),
323 .msg_stat = MAILBOX_MSGSTATUS(3),
325 .irqenable = MAILBOX_IRQENABLE(3),
326 .irqstatus = MAILBOX_IRQSTATUS(3),
327 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
328 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
329 .irqdisable = MAILBOX_IRQENABLE(3),
332 static struct omap_mbox mbox_iva_info = {
334 .ops = &omap2_mbox_ops,
335 .priv = &omap2_mbox_iva_priv,
338 struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL };
341 #if defined(CONFIG_ARCH_OMAP4)
343 static struct omap_mbox2_priv omap2_mbox_1_priv = {
345 .msg = MAILBOX_MESSAGE(0),
346 .fifo_stat = MAILBOX_FIFOSTATUS(0),
349 .msg = MAILBOX_MESSAGE(1),
350 .msg_stat = MAILBOX_MSGSTATUS(1),
352 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
353 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
354 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
355 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
356 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
359 struct omap_mbox mbox_1_info = {
361 .ops = &omap2_mbox_ops,
362 .priv = &omap2_mbox_1_priv,
365 static struct omap_mbox2_priv omap2_mbox_2_priv = {
367 .msg = MAILBOX_MESSAGE(3),
368 .fifo_stat = MAILBOX_FIFOSTATUS(3),
371 .msg = MAILBOX_MESSAGE(2),
372 .msg_stat = MAILBOX_MSGSTATUS(2),
374 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
375 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
376 .notfull_bit = MAILBOX_IRQ_NOTFULL(3),
377 .newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
378 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
381 struct omap_mbox mbox_2_info = {
383 .ops = &omap2_mbox_ops,
384 .priv = &omap2_mbox_2_priv,
387 struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
390 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
392 struct resource *mem;
394 struct omap_mbox **list;
398 #if defined(CONFIG_ARCH_OMAP3430)
399 else if (cpu_is_omap3430()) {
402 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
405 #if defined(CONFIG_ARCH_OMAP2420)
406 else if (cpu_is_omap2420()) {
409 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
410 list[1]->irq = platform_get_irq_byname(pdev, "iva");
413 #if defined(CONFIG_ARCH_OMAP4)
414 else if (cpu_is_omap44xx()) {
417 list[0]->irq = list[1]->irq =
418 platform_get_irq_byname(pdev, "mbox");
422 pr_err("%s: platform not supported\n", __func__);
426 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
427 mbox_base = ioremap(mem->start, resource_size(mem));
431 ret = omap_mbox_register(&pdev->dev, list);
441 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
443 omap_mbox_unregister();
448 static struct platform_driver omap2_mbox_driver = {
449 .probe = omap2_mbox_probe,
450 .remove = __devexit_p(omap2_mbox_remove),
452 .name = "omap-mailbox",
456 static int __init omap2_mbox_init(void)
458 return platform_driver_register(&omap2_mbox_driver);
461 static void __exit omap2_mbox_exit(void)
463 platform_driver_unregister(&omap2_mbox_driver);
466 module_init(omap2_mbox_init);
467 module_exit(omap2_mbox_exit);
469 MODULE_LICENSE("GPL v2");
470 MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
471 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
472 MODULE_AUTHOR("Paul Mundt");
473 MODULE_ALIAS("platform:omap2-mailbox");