arch/arm/mach-omap2/omap4-common.c

   1 /*
   2  * OMAP4 specific common source file.
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc.
   5  * Author:
   6  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   7  *
   8  *
   9  * This program is free software,you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/memblock.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/export.h>
  22
  23 #include <asm/hardware/gic.h>
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <asm/mach/map.h>
  26 #include <asm/memblock.h>
  27
  28 #include "omap-wakeupgen.h"
  29 #include "soc.h"
  30 #include "common.h"
  31 #include "mmc.h"
  32 #include "hsmmc.h"
  33 #include "omap4-sar-layout.h"
  34 #include "omap-secure.h"
  35 #include "sram.h"
  36
  37 #ifdef CONFIG_CACHE_L2X0
  38 static void __iomem *l2cache_base;
  39 #endif
  40
  41 static void __iomem *sar_ram_base;
  42
  43 #ifdef CONFIG_OMAP4_ERRATA_I688
  44 /* Used to implement memory barrier on DRAM path */
  45 #define OMAP4_DRAM_BARRIER_VA                   0xfe600000
  46
  47 void __iomem *dram_sync, *sram_sync;
  48
  49 static phys_addr_t paddr;
  50 static u32 size;
  51
  52 void omap_bus_sync(void)
  53 {
  54         if (dram_sync && sram_sync) {
  55                 writel_relaxed(readl_relaxed(dram_sync), dram_sync);
  56                 writel_relaxed(readl_relaxed(sram_sync), sram_sync);
  57                 isb();
  58         }
  59 }
  60 EXPORT_SYMBOL(omap_bus_sync);
  61
  62 /* Steal one page physical memory for barrier implementation */
  63 int __init omap_barrier_reserve_memblock(void)
  64 {
  65
  66         size = ALIGN(PAGE_SIZE, SZ_1M);
  67         paddr = arm_memblock_steal(size, SZ_1M);
  68
  69         return 0;
  70 }
  71
  72 void __init omap_barriers_init(void)
  73 {
  74         struct map_desc dram_io_desc[1];
  75
  76         dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
  77         dram_io_desc[0].pfn = __phys_to_pfn(paddr);
  78         dram_io_desc[0].length = size;
  79         dram_io_desc[0].type = MT_MEMORY_SO;
  80         iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
  81         dram_sync = (void __iomem *) dram_io_desc[0].virtual;
  82         sram_sync = (void __iomem *) OMAP4_SRAM_VA;
  83
  84         pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
  85                 (long long) paddr, dram_io_desc[0].virtual);
  86
  87 }
  88 #else
  89 void __init omap_barriers_init(void)
  90 {}
  91 #endif
  92
  93 void __init gic_init_irq(void)
  94 {
  95         void __iomem *omap_irq_base;
  96         void __iomem *gic_dist_base_addr;
  97
  98         /* Static mapping, never released */
  99         gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
 100         BUG_ON(!gic_dist_base_addr);
 101
 102         /* Static mapping, never released */
 103         omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
 104         BUG_ON(!omap_irq_base);
 105
 106         omap_wakeupgen_init();
 107
 108         gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
 109 }
 110
 111 #ifdef CONFIG_CACHE_L2X0
 112
 113 void __iomem *omap4_get_l2cache_base(void)
 114 {
 115         return l2cache_base;
 116 }
 117
 118 static void omap4_l2x0_disable(void)
 119 {
 120         /* Disable PL310 L2 Cache controller */
 121         omap_smc1(0x102, 0x0);
 122 }
 123
 124 static void omap4_l2x0_set_debug(unsigned long val)
 125 {
 126         /* Program PL310 L2 Cache controller debug register */
 127         omap_smc1(0x100, val);
 128 }
 129
 130 static int __init omap_l2_cache_init(void)
 131 {
 132         u32 aux_ctrl = 0;
 133
 134         /*
 135          * To avoid code running on other OMAPs in
 136          * multi-omap builds
 137          */
 138         if (!cpu_is_omap44xx())
 139                 return -ENODEV;
 140
 141         /* Static mapping, never released */
 142         l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
 143         if (WARN_ON(!l2cache_base))
 144                 return -ENOMEM;
 145
 146         /*
 147          * 16-way associativity, parity disabled
 148          * Way size - 32KB (es1.0)
 149          * Way size - 64KB (es2.0 +)
 150          */
 151         aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
 152                         (0x1 << 25) |
 153                         (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
 154                         (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
 155
 156         if (omap_rev() == OMAP4430_REV_ES1_0) {
 157                 aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
 158         } else {
 159                 aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
 160                         (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
 161                         (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
 162                         (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
 163                         (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
 164         }
 165         if (omap_rev() != OMAP4430_REV_ES1_0)
 166                 omap_smc1(0x109, aux_ctrl);
 167
 168         /* Enable PL310 L2 Cache controller */
 169         omap_smc1(0x102, 0x1);
 170
 171         if (of_have_populated_dt())
 172                 l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
 173         else
 174                 l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
 175
 176         /*
 177          * Override default outer_cache.disable with a OMAP4
 178          * specific one
 179         */
 180         outer_cache.disable = omap4_l2x0_disable;
 181         outer_cache.set_debug = omap4_l2x0_set_debug;
 182
 183         return 0;
 184 }
 185 early_initcall(omap_l2_cache_init);
 186 #endif
 187
 188 void __iomem *omap4_get_sar_ram_base(void)
 189 {
 190         return sar_ram_base;
 191 }
 192
 193 /*
 194  * SAR RAM used to save and restore the HW
 195  * context in low power modes
 196  */
 197 static int __init omap4_sar_ram_init(void)
 198 {
 199         /*
 200          * To avoid code running on other OMAPs in
 201          * multi-omap builds
 202          */
 203         if (!cpu_is_omap44xx())
 204                 return -ENOMEM;
 205
 206         /* Static mapping, never released */
 207         sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
 208         if (WARN_ON(!sar_ram_base))
 209                 return -ENOMEM;
 210
 211         return 0;
 212 }
 213 early_initcall(omap4_sar_ram_init);
 214
 215 static struct of_device_id irq_match[] __initdata = {
 216         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 217         { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
 218         { }
 219 };
 220
 221 void __init omap_gic_of_init(void)
 222 {
 223         omap_wakeupgen_init();
 224         of_irq_init(irq_match);
 225 }
 226
 227 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 228 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 229 {
 230         int irq = 0;
 231         struct platform_device *pdev = container_of(dev,
 232                                 struct platform_device, dev);
 233         struct omap_mmc_platform_data *pdata = dev->platform_data;
 234
 235         /* Setting MMC1 Card detect Irq */
 236         if (pdev->id == 0) {
 237                 irq = twl6030_mmc_card_detect_config();
 238                 if (irq < 0) {
 239                         dev_err(dev, "%s: Error card detect config(%d)\n",
 240                                 __func__, irq);
 241                         return irq;
 242                 }
 243                 pdata->slots[0].card_detect_irq = irq;
 244                 pdata->slots[0].card_detect = twl6030_mmc_card_detect;
 245         }
 246         return 0;
 247 }
 248
 249 static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
 250 {
 251         struct omap_mmc_platform_data *pdata;
 252
 253         /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
 254         if (!dev) {
 255                 pr_err("Failed %s\n", __func__);
 256                 return;
 257         }
 258         pdata = dev->platform_data;
 259         pdata->init =   omap4_twl6030_hsmmc_late_init;
 260 }
 261
 262 int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
 263 {
 264         struct omap2_hsmmc_info *c;
 265
 266         omap_hsmmc_init(controllers);
 267         for (c = controllers; c->mmc; c++) {
 268                 /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
 269                 if (!c->pdev)
 270                         continue;
 271                 omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
 272         }
 273
 274         return 0;
 275 }
 276 #else
 277 int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
 278 {
 279         return 0;
 280 }
 281 #endif