arch/arm/mach-omap2/omap_hwmod_2430_data.c

   1 /*
   2  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcbsp.h>
  22 #include <plat/mcspi.h>
  23 #include <plat/dmtimer.h>
  24 #include <plat/mmc.h>
  25 #include <plat/l3_2xxx.h>
  26
  27 #include "omap_hwmod_common_data.h"
  28
  29 #include "prm-regbits-24xx.h"
  30 #include "cm-regbits-24xx.h"
  31 #include "wd_timer.h"
  32
  33 /*
  34  * OMAP2430 hardware module integration data
  35  *
  36  * ALl of the data in this section should be autogeneratable from the
  37  * TI hardware database or other technical documentation.  Data that
  38  * is driver-specific or driver-kernel integration-specific belongs
  39  * elsewhere.
  40  */
  41
  42 static struct omap_hwmod omap2430_mpu_hwmod;
  43 static struct omap_hwmod omap2430_iva_hwmod;
  44 static struct omap_hwmod omap2430_l3_main_hwmod;
  45 static struct omap_hwmod omap2430_l4_core_hwmod;
  46 static struct omap_hwmod omap2430_dss_core_hwmod;
  47 static struct omap_hwmod omap2430_dss_dispc_hwmod;
  48 static struct omap_hwmod omap2430_dss_rfbi_hwmod;
  49 static struct omap_hwmod omap2430_dss_venc_hwmod;
  50 static struct omap_hwmod omap2430_wd_timer2_hwmod;
  51 static struct omap_hwmod omap2430_gpio1_hwmod;
  52 static struct omap_hwmod omap2430_gpio2_hwmod;
  53 static struct omap_hwmod omap2430_gpio3_hwmod;
  54 static struct omap_hwmod omap2430_gpio4_hwmod;
  55 static struct omap_hwmod omap2430_gpio5_hwmod;
  56 static struct omap_hwmod omap2430_dma_system_hwmod;
  57 static struct omap_hwmod omap2430_mcbsp1_hwmod;
  58 static struct omap_hwmod omap2430_mcbsp2_hwmod;
  59 static struct omap_hwmod omap2430_mcbsp3_hwmod;
  60 static struct omap_hwmod omap2430_mcbsp4_hwmod;
  61 static struct omap_hwmod omap2430_mcbsp5_hwmod;
  62 static struct omap_hwmod omap2430_mcspi1_hwmod;
  63 static struct omap_hwmod omap2430_mcspi2_hwmod;
  64 static struct omap_hwmod omap2430_mcspi3_hwmod;
  65 static struct omap_hwmod omap2430_mmc1_hwmod;
  66 static struct omap_hwmod omap2430_mmc2_hwmod;
  67
  68 /* L3 -> L4_CORE interface */
  69 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
  70         .master = &omap2430_l3_main_hwmod,
  71         .slave  = &omap2430_l4_core_hwmod,
  72         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  73 };
  74
  75 /* MPU -> L3 interface */
  76 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
  77         .master = &omap2430_mpu_hwmod,
  78         .slave  = &omap2430_l3_main_hwmod,
  79         .user   = OCP_USER_MPU,
  80 };
  81
  82 /* Slave interfaces on the L3 interconnect */
  83 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
  84         &omap2430_mpu__l3_main,
  85 };
  86
  87 /* DSS -> l3 */
  88 static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
  89         .master         = &omap2430_dss_core_hwmod,
  90         .slave          = &omap2430_l3_main_hwmod,
  91         .fw = {
  92                 .omap2 = {
  93                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  94                         .flags  = OMAP_FIREWALL_L3,
  95                 }
  96         },
  97         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  98 };
  99
 100 /* Master interfaces on the L3 interconnect */
 101 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
 102         &omap2430_l3_main__l4_core,
 103 };
 104
 105 /* L3 */
 106 static struct omap_hwmod omap2430_l3_main_hwmod = {
 107         .name           = "l3_main",
 108         .class          = &l3_hwmod_class,
 109         .masters        = omap2430_l3_main_masters,
 110         .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
 111         .slaves         = omap2430_l3_main_slaves,
 112         .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
 113         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 114         .flags          = HWMOD_NO_IDLEST,
 115 };
 116
 117 static struct omap_hwmod omap2430_l4_wkup_hwmod;
 118 static struct omap_hwmod omap2430_uart1_hwmod;
 119 static struct omap_hwmod omap2430_uart2_hwmod;
 120 static struct omap_hwmod omap2430_uart3_hwmod;
 121 static struct omap_hwmod omap2430_i2c1_hwmod;
 122 static struct omap_hwmod omap2430_i2c2_hwmod;
 123
 124 static struct omap_hwmod omap2430_usbhsotg_hwmod;
 125
 126 /* l3_core -> usbhsotg  interface */
 127 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
 128         .master         = &omap2430_usbhsotg_hwmod,
 129         .slave          = &omap2430_l3_main_hwmod,
 130         .clk            = "core_l3_ck",
 131         .user           = OCP_USER_MPU,
 132 };
 133
 134 /* I2C IP block address space length (in bytes) */
 135 #define OMAP2_I2C_AS_LEN                128
 136
 137 /* L4 CORE -> I2C1 interface */
 138 static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
 139         {
 140                 .pa_start       = 0x48070000,
 141                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 142                 .flags          = ADDR_TYPE_RT,
 143         },
 144 };
 145
 146 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
 147         .master         = &omap2430_l4_core_hwmod,
 148         .slave          = &omap2430_i2c1_hwmod,
 149         .clk            = "i2c1_ick",
 150         .addr           = omap2430_i2c1_addr_space,
 151         .addr_cnt       = ARRAY_SIZE(omap2430_i2c1_addr_space),
 152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 153 };
 154
 155 /* L4 CORE -> I2C2 interface */
 156 static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
 157         {
 158                 .pa_start       = 0x48072000,
 159                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 160                 .flags          = ADDR_TYPE_RT,
 161         },
 162 };
 163
 164 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
 165         .master         = &omap2430_l4_core_hwmod,
 166         .slave          = &omap2430_i2c2_hwmod,
 167         .clk            = "i2c2_ick",
 168         .addr           = omap2430_i2c2_addr_space,
 169         .addr_cnt       = ARRAY_SIZE(omap2430_i2c2_addr_space),
 170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 171 };
 172
 173 /* L4_CORE -> L4_WKUP interface */
 174 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
 175         .master = &omap2430_l4_core_hwmod,
 176         .slave  = &omap2430_l4_wkup_hwmod,
 177         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 178 };
 179
 180 /* L4 CORE -> UART1 interface */
 181 static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
 182         {
 183                 .pa_start       = OMAP2_UART1_BASE,
 184                 .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
 185                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 186         },
 187 };
 188
 189 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 190         .master         = &omap2430_l4_core_hwmod,
 191         .slave          = &omap2430_uart1_hwmod,
 192         .clk            = "uart1_ick",
 193         .addr           = omap2430_uart1_addr_space,
 194         .addr_cnt       = ARRAY_SIZE(omap2430_uart1_addr_space),
 195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 196 };
 197
 198 /* L4 CORE -> UART2 interface */
 199 static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
 200         {
 201                 .pa_start       = OMAP2_UART2_BASE,
 202                 .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
 203                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 204         },
 205 };
 206
 207 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 208         .master         = &omap2430_l4_core_hwmod,
 209         .slave          = &omap2430_uart2_hwmod,
 210         .clk            = "uart2_ick",
 211         .addr           = omap2430_uart2_addr_space,
 212         .addr_cnt       = ARRAY_SIZE(omap2430_uart2_addr_space),
 213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 214 };
 215
 216 /* L4 PER -> UART3 interface */
 217 static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
 218         {
 219                 .pa_start       = OMAP2_UART3_BASE,
 220                 .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
 221                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 222         },
 223 };
 224
 225 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 226         .master         = &omap2430_l4_core_hwmod,
 227         .slave          = &omap2430_uart3_hwmod,
 228         .clk            = "uart3_ick",
 229         .addr           = omap2430_uart3_addr_space,
 230         .addr_cnt       = ARRAY_SIZE(omap2430_uart3_addr_space),
 231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 232 };
 233
 234 /*
 235 * usbhsotg interface data
 236 */
 237 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
 238         {
 239                 .pa_start       = OMAP243X_HS_BASE,
 240                 .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
 241                 .flags          = ADDR_TYPE_RT
 242         },
 243 };
 244
 245 /*  l4_core ->usbhsotg  interface */
 246 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
 247         .master         = &omap2430_l4_core_hwmod,
 248         .slave          = &omap2430_usbhsotg_hwmod,
 249         .clk            = "usb_l4_ick",
 250         .addr           = omap2430_usbhsotg_addrs,
 251         .addr_cnt       = ARRAY_SIZE(omap2430_usbhsotg_addrs),
 252         .user           = OCP_USER_MPU,
 253 };
 254
 255 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
 256         &omap2430_usbhsotg__l3,
 257 };
 258
 259 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
 260         &omap2430_l4_core__usbhsotg,
 261 };
 262
 263 /* L4 CORE -> MMC1 interface */
 264 static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
 265         {
 266                 .pa_start       = 0x4809c000,
 267                 .pa_end         = 0x4809c1ff,
 268                 .flags          = ADDR_TYPE_RT,
 269         },
 270 };
 271
 272 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
 273         .master         = &omap2430_l4_core_hwmod,
 274         .slave          = &omap2430_mmc1_hwmod,
 275         .clk            = "mmchs1_ick",
 276         .addr           = omap2430_mmc1_addr_space,
 277         .addr_cnt       = ARRAY_SIZE(omap2430_mmc1_addr_space),
 278         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 279 };
 280
 281 /* L4 CORE -> MMC2 interface */
 282 static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
 283         {
 284                 .pa_start       = 0x480b4000,
 285                 .pa_end         = 0x480b41ff,
 286                 .flags          = ADDR_TYPE_RT,
 287         },
 288 };
 289
 290 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
 291         .master         = &omap2430_l4_core_hwmod,
 292         .slave          = &omap2430_mmc2_hwmod,
 293         .addr           = omap2430_mmc2_addr_space,
 294         .clk            = "mmchs2_ick",
 295         .addr_cnt       = ARRAY_SIZE(omap2430_mmc2_addr_space),
 296         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 297 };
 298
 299 /* Slave interfaces on the L4_CORE interconnect */
 300 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
 301         &omap2430_l3_main__l4_core,
 302 };
 303
 304 /* Master interfaces on the L4_CORE interconnect */
 305 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
 306         &omap2430_l4_core__l4_wkup,
 307         &omap2430_l4_core__mmc1,
 308         &omap2430_l4_core__mmc2,
 309 };
 310
 311 /* L4 CORE */
 312 static struct omap_hwmod omap2430_l4_core_hwmod = {
 313         .name           = "l4_core",
 314         .class          = &l4_hwmod_class,
 315         .masters        = omap2430_l4_core_masters,
 316         .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
 317         .slaves         = omap2430_l4_core_slaves,
 318         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
 319         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 320         .flags          = HWMOD_NO_IDLEST,
 321 };
 322
 323 /* Slave interfaces on the L4_WKUP interconnect */
 324 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
 325         &omap2430_l4_core__l4_wkup,
 326         &omap2_l4_core__uart1,
 327         &omap2_l4_core__uart2,
 328         &omap2_l4_core__uart3,
 329 };
 330
 331 /* Master interfaces on the L4_WKUP interconnect */
 332 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 333 };
 334
 335 /* l4 core -> mcspi1 interface */
 336 static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
 337         {
 338                 .pa_start       = 0x48098000,
 339                 .pa_end         = 0x480980ff,
 340                 .flags          = ADDR_TYPE_RT,
 341         },
 342 };
 343
 344 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
 345         .master         = &omap2430_l4_core_hwmod,
 346         .slave          = &omap2430_mcspi1_hwmod,
 347         .clk            = "mcspi1_ick",
 348         .addr           = omap2430_mcspi1_addr_space,
 349         .addr_cnt       = ARRAY_SIZE(omap2430_mcspi1_addr_space),
 350         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 351 };
 352
 353 /* l4 core -> mcspi2 interface */
 354 static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
 355         {
 356                 .pa_start       = 0x4809a000,
 357                 .pa_end         = 0x4809a0ff,
 358                 .flags          = ADDR_TYPE_RT,
 359         },
 360 };
 361
 362 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
 363         .master         = &omap2430_l4_core_hwmod,
 364         .slave          = &omap2430_mcspi2_hwmod,
 365         .clk            = "mcspi2_ick",
 366         .addr           = omap2430_mcspi2_addr_space,
 367         .addr_cnt       = ARRAY_SIZE(omap2430_mcspi2_addr_space),
 368         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 369 };
 370
 371 /* l4 core -> mcspi3 interface */
 372 static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
 373         {
 374                 .pa_start       = 0x480b8000,
 375                 .pa_end         = 0x480b80ff,
 376                 .flags          = ADDR_TYPE_RT,
 377         },
 378 };
 379
 380 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
 381         .master         = &omap2430_l4_core_hwmod,
 382         .slave          = &omap2430_mcspi3_hwmod,
 383         .clk            = "mcspi3_ick",
 384         .addr           = omap2430_mcspi3_addr_space,
 385         .addr_cnt       = ARRAY_SIZE(omap2430_mcspi3_addr_space),
 386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 387 };
 388
 389 /* L4 WKUP */
 390 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
 391         .name           = "l4_wkup",
 392         .class          = &l4_hwmod_class,
 393         .masters        = omap2430_l4_wkup_masters,
 394         .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
 395         .slaves         = omap2430_l4_wkup_slaves,
 396         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
 397         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 398         .flags          = HWMOD_NO_IDLEST,
 399 };
 400
 401 /* Master interfaces on the MPU device */
 402 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
 403         &omap2430_mpu__l3_main,
 404 };
 405
 406 /* MPU */
 407 static struct omap_hwmod omap2430_mpu_hwmod = {
 408         .name           = "mpu",
 409         .class          = &mpu_hwmod_class,
 410         .main_clk       = "mpu_ck",
 411         .masters        = omap2430_mpu_masters,
 412         .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
 413         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 414 };
 415
 416 /*
 417  * IVA2_1 interface data
 418  */
 419
 420 /* IVA2 <- L3 interface */
 421 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
 422         .master         = &omap2430_l3_main_hwmod,
 423         .slave          = &omap2430_iva_hwmod,
 424         .clk            = "dsp_fck",
 425         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 426 };
 427
 428 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
 429         &omap2430_l3__iva,
 430 };
 431
 432 /*
 433  * IVA2 (IVA2)
 434  */
 435
 436 static struct omap_hwmod omap2430_iva_hwmod = {
 437         .name           = "iva",
 438         .class          = &iva_hwmod_class,
 439         .masters        = omap2430_iva_masters,
 440         .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
 441         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 442 };
 443
 444 /* Timer Common */
 445 static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
 446         .rev_offs       = 0x0000,
 447         .sysc_offs      = 0x0010,
 448         .syss_offs      = 0x0014,
 449         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 450                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 451                            SYSC_HAS_AUTOIDLE),
 452         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 453         .sysc_fields    = &omap_hwmod_sysc_type1,
 454 };
 455
 456 static struct omap_hwmod_class omap2430_timer_hwmod_class = {
 457         .name = "timer",
 458         .sysc = &omap2430_timer_sysc,
 459         .rev = OMAP_TIMER_IP_VERSION_1,
 460 };
 461
 462 /* timer1 */
 463 static struct omap_hwmod omap2430_timer1_hwmod;
 464 static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
 465         { .irq = 37, },
 466 };
 467
 468 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
 469         {
 470                 .pa_start       = 0x49018000,
 471                 .pa_end         = 0x49018000 + SZ_1K - 1,
 472                 .flags          = ADDR_TYPE_RT
 473         },
 474 };
 475
 476 /* l4_wkup -> timer1 */
 477 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
 478         .master         = &omap2430_l4_wkup_hwmod,
 479         .slave          = &omap2430_timer1_hwmod,
 480         .clk            = "gpt1_ick",
 481         .addr           = omap2430_timer1_addrs,
 482         .addr_cnt       = ARRAY_SIZE(omap2430_timer1_addrs),
 483         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 484 };
 485
 486 /* timer1 slave port */
 487 static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
 488         &omap2430_l4_wkup__timer1,
 489 };
 490
 491 /* timer1 hwmod */
 492 static struct omap_hwmod omap2430_timer1_hwmod = {
 493         .name           = "timer1",
 494         .mpu_irqs       = omap2430_timer1_mpu_irqs,
 495         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
 496         .main_clk       = "gpt1_fck",
 497         .prcm           = {
 498                 .omap2 = {
 499                         .prcm_reg_id = 1,
 500                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 501                         .module_offs = WKUP_MOD,
 502                         .idlest_reg_id = 1,
 503                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 504                 },
 505         },
 506         .slaves         = omap2430_timer1_slaves,
 507         .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
 508         .class          = &omap2430_timer_hwmod_class,
 509         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 510 };
 511
 512 /* timer2 */
 513 static struct omap_hwmod omap2430_timer2_hwmod;
 514 static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
 515         { .irq = 38, },
 516 };
 517
 518 static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
 519         {
 520                 .pa_start       = 0x4802a000,
 521                 .pa_end         = 0x4802a000 + SZ_1K - 1,
 522                 .flags          = ADDR_TYPE_RT
 523         },
 524 };
 525
 526 /* l4_core -> timer2 */
 527 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
 528         .master         = &omap2430_l4_core_hwmod,
 529         .slave          = &omap2430_timer2_hwmod,
 530         .clk            = "gpt2_ick",
 531         .addr           = omap2430_timer2_addrs,
 532         .addr_cnt       = ARRAY_SIZE(omap2430_timer2_addrs),
 533         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 534 };
 535
 536 /* timer2 slave port */
 537 static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
 538         &omap2430_l4_core__timer2,
 539 };
 540
 541 /* timer2 hwmod */
 542 static struct omap_hwmod omap2430_timer2_hwmod = {
 543         .name           = "timer2",
 544         .mpu_irqs       = omap2430_timer2_mpu_irqs,
 545         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
 546         .main_clk       = "gpt2_fck",
 547         .prcm           = {
 548                 .omap2 = {
 549                         .prcm_reg_id = 1,
 550                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 551                         .module_offs = CORE_MOD,
 552                         .idlest_reg_id = 1,
 553                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 554                 },
 555         },
 556         .slaves         = omap2430_timer2_slaves,
 557         .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
 558         .class          = &omap2430_timer_hwmod_class,
 559         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 560 };
 561
 562 /* timer3 */
 563 static struct omap_hwmod omap2430_timer3_hwmod;
 564 static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
 565         { .irq = 39, },
 566 };
 567
 568 static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
 569         {
 570                 .pa_start       = 0x48078000,
 571                 .pa_end         = 0x48078000 + SZ_1K - 1,
 572                 .flags          = ADDR_TYPE_RT
 573         },
 574 };
 575
 576 /* l4_core -> timer3 */
 577 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
 578         .master         = &omap2430_l4_core_hwmod,
 579         .slave          = &omap2430_timer3_hwmod,
 580         .clk            = "gpt3_ick",
 581         .addr           = omap2430_timer3_addrs,
 582         .addr_cnt       = ARRAY_SIZE(omap2430_timer3_addrs),
 583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 584 };
 585
 586 /* timer3 slave port */
 587 static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
 588         &omap2430_l4_core__timer3,
 589 };
 590
 591 /* timer3 hwmod */
 592 static struct omap_hwmod omap2430_timer3_hwmod = {
 593         .name           = "timer3",
 594         .mpu_irqs       = omap2430_timer3_mpu_irqs,
 595         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
 596         .main_clk       = "gpt3_fck",
 597         .prcm           = {
 598                 .omap2 = {
 599                         .prcm_reg_id = 1,
 600                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 601                         .module_offs = CORE_MOD,
 602                         .idlest_reg_id = 1,
 603                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 604                 },
 605         },
 606         .slaves         = omap2430_timer3_slaves,
 607         .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
 608         .class          = &omap2430_timer_hwmod_class,
 609         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 610 };
 611
 612 /* timer4 */
 613 static struct omap_hwmod omap2430_timer4_hwmod;
 614 static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
 615         { .irq = 40, },
 616 };
 617
 618 static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
 619         {
 620                 .pa_start       = 0x4807a000,
 621                 .pa_end         = 0x4807a000 + SZ_1K - 1,
 622                 .flags          = ADDR_TYPE_RT
 623         },
 624 };
 625
 626 /* l4_core -> timer4 */
 627 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
 628         .master         = &omap2430_l4_core_hwmod,
 629         .slave          = &omap2430_timer4_hwmod,
 630         .clk            = "gpt4_ick",
 631         .addr           = omap2430_timer4_addrs,
 632         .addr_cnt       = ARRAY_SIZE(omap2430_timer4_addrs),
 633         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 634 };
 635
 636 /* timer4 slave port */
 637 static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
 638         &omap2430_l4_core__timer4,
 639 };
 640
 641 /* timer4 hwmod */
 642 static struct omap_hwmod omap2430_timer4_hwmod = {
 643         .name           = "timer4",
 644         .mpu_irqs       = omap2430_timer4_mpu_irqs,
 645         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
 646         .main_clk       = "gpt4_fck",
 647         .prcm           = {
 648                 .omap2 = {
 649                         .prcm_reg_id = 1,
 650                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 651                         .module_offs = CORE_MOD,
 652                         .idlest_reg_id = 1,
 653                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 654                 },
 655         },
 656         .slaves         = omap2430_timer4_slaves,
 657         .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
 658         .class          = &omap2430_timer_hwmod_class,
 659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 660 };
 661
 662 /* timer5 */
 663 static struct omap_hwmod omap2430_timer5_hwmod;
 664 static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
 665         { .irq = 41, },
 666 };
 667
 668 static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
 669         {
 670                 .pa_start       = 0x4807c000,
 671                 .pa_end         = 0x4807c000 + SZ_1K - 1,
 672                 .flags          = ADDR_TYPE_RT
 673         },
 674 };
 675
 676 /* l4_core -> timer5 */
 677 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
 678         .master         = &omap2430_l4_core_hwmod,
 679         .slave          = &omap2430_timer5_hwmod,
 680         .clk            = "gpt5_ick",
 681         .addr           = omap2430_timer5_addrs,
 682         .addr_cnt       = ARRAY_SIZE(omap2430_timer5_addrs),
 683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 684 };
 685
 686 /* timer5 slave port */
 687 static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
 688         &omap2430_l4_core__timer5,
 689 };
 690
 691 /* timer5 hwmod */
 692 static struct omap_hwmod omap2430_timer5_hwmod = {
 693         .name           = "timer5",
 694         .mpu_irqs       = omap2430_timer5_mpu_irqs,
 695         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
 696         .main_clk       = "gpt5_fck",
 697         .prcm           = {
 698                 .omap2 = {
 699                         .prcm_reg_id = 1,
 700                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 701                         .module_offs = CORE_MOD,
 702                         .idlest_reg_id = 1,
 703                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 704                 },
 705         },
 706         .slaves         = omap2430_timer5_slaves,
 707         .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
 708         .class          = &omap2430_timer_hwmod_class,
 709         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 710 };
 711
 712 /* timer6 */
 713 static struct omap_hwmod omap2430_timer6_hwmod;
 714 static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
 715         { .irq = 42, },
 716 };
 717
 718 static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
 719         {
 720                 .pa_start       = 0x4807e000,
 721                 .pa_end         = 0x4807e000 + SZ_1K - 1,
 722                 .flags          = ADDR_TYPE_RT
 723         },
 724 };
 725
 726 /* l4_core -> timer6 */
 727 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
 728         .master         = &omap2430_l4_core_hwmod,
 729         .slave          = &omap2430_timer6_hwmod,
 730         .clk            = "gpt6_ick",
 731         .addr           = omap2430_timer6_addrs,
 732         .addr_cnt       = ARRAY_SIZE(omap2430_timer6_addrs),
 733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 734 };
 735
 736 /* timer6 slave port */
 737 static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
 738         &omap2430_l4_core__timer6,
 739 };
 740
 741 /* timer6 hwmod */
 742 static struct omap_hwmod omap2430_timer6_hwmod = {
 743         .name           = "timer6",
 744         .mpu_irqs       = omap2430_timer6_mpu_irqs,
 745         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
 746         .main_clk       = "gpt6_fck",
 747         .prcm           = {
 748                 .omap2 = {
 749                         .prcm_reg_id = 1,
 750                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 751                         .module_offs = CORE_MOD,
 752                         .idlest_reg_id = 1,
 753                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 754                 },
 755         },
 756         .slaves         = omap2430_timer6_slaves,
 757         .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
 758         .class          = &omap2430_timer_hwmod_class,
 759         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 760 };
 761
 762 /* timer7 */
 763 static struct omap_hwmod omap2430_timer7_hwmod;
 764 static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
 765         { .irq = 43, },
 766 };
 767
 768 static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
 769         {
 770                 .pa_start       = 0x48080000,
 771                 .pa_end         = 0x48080000 + SZ_1K - 1,
 772                 .flags          = ADDR_TYPE_RT
 773         },
 774 };
 775
 776 /* l4_core -> timer7 */
 777 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
 778         .master         = &omap2430_l4_core_hwmod,
 779         .slave          = &omap2430_timer7_hwmod,
 780         .clk            = "gpt7_ick",
 781         .addr           = omap2430_timer7_addrs,
 782         .addr_cnt       = ARRAY_SIZE(omap2430_timer7_addrs),
 783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 784 };
 785
 786 /* timer7 slave port */
 787 static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
 788         &omap2430_l4_core__timer7,
 789 };
 790
 791 /* timer7 hwmod */
 792 static struct omap_hwmod omap2430_timer7_hwmod = {
 793         .name           = "timer7",
 794         .mpu_irqs       = omap2430_timer7_mpu_irqs,
 795         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
 796         .main_clk       = "gpt7_fck",
 797         .prcm           = {
 798                 .omap2 = {
 799                         .prcm_reg_id = 1,
 800                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 801                         .module_offs = CORE_MOD,
 802                         .idlest_reg_id = 1,
 803                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 804                 },
 805         },
 806         .slaves         = omap2430_timer7_slaves,
 807         .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
 808         .class          = &omap2430_timer_hwmod_class,
 809         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 810 };
 811
 812 /* timer8 */
 813 static struct omap_hwmod omap2430_timer8_hwmod;
 814 static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
 815         { .irq = 44, },
 816 };
 817
 818 static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
 819         {
 820                 .pa_start       = 0x48082000,
 821                 .pa_end         = 0x48082000 + SZ_1K - 1,
 822                 .flags          = ADDR_TYPE_RT
 823         },
 824 };
 825
 826 /* l4_core -> timer8 */
 827 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
 828         .master         = &omap2430_l4_core_hwmod,
 829         .slave          = &omap2430_timer8_hwmod,
 830         .clk            = "gpt8_ick",
 831         .addr           = omap2430_timer8_addrs,
 832         .addr_cnt       = ARRAY_SIZE(omap2430_timer8_addrs),
 833         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 834 };
 835
 836 /* timer8 slave port */
 837 static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
 838         &omap2430_l4_core__timer8,
 839 };
 840
 841 /* timer8 hwmod */
 842 static struct omap_hwmod omap2430_timer8_hwmod = {
 843         .name           = "timer8",
 844         .mpu_irqs       = omap2430_timer8_mpu_irqs,
 845         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
 846         .main_clk       = "gpt8_fck",
 847         .prcm           = {
 848                 .omap2 = {
 849                         .prcm_reg_id = 1,
 850                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 851                         .module_offs = CORE_MOD,
 852                         .idlest_reg_id = 1,
 853                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 854                 },
 855         },
 856         .slaves         = omap2430_timer8_slaves,
 857         .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
 858         .class          = &omap2430_timer_hwmod_class,
 859         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 860 };
 861
 862 /* timer9 */
 863 static struct omap_hwmod omap2430_timer9_hwmod;
 864 static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
 865         { .irq = 45, },
 866 };
 867
 868 static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
 869         {
 870                 .pa_start       = 0x48084000,
 871                 .pa_end         = 0x48084000 + SZ_1K - 1,
 872                 .flags          = ADDR_TYPE_RT
 873         },
 874 };
 875
 876 /* l4_core -> timer9 */
 877 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
 878         .master         = &omap2430_l4_core_hwmod,
 879         .slave          = &omap2430_timer9_hwmod,
 880         .clk            = "gpt9_ick",
 881         .addr           = omap2430_timer9_addrs,
 882         .addr_cnt       = ARRAY_SIZE(omap2430_timer9_addrs),
 883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 884 };
 885
 886 /* timer9 slave port */
 887 static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
 888         &omap2430_l4_core__timer9,
 889 };
 890
 891 /* timer9 hwmod */
 892 static struct omap_hwmod omap2430_timer9_hwmod = {
 893         .name           = "timer9",
 894         .mpu_irqs       = omap2430_timer9_mpu_irqs,
 895         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
 896         .main_clk       = "gpt9_fck",
 897         .prcm           = {
 898                 .omap2 = {
 899                         .prcm_reg_id = 1,
 900                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 901                         .module_offs = CORE_MOD,
 902                         .idlest_reg_id = 1,
 903                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 904                 },
 905         },
 906         .slaves         = omap2430_timer9_slaves,
 907         .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
 908         .class          = &omap2430_timer_hwmod_class,
 909         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 910 };
 911
 912 /* timer10 */
 913 static struct omap_hwmod omap2430_timer10_hwmod;
 914 static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
 915         { .irq = 46, },
 916 };
 917
 918 static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
 919         {
 920                 .pa_start       = 0x48086000,
 921                 .pa_end         = 0x48086000 + SZ_1K - 1,
 922                 .flags          = ADDR_TYPE_RT
 923         },
 924 };
 925
 926 /* l4_core -> timer10 */
 927 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
 928         .master         = &omap2430_l4_core_hwmod,
 929         .slave          = &omap2430_timer10_hwmod,
 930         .clk            = "gpt10_ick",
 931         .addr           = omap2430_timer10_addrs,
 932         .addr_cnt       = ARRAY_SIZE(omap2430_timer10_addrs),
 933         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 934 };
 935
 936 /* timer10 slave port */
 937 static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
 938         &omap2430_l4_core__timer10,
 939 };
 940
 941 /* timer10 hwmod */
 942 static struct omap_hwmod omap2430_timer10_hwmod = {
 943         .name           = "timer10",
 944         .mpu_irqs       = omap2430_timer10_mpu_irqs,
 945         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
 946         .main_clk       = "gpt10_fck",
 947         .prcm           = {
 948                 .omap2 = {
 949                         .prcm_reg_id = 1,
 950                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 951                         .module_offs = CORE_MOD,
 952                         .idlest_reg_id = 1,
 953                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 954                 },
 955         },
 956         .slaves         = omap2430_timer10_slaves,
 957         .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
 958         .class          = &omap2430_timer_hwmod_class,
 959         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 960 };
 961
 962 /* timer11 */
 963 static struct omap_hwmod omap2430_timer11_hwmod;
 964 static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
 965         { .irq = 47, },
 966 };
 967
 968 static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
 969         {
 970                 .pa_start       = 0x48088000,
 971                 .pa_end         = 0x48088000 + SZ_1K - 1,
 972                 .flags          = ADDR_TYPE_RT
 973         },
 974 };
 975
 976 /* l4_core -> timer11 */
 977 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
 978         .master         = &omap2430_l4_core_hwmod,
 979         .slave          = &omap2430_timer11_hwmod,
 980         .clk            = "gpt11_ick",
 981         .addr           = omap2430_timer11_addrs,
 982         .addr_cnt       = ARRAY_SIZE(omap2430_timer11_addrs),
 983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 984 };
 985
 986 /* timer11 slave port */
 987 static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
 988         &omap2430_l4_core__timer11,
 989 };
 990
 991 /* timer11 hwmod */
 992 static struct omap_hwmod omap2430_timer11_hwmod = {
 993         .name           = "timer11",
 994         .mpu_irqs       = omap2430_timer11_mpu_irqs,
 995         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
 996         .main_clk       = "gpt11_fck",
 997         .prcm           = {
 998                 .omap2 = {
 999                         .prcm_reg_id = 1,
1000                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
1001                         .module_offs = CORE_MOD,
1002                         .idlest_reg_id = 1,
1003                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
1004                 },
1005         },
1006         .slaves         = omap2430_timer11_slaves,
1007         .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
1008         .class          = &omap2430_timer_hwmod_class,
1009         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1010 };
1011
1012 /* timer12 */
1013 static struct omap_hwmod omap2430_timer12_hwmod;
1014 static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
1015         { .irq = 48, },
1016 };
1017
1018 static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
1019         {
1020                 .pa_start       = 0x4808a000,
1021                 .pa_end         = 0x4808a000 + SZ_1K - 1,
1022                 .flags          = ADDR_TYPE_RT
1023         },
1024 };
1025
1026 /* l4_core -> timer12 */
1027 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
1028         .master         = &omap2430_l4_core_hwmod,
1029         .slave          = &omap2430_timer12_hwmod,
1030         .clk            = "gpt12_ick",
1031         .addr           = omap2430_timer12_addrs,
1032         .addr_cnt       = ARRAY_SIZE(omap2430_timer12_addrs),
1033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1034 };
1035
1036 /* timer12 slave port */
1037 static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
1038         &omap2430_l4_core__timer12,
1039 };
1040
1041 /* timer12 hwmod */
1042 static struct omap_hwmod omap2430_timer12_hwmod = {
1043         .name           = "timer12",
1044         .mpu_irqs       = omap2430_timer12_mpu_irqs,
1045         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
1046         .main_clk       = "gpt12_fck",
1047         .prcm           = {
1048                 .omap2 = {
1049                         .prcm_reg_id = 1,
1050                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
1051                         .module_offs = CORE_MOD,
1052                         .idlest_reg_id = 1,
1053                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
1054                 },
1055         },
1056         .slaves         = omap2430_timer12_slaves,
1057         .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
1058         .class          = &omap2430_timer_hwmod_class,
1059         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1060 };
1061
1062 /* l4_wkup -> wd_timer2 */
1063 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
1064         {
1065                 .pa_start       = 0x49016000,
1066                 .pa_end         = 0x4901607f,
1067                 .flags          = ADDR_TYPE_RT
1068         },
1069 };
1070
1071 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
1072         .master         = &omap2430_l4_wkup_hwmod,
1073         .slave          = &omap2430_wd_timer2_hwmod,
1074         .clk            = "mpu_wdt_ick",
1075         .addr           = omap2430_wd_timer2_addrs,
1076         .addr_cnt       = ARRAY_SIZE(omap2430_wd_timer2_addrs),
1077         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1078 };
1079
1080 /*
1081  * 'wd_timer' class
1082  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1083  * overflow condition
1084  */
1085
1086 static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
1087         .rev_offs       = 0x0,
1088         .sysc_offs      = 0x0010,
1089         .syss_offs      = 0x0014,
1090         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
1091                            SYSC_HAS_AUTOIDLE),
1092         .sysc_fields    = &omap_hwmod_sysc_type1,
1093 };
1094
1095 static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
1096         .name           = "wd_timer",
1097         .sysc           = &omap2430_wd_timer_sysc,
1098         .pre_shutdown   = &omap2_wd_timer_disable
1099 };
1100
1101 /* wd_timer2 */
1102 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
1103         &omap2430_l4_wkup__wd_timer2,
1104 };
1105
1106 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
1107         .name           = "wd_timer2",
1108         .class          = &omap2430_wd_timer_hwmod_class,
1109         .main_clk       = "mpu_wdt_fck",
1110         .prcm           = {
1111                 .omap2 = {
1112                         .prcm_reg_id = 1,
1113                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1114                         .module_offs = WKUP_MOD,
1115                         .idlest_reg_id = 1,
1116                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
1117                 },
1118         },
1119         .slaves         = omap2430_wd_timer2_slaves,
1120         .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
1121         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1122 };
1123
1124 /* UART */
1125
1126 static struct omap_hwmod_class_sysconfig uart_sysc = {
1127         .rev_offs       = 0x50,
1128         .sysc_offs      = 0x54,
1129         .syss_offs      = 0x58,
1130         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
1131                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1132                            SYSC_HAS_AUTOIDLE),
1133         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1134         .sysc_fields    = &omap_hwmod_sysc_type1,
1135 };
1136
1137 static struct omap_hwmod_class uart_class = {
1138         .name = "uart",
1139         .sysc = &uart_sysc,
1140 };
1141
1142 /* UART1 */
1143
1144 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1145         { .irq = INT_24XX_UART1_IRQ, },
1146 };
1147
1148 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1149         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1150         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1151 };
1152
1153 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
1154         &omap2_l4_core__uart1,
1155 };
1156
1157 static struct omap_hwmod omap2430_uart1_hwmod = {
1158         .name           = "uart1",
1159         .mpu_irqs       = uart1_mpu_irqs,
1160         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
1161         .sdma_reqs      = uart1_sdma_reqs,
1162         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
1163         .main_clk       = "uart1_fck",
1164         .prcm           = {
1165                 .omap2 = {
1166                         .module_offs = CORE_MOD,
1167                         .prcm_reg_id = 1,
1168                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
1169                         .idlest_reg_id = 1,
1170                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
1171                 },
1172         },
1173         .slaves         = omap2430_uart1_slaves,
1174         .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
1175         .class          = &uart_class,
1176         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1177 };
1178
1179 /* UART2 */
1180
1181 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1182         { .irq = INT_24XX_UART2_IRQ, },
1183 };
1184
1185 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1186         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1187         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1188 };
1189
1190 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
1191         &omap2_l4_core__uart2,
1192 };
1193
1194 static struct omap_hwmod omap2430_uart2_hwmod = {
1195         .name           = "uart2",
1196         .mpu_irqs       = uart2_mpu_irqs,
1197         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
1198         .sdma_reqs      = uart2_sdma_reqs,
1199         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
1200         .main_clk       = "uart2_fck",
1201         .prcm           = {
1202                 .omap2 = {
1203                         .module_offs = CORE_MOD,
1204                         .prcm_reg_id = 1,
1205                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
1206                         .idlest_reg_id = 1,
1207                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
1208                 },
1209         },
1210         .slaves         = omap2430_uart2_slaves,
1211         .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
1212         .class          = &uart_class,
1213         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1214 };
1215
1216 /* UART3 */
1217
1218 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1219         { .irq = INT_24XX_UART3_IRQ, },
1220 };
1221
1222 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1223         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1224         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1225 };
1226
1227 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
1228         &omap2_l4_core__uart3,
1229 };
1230
1231 static struct omap_hwmod omap2430_uart3_hwmod = {
1232         .name           = "uart3",
1233         .mpu_irqs       = uart3_mpu_irqs,
1234         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
1235         .sdma_reqs      = uart3_sdma_reqs,
1236         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
1237         .main_clk       = "uart3_fck",
1238         .prcm           = {
1239                 .omap2 = {
1240                         .module_offs = CORE_MOD,
1241                         .prcm_reg_id = 2,
1242                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
1243                         .idlest_reg_id = 2,
1244                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
1245                 },
1246         },
1247         .slaves         = omap2430_uart3_slaves,
1248         .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
1249         .class          = &uart_class,
1250         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1251 };
1252
1253 /*
1254  * 'dss' class
1255  * display sub-system
1256  */
1257
1258 static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
1259         .rev_offs       = 0x0000,
1260         .sysc_offs      = 0x0010,
1261         .syss_offs      = 0x0014,
1262         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1263         .sysc_fields    = &omap_hwmod_sysc_type1,
1264 };
1265
1266 static struct omap_hwmod_class omap2430_dss_hwmod_class = {
1267         .name = "dss",
1268         .sysc = &omap2430_dss_sysc,
1269 };
1270
1271 /* dss */
1272 static struct omap_hwmod_irq_info omap2430_dss_irqs[] = {
1273         { .irq = 25 },
1274 };
1275 static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
1276         { .name = "dispc", .dma_req = 5 },
1277 };
1278
1279 /* dss */
1280 /* dss master ports */
1281 static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
1282         &omap2430_dss__l3,
1283 };
1284
1285 static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
1286         {
1287                 .pa_start       = 0x48050000,
1288                 .pa_end         = 0x480503FF,
1289                 .flags          = ADDR_TYPE_RT
1290         },
1291 };
1292
1293 /* l4_core -> dss */
1294 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
1295         .master         = &omap2430_l4_core_hwmod,
1296         .slave          = &omap2430_dss_core_hwmod,
1297         .clk            = "dss_ick",
1298         .addr           = omap2430_dss_addrs,
1299         .addr_cnt       = ARRAY_SIZE(omap2430_dss_addrs),
1300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1301 };
1302
1303 /* dss slave ports */
1304 static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
1305         &omap2430_l4_core__dss,
1306 };
1307
1308 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1309         { .role = "tv_clk", .clk = "dss_54m_fck" },
1310         { .role = "sys_clk", .clk = "dss2_fck" },
1311 };
1312
1313 static struct omap_hwmod omap2430_dss_core_hwmod = {
1314         .name           = "dss_core",
1315         .class          = &omap2430_dss_hwmod_class,
1316         .main_clk       = "dss1_fck", /* instead of dss_fck */
1317         .mpu_irqs       = omap2430_dss_irqs,
1318         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dss_irqs),
1319         .sdma_reqs      = omap2430_dss_sdma_chs,
1320         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_dss_sdma_chs),
1321         .prcm           = {
1322                 .omap2 = {
1323                         .prcm_reg_id = 1,
1324                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1325                         .module_offs = CORE_MOD,
1326                         .idlest_reg_id = 1,
1327                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1328                 },
1329         },
1330         .opt_clks       = dss_opt_clks,
1331         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1332         .slaves         = omap2430_dss_slaves,
1333         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
1334         .masters        = omap2430_dss_masters,
1335         .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
1336         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1337         .flags          = HWMOD_NO_IDLEST,
1338 };
1339
1340 /*
1341  * 'dispc' class
1342  * display controller
1343  */
1344
1345 static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
1346         .rev_offs       = 0x0000,
1347         .sysc_offs      = 0x0010,
1348         .syss_offs      = 0x0014,
1349         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1350                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1351         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1352                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1353         .sysc_fields    = &omap_hwmod_sysc_type1,
1354 };
1355
1356 static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
1357         .name = "dispc",
1358         .sysc = &omap2430_dispc_sysc,
1359 };
1360
1361 static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
1362         {
1363                 .pa_start       = 0x48050400,
1364                 .pa_end         = 0x480507FF,
1365                 .flags          = ADDR_TYPE_RT
1366         },
1367 };
1368
1369 /* l4_core -> dss_dispc */
1370 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
1371         .master         = &omap2430_l4_core_hwmod,
1372         .slave          = &omap2430_dss_dispc_hwmod,
1373         .clk            = "dss_ick",
1374         .addr           = omap2430_dss_dispc_addrs,
1375         .addr_cnt       = ARRAY_SIZE(omap2430_dss_dispc_addrs),
1376         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1377 };
1378
1379 /* dss_dispc slave ports */
1380 static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
1381         &omap2430_l4_core__dss_dispc,
1382 };
1383
1384 static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1385         .name           = "dss_dispc",
1386         .class          = &omap2430_dispc_hwmod_class,
1387         .main_clk       = "dss1_fck",
1388         .prcm           = {
1389                 .omap2 = {
1390                         .prcm_reg_id = 1,
1391                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1392                         .module_offs = CORE_MOD,
1393                         .idlest_reg_id = 1,
1394                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1395                 },
1396         },
1397         .slaves         = omap2430_dss_dispc_slaves,
1398         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1399         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1400         .flags          = HWMOD_NO_IDLEST,
1401 };
1402
1403 /*
1404  * 'rfbi' class
1405  * remote frame buffer interface
1406  */
1407
1408 static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
1409         .rev_offs       = 0x0000,
1410         .sysc_offs      = 0x0010,
1411         .syss_offs      = 0x0014,
1412         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1413                            SYSC_HAS_AUTOIDLE),
1414         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1415         .sysc_fields    = &omap_hwmod_sysc_type1,
1416 };
1417
1418 static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
1419         .name = "rfbi",
1420         .sysc = &omap2430_rfbi_sysc,
1421 };
1422
1423 static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
1424         {
1425                 .pa_start       = 0x48050800,
1426                 .pa_end         = 0x48050BFF,
1427                 .flags          = ADDR_TYPE_RT
1428         },
1429 };
1430
1431 /* l4_core -> dss_rfbi */
1432 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1433         .master         = &omap2430_l4_core_hwmod,
1434         .slave          = &omap2430_dss_rfbi_hwmod,
1435         .clk            = "dss_ick",
1436         .addr           = omap2430_dss_rfbi_addrs,
1437         .addr_cnt       = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
1438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1439 };
1440
1441 /* dss_rfbi slave ports */
1442 static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1443         &omap2430_l4_core__dss_rfbi,
1444 };
1445
1446 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1447         .name           = "dss_rfbi",
1448         .class          = &omap2430_rfbi_hwmod_class,
1449         .main_clk       = "dss1_fck",
1450         .prcm           = {
1451                 .omap2 = {
1452                         .prcm_reg_id = 1,
1453                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1454                         .module_offs = CORE_MOD,
1455                 },
1456         },
1457         .slaves         = omap2430_dss_rfbi_slaves,
1458         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1459         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1460         .flags          = HWMOD_NO_IDLEST,
1461 };
1462
1463 /*
1464  * 'venc' class
1465  * video encoder
1466  */
1467
1468 static struct omap_hwmod_class omap2430_venc_hwmod_class = {
1469         .name = "venc",
1470 };
1471
1472 /* dss_venc */
1473 static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
1474         {
1475                 .pa_start       = 0x48050C00,
1476                 .pa_end         = 0x48050FFF,
1477                 .flags          = ADDR_TYPE_RT
1478         },
1479 };
1480
1481 /* l4_core -> dss_venc */
1482 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1483         .master         = &omap2430_l4_core_hwmod,
1484         .slave          = &omap2430_dss_venc_hwmod,
1485         .clk            = "dss_54m_fck",
1486         .addr           = omap2430_dss_venc_addrs,
1487         .addr_cnt       = ARRAY_SIZE(omap2430_dss_venc_addrs),
1488         .flags          = OCPIF_SWSUP_IDLE,
1489         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1490 };
1491
1492 /* dss_venc slave ports */
1493 static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1494         &omap2430_l4_core__dss_venc,
1495 };
1496
1497 static struct omap_hwmod omap2430_dss_venc_hwmod = {
1498         .name           = "dss_venc",
1499         .class          = &omap2430_venc_hwmod_class,
1500         .main_clk       = "dss1_fck",
1501         .prcm           = {
1502                 .omap2 = {
1503                         .prcm_reg_id = 1,
1504                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1505                         .module_offs = CORE_MOD,
1506                 },
1507         },
1508         .slaves         = omap2430_dss_venc_slaves,
1509         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
1510         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1511         .flags          = HWMOD_NO_IDLEST,
1512 };
1513
1514 /* I2C common */
1515 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1516         .rev_offs       = 0x00,
1517         .sysc_offs      = 0x20,
1518         .syss_offs      = 0x10,
1519         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1520         .sysc_fields    = &omap_hwmod_sysc_type1,
1521 };
1522
1523 static struct omap_hwmod_class i2c_class = {
1524         .name           = "i2c",
1525         .sysc           = &i2c_sysc,
1526 };
1527
1528 static struct omap_i2c_dev_attr i2c_dev_attr = {
1529         .fifo_depth     = 8, /* bytes */
1530 };
1531
1532 /* I2C1 */
1533
1534 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1535         { .irq = INT_24XX_I2C1_IRQ, },
1536 };
1537
1538 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1539         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1540         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1541 };
1542
1543 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1544         &omap2430_l4_core__i2c1,
1545 };
1546
1547 static struct omap_hwmod omap2430_i2c1_hwmod = {
1548         .name           = "i2c1",
1549         .mpu_irqs       = i2c1_mpu_irqs,
1550         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
1551         .sdma_reqs      = i2c1_sdma_reqs,
1552         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1553         .main_clk       = "i2chs1_fck",
1554         .prcm           = {
1555                 .omap2 = {
1556                         /*
1557                          * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
1558                          * I2CHS IP's do not follow the usual pattern.
1559                          * prcm_reg_id alone cannot be used to program
1560                          * the iclk and fclk. Needs to be handled using
1561                          * additonal flags when clk handling is moved
1562                          * to hwmod framework.
1563                          */
1564                         .module_offs = CORE_MOD,
1565                         .prcm_reg_id = 1,
1566                         .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
1567                         .idlest_reg_id = 1,
1568                         .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
1569                 },
1570         },
1571         .slaves         = omap2430_i2c1_slaves,
1572         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
1573         .class          = &i2c_class,
1574         .dev_attr       = &i2c_dev_attr,
1575         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1576 };
1577
1578 /* I2C2 */
1579
1580 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1581         { .irq = INT_24XX_I2C2_IRQ, },
1582 };
1583
1584 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1585         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1586         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1587 };
1588
1589 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1590         &omap2430_l4_core__i2c2,
1591 };
1592
1593 static struct omap_hwmod omap2430_i2c2_hwmod = {
1594         .name           = "i2c2",
1595         .mpu_irqs       = i2c2_mpu_irqs,
1596         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
1597         .sdma_reqs      = i2c2_sdma_reqs,
1598         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1599         .main_clk       = "i2chs2_fck",
1600         .prcm           = {
1601                 .omap2 = {
1602                         .module_offs = CORE_MOD,
1603                         .prcm_reg_id = 1,
1604                         .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
1605                         .idlest_reg_id = 1,
1606                         .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
1607                 },
1608         },
1609         .slaves         = omap2430_i2c2_slaves,
1610         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
1611         .class          = &i2c_class,
1612         .dev_attr       = &i2c_dev_attr,
1613         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1614 };
1615
1616 /* l4_wkup -> gpio1 */
1617 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1618         {
1619                 .pa_start       = 0x4900C000,
1620                 .pa_end         = 0x4900C1ff,
1621                 .flags          = ADDR_TYPE_RT
1622         },
1623 };
1624
1625 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1626         .master         = &omap2430_l4_wkup_hwmod,
1627         .slave          = &omap2430_gpio1_hwmod,
1628         .clk            = "gpios_ick",
1629         .addr           = omap2430_gpio1_addr_space,
1630         .addr_cnt       = ARRAY_SIZE(omap2430_gpio1_addr_space),
1631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1632 };
1633
1634 /* l4_wkup -> gpio2 */
1635 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1636         {
1637                 .pa_start       = 0x4900E000,
1638                 .pa_end         = 0x4900E1ff,
1639                 .flags          = ADDR_TYPE_RT
1640         },
1641 };
1642
1643 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1644         .master         = &omap2430_l4_wkup_hwmod,
1645         .slave          = &omap2430_gpio2_hwmod,
1646         .clk            = "gpios_ick",
1647         .addr           = omap2430_gpio2_addr_space,
1648         .addr_cnt       = ARRAY_SIZE(omap2430_gpio2_addr_space),
1649         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1650 };
1651
1652 /* l4_wkup -> gpio3 */
1653 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1654         {
1655                 .pa_start       = 0x49010000,
1656                 .pa_end         = 0x490101ff,
1657                 .flags          = ADDR_TYPE_RT
1658         },
1659 };
1660
1661 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1662         .master         = &omap2430_l4_wkup_hwmod,
1663         .slave          = &omap2430_gpio3_hwmod,
1664         .clk            = "gpios_ick",
1665         .addr           = omap2430_gpio3_addr_space,
1666         .addr_cnt       = ARRAY_SIZE(omap2430_gpio3_addr_space),
1667         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1668 };
1669
1670 /* l4_wkup -> gpio4 */
1671 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1672         {
1673                 .pa_start       = 0x49012000,
1674                 .pa_end         = 0x490121ff,
1675                 .flags          = ADDR_TYPE_RT
1676         },
1677 };
1678
1679 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1680         .master         = &omap2430_l4_wkup_hwmod,
1681         .slave          = &omap2430_gpio4_hwmod,
1682         .clk            = "gpios_ick",
1683         .addr           = omap2430_gpio4_addr_space,
1684         .addr_cnt       = ARRAY_SIZE(omap2430_gpio4_addr_space),
1685         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1686 };
1687
1688 /* l4_core -> gpio5 */
1689 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1690         {
1691                 .pa_start       = 0x480B6000,
1692                 .pa_end         = 0x480B61ff,
1693                 .flags          = ADDR_TYPE_RT
1694         },
1695 };
1696
1697 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1698         .master         = &omap2430_l4_core_hwmod,
1699         .slave          = &omap2430_gpio5_hwmod,
1700         .clk            = "gpio5_ick",
1701         .addr           = omap2430_gpio5_addr_space,
1702         .addr_cnt       = ARRAY_SIZE(omap2430_gpio5_addr_space),
1703         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1704 };
1705
1706 /* gpio dev_attr */
1707 static struct omap_gpio_dev_attr gpio_dev_attr = {
1708         .bank_width = 32,
1709         .dbck_flag = false,
1710 };
1711
1712 static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
1713         .rev_offs       = 0x0000,
1714         .sysc_offs      = 0x0010,
1715         .syss_offs      = 0x0014,
1716         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1717                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1718         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1719         .sysc_fields    = &omap_hwmod_sysc_type1,
1720 };
1721
1722 /*
1723  * 'gpio' class
1724  * general purpose io module
1725  */
1726 static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
1727         .name = "gpio",
1728         .sysc = &omap243x_gpio_sysc,
1729         .rev = 0,
1730 };
1731
1732 /* gpio1 */
1733 static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
1734         { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1735 };
1736
1737 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1738         &omap2430_l4_wkup__gpio1,
1739 };
1740
1741 static struct omap_hwmod omap2430_gpio1_hwmod = {
1742         .name           = "gpio1",
1743         .mpu_irqs       = omap243x_gpio1_irqs,
1744         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio1_irqs),
1745         .main_clk       = "gpios_fck",
1746         .prcm           = {
1747                 .omap2 = {
1748                         .prcm_reg_id = 1,
1749                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1750                         .module_offs = WKUP_MOD,
1751                         .idlest_reg_id = 1,
1752                         .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1753                 },
1754         },
1755         .slaves         = omap2430_gpio1_slaves,
1756         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
1757         .class          = &omap243x_gpio_hwmod_class,
1758         .dev_attr       = &gpio_dev_attr,
1759         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1760 };
1761
1762 /* gpio2 */
1763 static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
1764         { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1765 };
1766
1767 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1768         &omap2430_l4_wkup__gpio2,
1769 };
1770
1771 static struct omap_hwmod omap2430_gpio2_hwmod = {
1772         .name           = "gpio2",
1773         .mpu_irqs       = omap243x_gpio2_irqs,
1774         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio2_irqs),
1775         .main_clk       = "gpios_fck",
1776         .prcm           = {
1777                 .omap2 = {
1778                         .prcm_reg_id = 1,
1779                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1780                         .module_offs = WKUP_MOD,
1781                         .idlest_reg_id = 1,
1782                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1783                 },
1784         },
1785         .slaves         = omap2430_gpio2_slaves,
1786         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
1787         .class          = &omap243x_gpio_hwmod_class,
1788         .dev_attr       = &gpio_dev_attr,
1789         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1790 };
1791
1792 /* gpio3 */
1793 static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
1794         { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1795 };
1796
1797 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1798         &omap2430_l4_wkup__gpio3,
1799 };
1800
1801 static struct omap_hwmod omap2430_gpio3_hwmod = {
1802         .name           = "gpio3",
1803         .mpu_irqs       = omap243x_gpio3_irqs,
1804         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio3_irqs),
1805         .main_clk       = "gpios_fck",
1806         .prcm           = {
1807                 .omap2 = {
1808                         .prcm_reg_id = 1,
1809                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1810                         .module_offs = WKUP_MOD,
1811                         .idlest_reg_id = 1,
1812                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1813                 },
1814         },
1815         .slaves         = omap2430_gpio3_slaves,
1816         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
1817         .class          = &omap243x_gpio_hwmod_class,
1818         .dev_attr       = &gpio_dev_attr,
1819         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1820 };
1821
1822 /* gpio4 */
1823 static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
1824         { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1825 };
1826
1827 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1828         &omap2430_l4_wkup__gpio4,
1829 };
1830
1831 static struct omap_hwmod omap2430_gpio4_hwmod = {
1832         .name           = "gpio4",
1833         .mpu_irqs       = omap243x_gpio4_irqs,
1834         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio4_irqs),
1835         .main_clk       = "gpios_fck",
1836         .prcm           = {
1837                 .omap2 = {
1838                         .prcm_reg_id = 1,
1839                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1840                         .module_offs = WKUP_MOD,
1841                         .idlest_reg_id = 1,
1842                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1843                 },
1844         },
1845         .slaves         = omap2430_gpio4_slaves,
1846         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
1847         .class          = &omap243x_gpio_hwmod_class,
1848         .dev_attr       = &gpio_dev_attr,
1849         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1850 };
1851
1852 /* gpio5 */
1853 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1854         { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1855 };
1856
1857 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1858         &omap2430_l4_core__gpio5,
1859 };
1860
1861 static struct omap_hwmod omap2430_gpio5_hwmod = {
1862         .name           = "gpio5",
1863         .mpu_irqs       = omap243x_gpio5_irqs,
1864         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio5_irqs),
1865         .main_clk       = "gpio5_fck",
1866         .prcm           = {
1867                 .omap2 = {
1868                         .prcm_reg_id = 2,
1869                         .module_bit = OMAP2430_EN_GPIO5_SHIFT,
1870                         .module_offs = CORE_MOD,
1871                         .idlest_reg_id = 2,
1872                         .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1873                 },
1874         },
1875         .slaves         = omap2430_gpio5_slaves,
1876         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
1877         .class          = &omap243x_gpio_hwmod_class,
1878         .dev_attr       = &gpio_dev_attr,
1879         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1880 };
1881
1882 /* dma_system */
1883 static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
1884         .rev_offs       = 0x0000,
1885         .sysc_offs      = 0x002c,
1886         .syss_offs      = 0x0028,
1887         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1888                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1889                            SYSC_HAS_AUTOIDLE),
1890         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1891         .sysc_fields    = &omap_hwmod_sysc_type1,
1892 };
1893
1894 static struct omap_hwmod_class omap2430_dma_hwmod_class = {
1895         .name = "dma",
1896         .sysc = &omap2430_dma_sysc,
1897 };
1898
1899 /* dma attributes */
1900 static struct omap_dma_dev_attr dma_dev_attr = {
1901         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1902                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1903         .lch_count = 32,
1904 };
1905
1906 static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
1907         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1908         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1909         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1910         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1911 };
1912
1913 static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
1914         {
1915                 .pa_start       = 0x48056000,
1916                 .pa_end         = 0x4a0560ff,
1917                 .flags          = ADDR_TYPE_RT
1918         },
1919 };
1920
1921 /* dma_system -> L3 */
1922 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1923         .master         = &omap2430_dma_system_hwmod,
1924         .slave          = &omap2430_l3_main_hwmod,
1925         .clk            = "core_l3_ck",
1926         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1927 };
1928
1929 /* dma_system master ports */
1930 static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1931         &omap2430_dma_system__l3,
1932 };
1933
1934 /* l4_core -> dma_system */
1935 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1936         .master         = &omap2430_l4_core_hwmod,
1937         .slave          = &omap2430_dma_system_hwmod,
1938         .clk            = "sdma_ick",
1939         .addr           = omap2430_dma_system_addrs,
1940         .addr_cnt       = ARRAY_SIZE(omap2430_dma_system_addrs),
1941         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1942 };
1943
1944 /* dma_system slave ports */
1945 static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1946         &omap2430_l4_core__dma_system,
1947 };
1948
1949 static struct omap_hwmod omap2430_dma_system_hwmod = {
1950         .name           = "dma",
1951         .class          = &omap2430_dma_hwmod_class,
1952         .mpu_irqs       = omap2430_dma_system_irqs,
1953         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dma_system_irqs),
1954         .main_clk       = "core_l3_ck",
1955         .slaves         = omap2430_dma_system_slaves,
1956         .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
1957         .masters        = omap2430_dma_system_masters,
1958         .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
1959         .dev_attr       = &dma_dev_attr,
1960         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1961         .flags          = HWMOD_NO_IDLEST,
1962 };
1963
1964 /*
1965  * 'mailbox' class
1966  * mailbox module allowing communication between the on-chip processors
1967  * using a queued mailbox-interrupt mechanism.
1968  */
1969
1970 static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
1971         .rev_offs       = 0x000,
1972         .sysc_offs      = 0x010,
1973         .syss_offs      = 0x014,
1974         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1975                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1976         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1977         .sysc_fields    = &omap_hwmod_sysc_type1,
1978 };
1979
1980 static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
1981         .name = "mailbox",
1982         .sysc = &omap2430_mailbox_sysc,
1983 };
1984
1985 /* mailbox */
1986 static struct omap_hwmod omap2430_mailbox_hwmod;
1987 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1988         { .irq = 26 },
1989 };
1990
1991 static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
1992         {
1993                 .pa_start       = 0x48094000,
1994                 .pa_end         = 0x480941ff,
1995                 .flags          = ADDR_TYPE_RT,
1996         },
1997 };
1998
1999 /* l4_core -> mailbox */
2000 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
2001         .master         = &omap2430_l4_core_hwmod,
2002         .slave          = &omap2430_mailbox_hwmod,
2003         .addr           = omap2430_mailbox_addrs,
2004         .addr_cnt       = ARRAY_SIZE(omap2430_mailbox_addrs),
2005         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2006 };
2007
2008 /* mailbox slave ports */
2009 static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
2010         &omap2430_l4_core__mailbox,
2011 };
2012
2013 static struct omap_hwmod omap2430_mailbox_hwmod = {
2014         .name           = "mailbox",
2015         .class          = &omap2430_mailbox_hwmod_class,
2016         .mpu_irqs       = omap2430_mailbox_irqs,
2017         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mailbox_irqs),
2018         .main_clk       = "mailboxes_ick",
2019         .prcm           = {
2020                 .omap2 = {
2021                         .prcm_reg_id = 1,
2022                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2023                         .module_offs = CORE_MOD,
2024                         .idlest_reg_id = 1,
2025                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
2026                 },
2027         },
2028         .slaves         = omap2430_mailbox_slaves,
2029         .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
2030         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2031 };
2032
2033 /*
2034  * 'mcspi' class
2035  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2036  * bus
2037  */
2038
2039 static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
2040         .rev_offs       = 0x0000,
2041         .sysc_offs      = 0x0010,
2042         .syss_offs      = 0x0014,
2043         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2044                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2045                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2046         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2047         .sysc_fields    = &omap_hwmod_sysc_type1,
2048 };
2049
2050 static struct omap_hwmod_class omap2430_mcspi_class = {
2051         .name = "mcspi",
2052         .sysc = &omap2430_mcspi_sysc,
2053         .rev = OMAP2_MCSPI_REV,
2054 };
2055
2056 /* mcspi1 */
2057 static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
2058         { .irq = 65 },
2059 };
2060
2061 static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
2062         { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
2063         { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
2064         { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
2065         { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
2066         { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
2067         { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
2068         { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
2069         { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
2070 };
2071
2072 static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
2073         &omap2430_l4_core__mcspi1,
2074 };
2075
2076 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2077         .num_chipselect = 4,
2078 };
2079
2080 static struct omap_hwmod omap2430_mcspi1_hwmod = {
2081         .name           = "mcspi1_hwmod",
2082         .mpu_irqs       = omap2430_mcspi1_mpu_irqs,
2083         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
2084         .sdma_reqs      = omap2430_mcspi1_sdma_reqs,
2085         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
2086         .main_clk       = "mcspi1_fck",
2087         .prcm           = {
2088                 .omap2 = {
2089                         .module_offs = CORE_MOD,
2090                         .prcm_reg_id = 1,
2091                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
2092                         .idlest_reg_id = 1,
2093                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
2094                 },
2095         },
2096         .slaves         = omap2430_mcspi1_slaves,
2097         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
2098         .class          = &omap2430_mcspi_class,
2099         .dev_attr       = &omap_mcspi1_dev_attr,
2100         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2101 };
2102
2103 /* mcspi2 */
2104 static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
2105         { .irq = 66 },
2106 };
2107
2108 static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
2109         { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
2110         { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
2111         { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
2112         { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
2113 };
2114
2115 static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
2116         &omap2430_l4_core__mcspi2,
2117 };
2118
2119 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2120         .num_chipselect = 2,
2121 };
2122
2123 static struct omap_hwmod omap2430_mcspi2_hwmod = {
2124         .name           = "mcspi2_hwmod",
2125         .mpu_irqs       = omap2430_mcspi2_mpu_irqs,
2126         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
2127         .sdma_reqs      = omap2430_mcspi2_sdma_reqs,
2128         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
2129         .main_clk       = "mcspi2_fck",
2130         .prcm           = {
2131                 .omap2 = {
2132                         .module_offs = CORE_MOD,
2133                         .prcm_reg_id = 1,
2134                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
2135                         .idlest_reg_id = 1,
2136                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
2137                 },
2138         },
2139         .slaves         = omap2430_mcspi2_slaves,
2140         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
2141         .class          = &omap2430_mcspi_class,
2142         .dev_attr       = &omap_mcspi2_dev_attr,
2143         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2144 };
2145
2146 /* mcspi3 */
2147 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
2148         { .irq = 91 },
2149 };
2150
2151 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
2152         { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
2153         { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
2154         { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
2155         { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
2156 };
2157
2158 static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
2159         &omap2430_l4_core__mcspi3,
2160 };
2161
2162 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2163         .num_chipselect = 2,
2164 };
2165
2166 static struct omap_hwmod omap2430_mcspi3_hwmod = {
2167         .name           = "mcspi3_hwmod",
2168         .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
2169         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
2170         .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
2171         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
2172         .main_clk       = "mcspi3_fck",
2173         .prcm           = {
2174                 .omap2 = {
2175                         .module_offs = CORE_MOD,
2176                         .prcm_reg_id = 2,
2177                         .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
2178                         .idlest_reg_id = 2,
2179                         .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
2180                 },
2181         },
2182         .slaves         = omap2430_mcspi3_slaves,
2183         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
2184         .class          = &omap2430_mcspi_class,
2185         .dev_attr       = &omap_mcspi3_dev_attr,
2186         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2187 };
2188
2189 /*
2190  * usbhsotg
2191  */
2192 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
2193         .rev_offs       = 0x0400,
2194         .sysc_offs      = 0x0404,
2195         .syss_offs      = 0x0408,
2196         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2197                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2198                           SYSC_HAS_AUTOIDLE),
2199         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2200                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2201         .sysc_fields    = &omap_hwmod_sysc_type1,
2202 };
2203
2204 static struct omap_hwmod_class usbotg_class = {
2205         .name = "usbotg",
2206         .sysc = &omap2430_usbhsotg_sysc,
2207 };
2208
2209 /* usb_otg_hs */
2210 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
2211
2212         { .name = "mc", .irq = 92 },
2213         { .name = "dma", .irq = 93 },
2214 };
2215
2216 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
2217         .name           = "usb_otg_hs",
2218         .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
2219         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
2220         .main_clk       = "usbhs_ick",
2221         .prcm           = {
2222                 .omap2 = {
2223                         .prcm_reg_id = 1,
2224                         .module_bit = OMAP2430_EN_USBHS_MASK,
2225                         .module_offs = CORE_MOD,
2226                         .idlest_reg_id = 1,
2227                         .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
2228                 },
2229         },
2230         .masters        = omap2430_usbhsotg_masters,
2231         .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
2232         .slaves         = omap2430_usbhsotg_slaves,
2233         .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
2234         .class          = &usbotg_class,
2235         /*
2236          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
2237          * broken when autoidle is enabled
2238          * workaround is to disable the autoidle bit at module level.
2239          */
2240         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2241                                 | HWMOD_SWSUP_MSTANDBY,
2242         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
2243 };
2244
2245 /*
2246  * 'mcbsp' class
2247  * multi channel buffered serial port controller
2248  */
2249
2250 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
2251         .rev_offs       = 0x007C,
2252         .sysc_offs      = 0x008C,
2253         .sysc_flags     = (SYSC_HAS_SOFTRESET),
2254         .sysc_fields    = &omap_hwmod_sysc_type1,
2255 };
2256
2257 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
2258         .name = "mcbsp",
2259         .sysc = &omap2430_mcbsp_sysc,
2260         .rev  = MCBSP_CONFIG_TYPE2,
2261 };
2262
2263 /* mcbsp1 */
2264 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
2265         { .name = "tx",         .irq = 59 },
2266         { .name = "rx",         .irq = 60 },
2267         { .name = "ovr",        .irq = 61 },
2268         { .name = "common",     .irq = 64 },
2269 };
2270
2271 static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
2272         { .name = "rx", .dma_req = 32 },
2273         { .name = "tx", .dma_req = 31 },
2274 };
2275
2276 static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
2277         {
2278                 .name           = "mpu",
2279                 .pa_start       = 0x48074000,
2280                 .pa_end         = 0x480740ff,
2281                 .flags          = ADDR_TYPE_RT
2282         },
2283 };
2284
2285 /* l4_core -> mcbsp1 */
2286 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
2287         .master         = &omap2430_l4_core_hwmod,
2288         .slave          = &omap2430_mcbsp1_hwmod,
2289         .clk            = "mcbsp1_ick",
2290         .addr           = omap2430_mcbsp1_addrs,
2291         .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp1_addrs),
2292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2293 };
2294
2295 /* mcbsp1 slave ports */
2296 static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
2297         &omap2430_l4_core__mcbsp1,
2298 };
2299
2300 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
2301         .name           = "mcbsp1",
2302         .class          = &omap2430_mcbsp_hwmod_class,
2303         .mpu_irqs       = omap2430_mcbsp1_irqs,
2304         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp1_irqs),
2305         .sdma_reqs      = omap2430_mcbsp1_sdma_chs,
2306         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
2307         .main_clk       = "mcbsp1_fck",
2308         .prcm           = {
2309                 .omap2 = {
2310                         .prcm_reg_id = 1,
2311                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
2312                         .module_offs = CORE_MOD,
2313                         .idlest_reg_id = 1,
2314                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
2315                 },
2316         },
2317         .slaves         = omap2430_mcbsp1_slaves,
2318         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
2319         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2320 };
2321
2322 /* mcbsp2 */
2323 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
2324         { .name = "tx",         .irq = 62 },
2325         { .name = "rx",         .irq = 63 },
2326         { .name = "common",     .irq = 16 },
2327 };
2328
2329 static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
2330         { .name = "rx", .dma_req = 34 },
2331         { .name = "tx", .dma_req = 33 },
2332 };
2333
2334 static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
2335         {
2336                 .name           = "mpu",
2337                 .pa_start       = 0x48076000,
2338                 .pa_end         = 0x480760ff,
2339                 .flags          = ADDR_TYPE_RT
2340         },
2341 };
2342
2343 /* l4_core -> mcbsp2 */
2344 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
2345         .master         = &omap2430_l4_core_hwmod,
2346         .slave          = &omap2430_mcbsp2_hwmod,
2347         .clk            = "mcbsp2_ick",
2348         .addr           = omap2430_mcbsp2_addrs,
2349         .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp2_addrs),
2350         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2351 };
2352
2353 /* mcbsp2 slave ports */
2354 static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
2355         &omap2430_l4_core__mcbsp2,
2356 };
2357
2358 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
2359         .name           = "mcbsp2",
2360         .class          = &omap2430_mcbsp_hwmod_class,
2361         .mpu_irqs       = omap2430_mcbsp2_irqs,
2362         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp2_irqs),
2363         .sdma_reqs      = omap2430_mcbsp2_sdma_chs,
2364         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
2365         .main_clk       = "mcbsp2_fck",
2366         .prcm           = {
2367                 .omap2 = {
2368                         .prcm_reg_id = 1,
2369                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
2370                         .module_offs = CORE_MOD,
2371                         .idlest_reg_id = 1,
2372                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
2373                 },
2374         },
2375         .slaves         = omap2430_mcbsp2_slaves,
2376         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
2377         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2378 };
2379
2380 /* mcbsp3 */
2381 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
2382         { .name = "tx",         .irq = 89 },
2383         { .name = "rx",         .irq = 90 },
2384         { .name = "common",     .irq = 17 },
2385 };
2386
2387 static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
2388         { .name = "rx", .dma_req = 18 },
2389         { .name = "tx", .dma_req = 17 },
2390 };
2391
2392 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
2393         {
2394                 .name           = "mpu",
2395                 .pa_start       = 0x4808C000,
2396                 .pa_end         = 0x4808C0ff,
2397                 .flags          = ADDR_TYPE_RT
2398         },
2399 };
2400
2401 /* l4_core -> mcbsp3 */
2402 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
2403         .master         = &omap2430_l4_core_hwmod,
2404         .slave          = &omap2430_mcbsp3_hwmod,
2405         .clk            = "mcbsp3_ick",
2406         .addr           = omap2430_mcbsp3_addrs,
2407         .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp3_addrs),
2408         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2409 };
2410
2411 /* mcbsp3 slave ports */
2412 static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
2413         &omap2430_l4_core__mcbsp3,
2414 };
2415
2416 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
2417         .name           = "mcbsp3",
2418         .class          = &omap2430_mcbsp_hwmod_class,
2419         .mpu_irqs       = omap2430_mcbsp3_irqs,
2420         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp3_irqs),
2421         .sdma_reqs      = omap2430_mcbsp3_sdma_chs,
2422         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
2423         .main_clk       = "mcbsp3_fck",
2424         .prcm           = {
2425                 .omap2 = {
2426                         .prcm_reg_id = 1,
2427                         .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
2428                         .module_offs = CORE_MOD,
2429                         .idlest_reg_id = 2,
2430                         .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
2431                 },
2432         },
2433         .slaves         = omap2430_mcbsp3_slaves,
2434         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
2435         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2436 };
2437
2438 /* mcbsp4 */
2439 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
2440         { .name = "tx",         .irq = 54 },
2441         { .name = "rx",         .irq = 55 },
2442         { .name = "common",     .irq = 18 },
2443 };
2444
2445 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
2446         { .name = "rx", .dma_req = 20 },
2447         { .name = "tx", .dma_req = 19 },
2448 };
2449
2450 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
2451         {
2452                 .name           = "mpu",
2453                 .pa_start       = 0x4808E000,
2454                 .pa_end         = 0x4808E0ff,
2455                 .flags          = ADDR_TYPE_RT
2456         },
2457 };
2458
2459 /* l4_core -> mcbsp4 */
2460 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
2461         .master         = &omap2430_l4_core_hwmod,
2462         .slave          = &omap2430_mcbsp4_hwmod,
2463         .clk            = "mcbsp4_ick",
2464         .addr           = omap2430_mcbsp4_addrs,
2465         .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp4_addrs),
2466         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2467 };
2468
2469 /* mcbsp4 slave ports */
2470 static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
2471         &omap2430_l4_core__mcbsp4,
2472 };
2473
2474 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
2475         .name           = "mcbsp4",
2476         .class          = &omap2430_mcbsp_hwmod_class,
2477         .mpu_irqs       = omap2430_mcbsp4_irqs,
2478         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp4_irqs),
2479         .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
2480         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
2481         .main_clk       = "mcbsp4_fck",
2482         .prcm           = {
2483                 .omap2 = {
2484                         .prcm_reg_id = 1,
2485                         .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
2486                         .module_offs = CORE_MOD,
2487                         .idlest_reg_id = 2,
2488                         .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
2489                 },
2490         },
2491         .slaves         = omap2430_mcbsp4_slaves,
2492         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
2493         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2494 };
2495
2496 /* mcbsp5 */
2497 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
2498         { .name = "tx",         .irq = 81 },
2499         { .name = "rx",         .irq = 82 },
2500         { .name = "common",     .irq = 19 },
2501 };
2502
2503 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
2504         { .name = "rx", .dma_req = 22 },
2505         { .name = "tx", .dma_req = 21 },
2506 };
2507
2508 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
2509         {
2510                 .name           = "mpu",
2511                 .pa_start       = 0x48096000,
2512                 .pa_end         = 0x480960ff,
2513                 .flags          = ADDR_TYPE_RT
2514         },
2515 };
2516
2517 /* l4_core -> mcbsp5 */
2518 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
2519         .master         = &omap2430_l4_core_hwmod,
2520         .slave          = &omap2430_mcbsp5_hwmod,
2521         .clk            = "mcbsp5_ick",
2522         .addr           = omap2430_mcbsp5_addrs,
2523         .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp5_addrs),
2524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2525 };
2526
2527 /* mcbsp5 slave ports */
2528 static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
2529         &omap2430_l4_core__mcbsp5,
2530 };
2531
2532 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
2533         .name           = "mcbsp5",
2534         .class          = &omap2430_mcbsp_hwmod_class,
2535         .mpu_irqs       = omap2430_mcbsp5_irqs,
2536         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp5_irqs),
2537         .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
2538         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
2539         .main_clk       = "mcbsp5_fck",
2540         .prcm           = {
2541                 .omap2 = {
2542                         .prcm_reg_id = 1,
2543                         .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
2544                         .module_offs = CORE_MOD,
2545                         .idlest_reg_id = 2,
2546                         .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
2547                 },
2548         },
2549         .slaves         = omap2430_mcbsp5_slaves,
2550         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
2551         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2552 };
2553
2554 /* MMC/SD/SDIO common */
2555
2556 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
2557         .rev_offs       = 0x1fc,
2558         .sysc_offs      = 0x10,
2559         .syss_offs      = 0x14,
2560         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2561                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2562                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2563         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2564         .sysc_fields    = &omap_hwmod_sysc_type1,
2565 };
2566
2567 static struct omap_hwmod_class omap2430_mmc_class = {
2568         .name = "mmc",
2569         .sysc = &omap2430_mmc_sysc,
2570 };
2571
2572 /* MMC/SD/SDIO1 */
2573
2574 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
2575         { .irq = 83 },
2576 };
2577
2578 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
2579         { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
2580         { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
2581 };
2582
2583 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
2584         { .role = "dbck", .clk = "mmchsdb1_fck" },
2585 };
2586
2587 static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
2588         &omap2430_l4_core__mmc1,
2589 };
2590
2591 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2592         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2593 };
2594
2595 static struct omap_hwmod omap2430_mmc1_hwmod = {
2596         .name           = "mmc1",
2597         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2598         .mpu_irqs       = omap2430_mmc1_mpu_irqs,
2599         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
2600         .sdma_reqs      = omap2430_mmc1_sdma_reqs,
2601         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
2602         .opt_clks       = omap2430_mmc1_opt_clks,
2603         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
2604         .main_clk       = "mmchs1_fck",
2605         .prcm           = {
2606                 .omap2 = {
2607                         .module_offs = CORE_MOD,
2608                         .prcm_reg_id = 2,
2609                         .module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
2610                         .idlest_reg_id = 2,
2611                         .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
2612                 },
2613         },
2614         .dev_attr       = &mmc1_dev_attr,
2615         .slaves         = omap2430_mmc1_slaves,
2616         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
2617         .class          = &omap2430_mmc_class,
2618         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2619 };
2620
2621 /* MMC/SD/SDIO2 */
2622
2623 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
2624         { .irq = 86 },
2625 };
2626
2627 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
2628         { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
2629         { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
2630 };
2631
2632 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
2633         { .role = "dbck", .clk = "mmchsdb2_fck" },
2634 };
2635
2636 static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
2637         &omap2430_l4_core__mmc2,
2638 };
2639
2640 static struct omap_hwmod omap2430_mmc2_hwmod = {
2641         .name           = "mmc2",
2642         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2643         .mpu_irqs       = omap2430_mmc2_mpu_irqs,
2644         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
2645         .sdma_reqs      = omap2430_mmc2_sdma_reqs,
2646         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
2647         .opt_clks       = omap2430_mmc2_opt_clks,
2648         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
2649         .main_clk       = "mmchs2_fck",
2650         .prcm           = {
2651                 .omap2 = {
2652                         .module_offs = CORE_MOD,
2653                         .prcm_reg_id = 2,
2654                         .module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
2655                         .idlest_reg_id = 2,
2656                         .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
2657                 },
2658         },
2659         .slaves         = omap2430_mmc2_slaves,
2660         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
2661         .class          = &omap2430_mmc_class,
2662         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2663 };
2664
2665 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
2666         &omap2430_l3_main_hwmod,
2667         &omap2430_l4_core_hwmod,
2668         &omap2430_l4_wkup_hwmod,
2669         &omap2430_mpu_hwmod,
2670         &omap2430_iva_hwmod,
2671
2672         &omap2430_timer1_hwmod,
2673         &omap2430_timer2_hwmod,
2674         &omap2430_timer3_hwmod,
2675         &omap2430_timer4_hwmod,
2676         &omap2430_timer5_hwmod,
2677         &omap2430_timer6_hwmod,
2678         &omap2430_timer7_hwmod,
2679         &omap2430_timer8_hwmod,
2680         &omap2430_timer9_hwmod,
2681         &omap2430_timer10_hwmod,
2682         &omap2430_timer11_hwmod,
2683         &omap2430_timer12_hwmod,
2684
2685         &omap2430_wd_timer2_hwmod,
2686         &omap2430_uart1_hwmod,
2687         &omap2430_uart2_hwmod,
2688         &omap2430_uart3_hwmod,
2689         /* dss class */
2690         &omap2430_dss_core_hwmod,
2691         &omap2430_dss_dispc_hwmod,
2692         &omap2430_dss_rfbi_hwmod,
2693         &omap2430_dss_venc_hwmod,
2694         /* i2c class */
2695         &omap2430_i2c1_hwmod,
2696         &omap2430_i2c2_hwmod,
2697         &omap2430_mmc1_hwmod,
2698         &omap2430_mmc2_hwmod,
2699
2700         /* gpio class */
2701         &omap2430_gpio1_hwmod,
2702         &omap2430_gpio2_hwmod,
2703         &omap2430_gpio3_hwmod,
2704         &omap2430_gpio4_hwmod,
2705         &omap2430_gpio5_hwmod,
2706
2707         /* dma_system class*/
2708         &omap2430_dma_system_hwmod,
2709
2710         /* mcbsp class */
2711         &omap2430_mcbsp1_hwmod,
2712         &omap2430_mcbsp2_hwmod,
2713         &omap2430_mcbsp3_hwmod,
2714         &omap2430_mcbsp4_hwmod,
2715         &omap2430_mcbsp5_hwmod,
2716
2717         /* mailbox class */
2718         &omap2430_mailbox_hwmod,
2719
2720         /* mcspi class */
2721         &omap2430_mcspi1_hwmod,
2722         &omap2430_mcspi2_hwmod,
2723         &omap2430_mcspi3_hwmod,
2724
2725         /* usbotg class*/
2726         &omap2430_usbhsotg_hwmod,
2727
2728         NULL,
2729 };
2730
2731 int __init omap2430_hwmod_init(void)
2732 {
2733         return omap_hwmod_register(omap2430_hwmods);
2734 }