arch/arm/mach-omap2/omap_hwmod_2430_data.c

   1 /*
   2  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcspi.h>
  22 #include <plat/dmtimer.h>
  23 #include <plat/mmc.h>
  24 #include <plat/l3_2xxx.h>
  25
  26 #include "omap_hwmod_common_data.h"
  27
  28 #include "prm-regbits-24xx.h"
  29 #include "cm-regbits-24xx.h"
  30 #include "wd_timer.h"
  31
  32 /*
  33  * OMAP2430 hardware module integration data
  34  *
  35  * ALl of the data in this section should be autogeneratable from the
  36  * TI hardware database or other technical documentation.  Data that
  37  * is driver-specific or driver-kernel integration-specific belongs
  38  * elsewhere.
  39  */
  40
  41 static struct omap_hwmod omap2430_mpu_hwmod;
  42 static struct omap_hwmod omap2430_iva_hwmod;
  43 static struct omap_hwmod omap2430_l3_main_hwmod;
  44 static struct omap_hwmod omap2430_l4_core_hwmod;
  45 static struct omap_hwmod omap2430_dss_core_hwmod;
  46 static struct omap_hwmod omap2430_dss_dispc_hwmod;
  47 static struct omap_hwmod omap2430_dss_rfbi_hwmod;
  48 static struct omap_hwmod omap2430_dss_venc_hwmod;
  49 static struct omap_hwmod omap2430_wd_timer2_hwmod;
  50 static struct omap_hwmod omap2430_gpio1_hwmod;
  51 static struct omap_hwmod omap2430_gpio2_hwmod;
  52 static struct omap_hwmod omap2430_gpio3_hwmod;
  53 static struct omap_hwmod omap2430_gpio4_hwmod;
  54 static struct omap_hwmod omap2430_gpio5_hwmod;
  55 static struct omap_hwmod omap2430_dma_system_hwmod;
  56 static struct omap_hwmod omap2430_mcspi1_hwmod;
  57 static struct omap_hwmod omap2430_mcspi2_hwmod;
  58 static struct omap_hwmod omap2430_mcspi3_hwmod;
  59 static struct omap_hwmod omap2430_mmc1_hwmod;
  60 static struct omap_hwmod omap2430_mmc2_hwmod;
  61
  62 /* L3 -> L4_CORE interface */
  63 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
  64         .master = &omap2430_l3_main_hwmod,
  65         .slave  = &omap2430_l4_core_hwmod,
  66         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  67 };
  68
  69 /* MPU -> L3 interface */
  70 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
  71         .master = &omap2430_mpu_hwmod,
  72         .slave  = &omap2430_l3_main_hwmod,
  73         .user   = OCP_USER_MPU,
  74 };
  75
  76 /* Slave interfaces on the L3 interconnect */
  77 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
  78         &omap2430_mpu__l3_main,
  79 };
  80
  81 /* DSS -> l3 */
  82 static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
  83         .master         = &omap2430_dss_core_hwmod,
  84         .slave          = &omap2430_l3_main_hwmod,
  85         .fw = {
  86                 .omap2 = {
  87                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  88                         .flags  = OMAP_FIREWALL_L3,
  89                 }
  90         },
  91         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  92 };
  93
  94 /* Master interfaces on the L3 interconnect */
  95 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
  96         &omap2430_l3_main__l4_core,
  97 };
  98
  99 /* L3 */
 100 static struct omap_hwmod omap2430_l3_main_hwmod = {
 101         .name           = "l3_main",
 102         .class          = &l3_hwmod_class,
 103         .masters        = omap2430_l3_main_masters,
 104         .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
 105         .slaves         = omap2430_l3_main_slaves,
 106         .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
 107         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 108         .flags          = HWMOD_NO_IDLEST,
 109 };
 110
 111 static struct omap_hwmod omap2430_l4_wkup_hwmod;
 112 static struct omap_hwmod omap2430_uart1_hwmod;
 113 static struct omap_hwmod omap2430_uart2_hwmod;
 114 static struct omap_hwmod omap2430_uart3_hwmod;
 115 static struct omap_hwmod omap2430_i2c1_hwmod;
 116 static struct omap_hwmod omap2430_i2c2_hwmod;
 117
 118 static struct omap_hwmod omap2430_usbhsotg_hwmod;
 119
 120 /* l3_core -> usbhsotg  interface */
 121 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
 122         .master         = &omap2430_usbhsotg_hwmod,
 123         .slave          = &omap2430_l3_main_hwmod,
 124         .clk            = "core_l3_ck",
 125         .user           = OCP_USER_MPU,
 126 };
 127
 128 /* I2C IP block address space length (in bytes) */
 129 #define OMAP2_I2C_AS_LEN                128
 130
 131 /* L4 CORE -> I2C1 interface */
 132 static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
 133         {
 134                 .pa_start       = 0x48070000,
 135                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 136                 .flags          = ADDR_TYPE_RT,
 137         },
 138 };
 139
 140 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
 141         .master         = &omap2430_l4_core_hwmod,
 142         .slave          = &omap2430_i2c1_hwmod,
 143         .clk            = "i2c1_ick",
 144         .addr           = omap2430_i2c1_addr_space,
 145         .addr_cnt       = ARRAY_SIZE(omap2430_i2c1_addr_space),
 146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 147 };
 148
 149 /* L4 CORE -> I2C2 interface */
 150 static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
 151         {
 152                 .pa_start       = 0x48072000,
 153                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 154                 .flags          = ADDR_TYPE_RT,
 155         },
 156 };
 157
 158 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
 159         .master         = &omap2430_l4_core_hwmod,
 160         .slave          = &omap2430_i2c2_hwmod,
 161         .clk            = "i2c2_ick",
 162         .addr           = omap2430_i2c2_addr_space,
 163         .addr_cnt       = ARRAY_SIZE(omap2430_i2c2_addr_space),
 164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 165 };
 166
 167 /* L4_CORE -> L4_WKUP interface */
 168 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
 169         .master = &omap2430_l4_core_hwmod,
 170         .slave  = &omap2430_l4_wkup_hwmod,
 171         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 172 };
 173
 174 /* L4 CORE -> UART1 interface */
 175 static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
 176         {
 177                 .pa_start       = OMAP2_UART1_BASE,
 178                 .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
 179                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 180         },
 181 };
 182
 183 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 184         .master         = &omap2430_l4_core_hwmod,
 185         .slave          = &omap2430_uart1_hwmod,
 186         .clk            = "uart1_ick",
 187         .addr           = omap2430_uart1_addr_space,
 188         .addr_cnt       = ARRAY_SIZE(omap2430_uart1_addr_space),
 189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 190 };
 191
 192 /* L4 CORE -> UART2 interface */
 193 static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
 194         {
 195                 .pa_start       = OMAP2_UART2_BASE,
 196                 .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
 197                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 198         },
 199 };
 200
 201 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 202         .master         = &omap2430_l4_core_hwmod,
 203         .slave          = &omap2430_uart2_hwmod,
 204         .clk            = "uart2_ick",
 205         .addr           = omap2430_uart2_addr_space,
 206         .addr_cnt       = ARRAY_SIZE(omap2430_uart2_addr_space),
 207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 208 };
 209
 210 /* L4 PER -> UART3 interface */
 211 static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
 212         {
 213                 .pa_start       = OMAP2_UART3_BASE,
 214                 .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
 215                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 216         },
 217 };
 218
 219 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 220         .master         = &omap2430_l4_core_hwmod,
 221         .slave          = &omap2430_uart3_hwmod,
 222         .clk            = "uart3_ick",
 223         .addr           = omap2430_uart3_addr_space,
 224         .addr_cnt       = ARRAY_SIZE(omap2430_uart3_addr_space),
 225         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 226 };
 227
 228 /*
 229 * usbhsotg interface data
 230 */
 231 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
 232         {
 233                 .pa_start       = OMAP243X_HS_BASE,
 234                 .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
 235                 .flags          = ADDR_TYPE_RT
 236         },
 237 };
 238
 239 /*  l4_core ->usbhsotg  interface */
 240 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
 241         .master         = &omap2430_l4_core_hwmod,
 242         .slave          = &omap2430_usbhsotg_hwmod,
 243         .clk            = "usb_l4_ick",
 244         .addr           = omap2430_usbhsotg_addrs,
 245         .addr_cnt       = ARRAY_SIZE(omap2430_usbhsotg_addrs),
 246         .user           = OCP_USER_MPU,
 247 };
 248
 249 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
 250         &omap2430_usbhsotg__l3,
 251 };
 252
 253 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
 254         &omap2430_l4_core__usbhsotg,
 255 };
 256
 257 /* L4 CORE -> MMC1 interface */
 258 static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
 259         {
 260                 .pa_start       = 0x4809c000,
 261                 .pa_end         = 0x4809c1ff,
 262                 .flags          = ADDR_TYPE_RT,
 263         },
 264 };
 265
 266 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
 267         .master         = &omap2430_l4_core_hwmod,
 268         .slave          = &omap2430_mmc1_hwmod,
 269         .clk            = "mmchs1_ick",
 270         .addr           = omap2430_mmc1_addr_space,
 271         .addr_cnt       = ARRAY_SIZE(omap2430_mmc1_addr_space),
 272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 273 };
 274
 275 /* L4 CORE -> MMC2 interface */
 276 static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
 277         {
 278                 .pa_start       = 0x480b4000,
 279                 .pa_end         = 0x480b41ff,
 280                 .flags          = ADDR_TYPE_RT,
 281         },
 282 };
 283
 284 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
 285         .master         = &omap2430_l4_core_hwmod,
 286         .slave          = &omap2430_mmc2_hwmod,
 287         .addr           = omap2430_mmc2_addr_space,
 288         .clk            = "mmchs2_ick",
 289         .addr_cnt       = ARRAY_SIZE(omap2430_mmc2_addr_space),
 290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 291 };
 292
 293 /* Slave interfaces on the L4_CORE interconnect */
 294 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
 295         &omap2430_l3_main__l4_core,
 296 };
 297
 298 /* Master interfaces on the L4_CORE interconnect */
 299 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
 300         &omap2430_l4_core__l4_wkup,
 301         &omap2430_l4_core__mmc1,
 302         &omap2430_l4_core__mmc2,
 303 };
 304
 305 /* L4 CORE */
 306 static struct omap_hwmod omap2430_l4_core_hwmod = {
 307         .name           = "l4_core",
 308         .class          = &l4_hwmod_class,
 309         .masters        = omap2430_l4_core_masters,
 310         .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
 311         .slaves         = omap2430_l4_core_slaves,
 312         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
 313         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 314         .flags          = HWMOD_NO_IDLEST,
 315 };
 316
 317 /* Slave interfaces on the L4_WKUP interconnect */
 318 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
 319         &omap2430_l4_core__l4_wkup,
 320         &omap2_l4_core__uart1,
 321         &omap2_l4_core__uart2,
 322         &omap2_l4_core__uart3,
 323 };
 324
 325 /* Master interfaces on the L4_WKUP interconnect */
 326 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 327 };
 328
 329 /* l4 core -> mcspi1 interface */
 330 static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
 331         {
 332                 .pa_start       = 0x48098000,
 333                 .pa_end         = 0x480980ff,
 334                 .flags          = ADDR_TYPE_RT,
 335         },
 336 };
 337
 338 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
 339         .master         = &omap2430_l4_core_hwmod,
 340         .slave          = &omap2430_mcspi1_hwmod,
 341         .clk            = "mcspi1_ick",
 342         .addr           = omap2430_mcspi1_addr_space,
 343         .addr_cnt       = ARRAY_SIZE(omap2430_mcspi1_addr_space),
 344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 345 };
 346
 347 /* l4 core -> mcspi2 interface */
 348 static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
 349         {
 350                 .pa_start       = 0x4809a000,
 351                 .pa_end         = 0x4809a0ff,
 352                 .flags          = ADDR_TYPE_RT,
 353         },
 354 };
 355
 356 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
 357         .master         = &omap2430_l4_core_hwmod,
 358         .slave          = &omap2430_mcspi2_hwmod,
 359         .clk            = "mcspi2_ick",
 360         .addr           = omap2430_mcspi2_addr_space,
 361         .addr_cnt       = ARRAY_SIZE(omap2430_mcspi2_addr_space),
 362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 363 };
 364
 365 /* l4 core -> mcspi3 interface */
 366 static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
 367         {
 368                 .pa_start       = 0x480b8000,
 369                 .pa_end         = 0x480b80ff,
 370                 .flags          = ADDR_TYPE_RT,
 371         },
 372 };
 373
 374 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
 375         .master         = &omap2430_l4_core_hwmod,
 376         .slave          = &omap2430_mcspi3_hwmod,
 377         .clk            = "mcspi3_ick",
 378         .addr           = omap2430_mcspi3_addr_space,
 379         .addr_cnt       = ARRAY_SIZE(omap2430_mcspi3_addr_space),
 380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 381 };
 382
 383 /* L4 WKUP */
 384 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
 385         .name           = "l4_wkup",
 386         .class          = &l4_hwmod_class,
 387         .masters        = omap2430_l4_wkup_masters,
 388         .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
 389         .slaves         = omap2430_l4_wkup_slaves,
 390         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
 391         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 392         .flags          = HWMOD_NO_IDLEST,
 393 };
 394
 395 /* Master interfaces on the MPU device */
 396 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
 397         &omap2430_mpu__l3_main,
 398 };
 399
 400 /* MPU */
 401 static struct omap_hwmod omap2430_mpu_hwmod = {
 402         .name           = "mpu",
 403         .class          = &mpu_hwmod_class,
 404         .main_clk       = "mpu_ck",
 405         .masters        = omap2430_mpu_masters,
 406         .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
 407         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 408 };
 409
 410 /*
 411  * IVA2_1 interface data
 412  */
 413
 414 /* IVA2 <- L3 interface */
 415 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
 416         .master         = &omap2430_l3_main_hwmod,
 417         .slave          = &omap2430_iva_hwmod,
 418         .clk            = "dsp_fck",
 419         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 420 };
 421
 422 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
 423         &omap2430_l3__iva,
 424 };
 425
 426 /*
 427  * IVA2 (IVA2)
 428  */
 429
 430 static struct omap_hwmod omap2430_iva_hwmod = {
 431         .name           = "iva",
 432         .class          = &iva_hwmod_class,
 433         .masters        = omap2430_iva_masters,
 434         .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
 435         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 436 };
 437
 438 /* Timer Common */
 439 static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
 440         .rev_offs       = 0x0000,
 441         .sysc_offs      = 0x0010,
 442         .syss_offs      = 0x0014,
 443         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 444                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 445                            SYSC_HAS_AUTOIDLE),
 446         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 447         .sysc_fields    = &omap_hwmod_sysc_type1,
 448 };
 449
 450 static struct omap_hwmod_class omap2430_timer_hwmod_class = {
 451         .name = "timer",
 452         .sysc = &omap2430_timer_sysc,
 453         .rev = OMAP_TIMER_IP_VERSION_1,
 454 };
 455
 456 /* timer1 */
 457 static struct omap_hwmod omap2430_timer1_hwmod;
 458 static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
 459         { .irq = 37, },
 460 };
 461
 462 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
 463         {
 464                 .pa_start       = 0x49018000,
 465                 .pa_end         = 0x49018000 + SZ_1K - 1,
 466                 .flags          = ADDR_TYPE_RT
 467         },
 468 };
 469
 470 /* l4_wkup -> timer1 */
 471 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
 472         .master         = &omap2430_l4_wkup_hwmod,
 473         .slave          = &omap2430_timer1_hwmod,
 474         .clk            = "gpt1_ick",
 475         .addr           = omap2430_timer1_addrs,
 476         .addr_cnt       = ARRAY_SIZE(omap2430_timer1_addrs),
 477         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 478 };
 479
 480 /* timer1 slave port */
 481 static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
 482         &omap2430_l4_wkup__timer1,
 483 };
 484
 485 /* timer1 hwmod */
 486 static struct omap_hwmod omap2430_timer1_hwmod = {
 487         .name           = "timer1",
 488         .mpu_irqs       = omap2430_timer1_mpu_irqs,
 489         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
 490         .main_clk       = "gpt1_fck",
 491         .prcm           = {
 492                 .omap2 = {
 493                         .prcm_reg_id = 1,
 494                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 495                         .module_offs = WKUP_MOD,
 496                         .idlest_reg_id = 1,
 497                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 498                 },
 499         },
 500         .slaves         = omap2430_timer1_slaves,
 501         .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
 502         .class          = &omap2430_timer_hwmod_class,
 503         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 504 };
 505
 506 /* timer2 */
 507 static struct omap_hwmod omap2430_timer2_hwmod;
 508 static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
 509         { .irq = 38, },
 510 };
 511
 512 static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
 513         {
 514                 .pa_start       = 0x4802a000,
 515                 .pa_end         = 0x4802a000 + SZ_1K - 1,
 516                 .flags          = ADDR_TYPE_RT
 517         },
 518 };
 519
 520 /* l4_core -> timer2 */
 521 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
 522         .master         = &omap2430_l4_core_hwmod,
 523         .slave          = &omap2430_timer2_hwmod,
 524         .clk            = "gpt2_ick",
 525         .addr           = omap2430_timer2_addrs,
 526         .addr_cnt       = ARRAY_SIZE(omap2430_timer2_addrs),
 527         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 528 };
 529
 530 /* timer2 slave port */
 531 static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
 532         &omap2430_l4_core__timer2,
 533 };
 534
 535 /* timer2 hwmod */
 536 static struct omap_hwmod omap2430_timer2_hwmod = {
 537         .name           = "timer2",
 538         .mpu_irqs       = omap2430_timer2_mpu_irqs,
 539         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
 540         .main_clk       = "gpt2_fck",
 541         .prcm           = {
 542                 .omap2 = {
 543                         .prcm_reg_id = 1,
 544                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 545                         .module_offs = CORE_MOD,
 546                         .idlest_reg_id = 1,
 547                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 548                 },
 549         },
 550         .slaves         = omap2430_timer2_slaves,
 551         .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
 552         .class          = &omap2430_timer_hwmod_class,
 553         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 554 };
 555
 556 /* timer3 */
 557 static struct omap_hwmod omap2430_timer3_hwmod;
 558 static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
 559         { .irq = 39, },
 560 };
 561
 562 static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
 563         {
 564                 .pa_start       = 0x48078000,
 565                 .pa_end         = 0x48078000 + SZ_1K - 1,
 566                 .flags          = ADDR_TYPE_RT
 567         },
 568 };
 569
 570 /* l4_core -> timer3 */
 571 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
 572         .master         = &omap2430_l4_core_hwmod,
 573         .slave          = &omap2430_timer3_hwmod,
 574         .clk            = "gpt3_ick",
 575         .addr           = omap2430_timer3_addrs,
 576         .addr_cnt       = ARRAY_SIZE(omap2430_timer3_addrs),
 577         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 578 };
 579
 580 /* timer3 slave port */
 581 static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
 582         &omap2430_l4_core__timer3,
 583 };
 584
 585 /* timer3 hwmod */
 586 static struct omap_hwmod omap2430_timer3_hwmod = {
 587         .name           = "timer3",
 588         .mpu_irqs       = omap2430_timer3_mpu_irqs,
 589         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
 590         .main_clk       = "gpt3_fck",
 591         .prcm           = {
 592                 .omap2 = {
 593                         .prcm_reg_id = 1,
 594                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 595                         .module_offs = CORE_MOD,
 596                         .idlest_reg_id = 1,
 597                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 598                 },
 599         },
 600         .slaves         = omap2430_timer3_slaves,
 601         .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
 602         .class          = &omap2430_timer_hwmod_class,
 603         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 604 };
 605
 606 /* timer4 */
 607 static struct omap_hwmod omap2430_timer4_hwmod;
 608 static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
 609         { .irq = 40, },
 610 };
 611
 612 static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
 613         {
 614                 .pa_start       = 0x4807a000,
 615                 .pa_end         = 0x4807a000 + SZ_1K - 1,
 616                 .flags          = ADDR_TYPE_RT
 617         },
 618 };
 619
 620 /* l4_core -> timer4 */
 621 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
 622         .master         = &omap2430_l4_core_hwmod,
 623         .slave          = &omap2430_timer4_hwmod,
 624         .clk            = "gpt4_ick",
 625         .addr           = omap2430_timer4_addrs,
 626         .addr_cnt       = ARRAY_SIZE(omap2430_timer4_addrs),
 627         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 628 };
 629
 630 /* timer4 slave port */
 631 static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
 632         &omap2430_l4_core__timer4,
 633 };
 634
 635 /* timer4 hwmod */
 636 static struct omap_hwmod omap2430_timer4_hwmod = {
 637         .name           = "timer4",
 638         .mpu_irqs       = omap2430_timer4_mpu_irqs,
 639         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
 640         .main_clk       = "gpt4_fck",
 641         .prcm           = {
 642                 .omap2 = {
 643                         .prcm_reg_id = 1,
 644                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 645                         .module_offs = CORE_MOD,
 646                         .idlest_reg_id = 1,
 647                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 648                 },
 649         },
 650         .slaves         = omap2430_timer4_slaves,
 651         .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
 652         .class          = &omap2430_timer_hwmod_class,
 653         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 654 };
 655
 656 /* timer5 */
 657 static struct omap_hwmod omap2430_timer5_hwmod;
 658 static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
 659         { .irq = 41, },
 660 };
 661
 662 static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
 663         {
 664                 .pa_start       = 0x4807c000,
 665                 .pa_end         = 0x4807c000 + SZ_1K - 1,
 666                 .flags          = ADDR_TYPE_RT
 667         },
 668 };
 669
 670 /* l4_core -> timer5 */
 671 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
 672         .master         = &omap2430_l4_core_hwmod,
 673         .slave          = &omap2430_timer5_hwmod,
 674         .clk            = "gpt5_ick",
 675         .addr           = omap2430_timer5_addrs,
 676         .addr_cnt       = ARRAY_SIZE(omap2430_timer5_addrs),
 677         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 678 };
 679
 680 /* timer5 slave port */
 681 static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
 682         &omap2430_l4_core__timer5,
 683 };
 684
 685 /* timer5 hwmod */
 686 static struct omap_hwmod omap2430_timer5_hwmod = {
 687         .name           = "timer5",
 688         .mpu_irqs       = omap2430_timer5_mpu_irqs,
 689         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
 690         .main_clk       = "gpt5_fck",
 691         .prcm           = {
 692                 .omap2 = {
 693                         .prcm_reg_id = 1,
 694                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 695                         .module_offs = CORE_MOD,
 696                         .idlest_reg_id = 1,
 697                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 698                 },
 699         },
 700         .slaves         = omap2430_timer5_slaves,
 701         .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
 702         .class          = &omap2430_timer_hwmod_class,
 703         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 704 };
 705
 706 /* timer6 */
 707 static struct omap_hwmod omap2430_timer6_hwmod;
 708 static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
 709         { .irq = 42, },
 710 };
 711
 712 static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
 713         {
 714                 .pa_start       = 0x4807e000,
 715                 .pa_end         = 0x4807e000 + SZ_1K - 1,
 716                 .flags          = ADDR_TYPE_RT
 717         },
 718 };
 719
 720 /* l4_core -> timer6 */
 721 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
 722         .master         = &omap2430_l4_core_hwmod,
 723         .slave          = &omap2430_timer6_hwmod,
 724         .clk            = "gpt6_ick",
 725         .addr           = omap2430_timer6_addrs,
 726         .addr_cnt       = ARRAY_SIZE(omap2430_timer6_addrs),
 727         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 728 };
 729
 730 /* timer6 slave port */
 731 static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
 732         &omap2430_l4_core__timer6,
 733 };
 734
 735 /* timer6 hwmod */
 736 static struct omap_hwmod omap2430_timer6_hwmod = {
 737         .name           = "timer6",
 738         .mpu_irqs       = omap2430_timer6_mpu_irqs,
 739         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
 740         .main_clk       = "gpt6_fck",
 741         .prcm           = {
 742                 .omap2 = {
 743                         .prcm_reg_id = 1,
 744                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 745                         .module_offs = CORE_MOD,
 746                         .idlest_reg_id = 1,
 747                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 748                 },
 749         },
 750         .slaves         = omap2430_timer6_slaves,
 751         .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
 752         .class          = &omap2430_timer_hwmod_class,
 753         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 754 };
 755
 756 /* timer7 */
 757 static struct omap_hwmod omap2430_timer7_hwmod;
 758 static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
 759         { .irq = 43, },
 760 };
 761
 762 static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
 763         {
 764                 .pa_start       = 0x48080000,
 765                 .pa_end         = 0x48080000 + SZ_1K - 1,
 766                 .flags          = ADDR_TYPE_RT
 767         },
 768 };
 769
 770 /* l4_core -> timer7 */
 771 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
 772         .master         = &omap2430_l4_core_hwmod,
 773         .slave          = &omap2430_timer7_hwmod,
 774         .clk            = "gpt7_ick",
 775         .addr           = omap2430_timer7_addrs,
 776         .addr_cnt       = ARRAY_SIZE(omap2430_timer7_addrs),
 777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 778 };
 779
 780 /* timer7 slave port */
 781 static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
 782         &omap2430_l4_core__timer7,
 783 };
 784
 785 /* timer7 hwmod */
 786 static struct omap_hwmod omap2430_timer7_hwmod = {
 787         .name           = "timer7",
 788         .mpu_irqs       = omap2430_timer7_mpu_irqs,
 789         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
 790         .main_clk       = "gpt7_fck",
 791         .prcm           = {
 792                 .omap2 = {
 793                         .prcm_reg_id = 1,
 794                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 795                         .module_offs = CORE_MOD,
 796                         .idlest_reg_id = 1,
 797                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 798                 },
 799         },
 800         .slaves         = omap2430_timer7_slaves,
 801         .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
 802         .class          = &omap2430_timer_hwmod_class,
 803         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 804 };
 805
 806 /* timer8 */
 807 static struct omap_hwmod omap2430_timer8_hwmod;
 808 static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
 809         { .irq = 44, },
 810 };
 811
 812 static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
 813         {
 814                 .pa_start       = 0x48082000,
 815                 .pa_end         = 0x48082000 + SZ_1K - 1,
 816                 .flags          = ADDR_TYPE_RT
 817         },
 818 };
 819
 820 /* l4_core -> timer8 */
 821 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
 822         .master         = &omap2430_l4_core_hwmod,
 823         .slave          = &omap2430_timer8_hwmod,
 824         .clk            = "gpt8_ick",
 825         .addr           = omap2430_timer8_addrs,
 826         .addr_cnt       = ARRAY_SIZE(omap2430_timer8_addrs),
 827         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 828 };
 829
 830 /* timer8 slave port */
 831 static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
 832         &omap2430_l4_core__timer8,
 833 };
 834
 835 /* timer8 hwmod */
 836 static struct omap_hwmod omap2430_timer8_hwmod = {
 837         .name           = "timer8",
 838         .mpu_irqs       = omap2430_timer8_mpu_irqs,
 839         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
 840         .main_clk       = "gpt8_fck",
 841         .prcm           = {
 842                 .omap2 = {
 843                         .prcm_reg_id = 1,
 844                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 845                         .module_offs = CORE_MOD,
 846                         .idlest_reg_id = 1,
 847                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 848                 },
 849         },
 850         .slaves         = omap2430_timer8_slaves,
 851         .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
 852         .class          = &omap2430_timer_hwmod_class,
 853         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 854 };
 855
 856 /* timer9 */
 857 static struct omap_hwmod omap2430_timer9_hwmod;
 858 static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
 859         { .irq = 45, },
 860 };
 861
 862 static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
 863         {
 864                 .pa_start       = 0x48084000,
 865                 .pa_end         = 0x48084000 + SZ_1K - 1,
 866                 .flags          = ADDR_TYPE_RT
 867         },
 868 };
 869
 870 /* l4_core -> timer9 */
 871 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
 872         .master         = &omap2430_l4_core_hwmod,
 873         .slave          = &omap2430_timer9_hwmod,
 874         .clk            = "gpt9_ick",
 875         .addr           = omap2430_timer9_addrs,
 876         .addr_cnt       = ARRAY_SIZE(omap2430_timer9_addrs),
 877         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 878 };
 879
 880 /* timer9 slave port */
 881 static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
 882         &omap2430_l4_core__timer9,
 883 };
 884
 885 /* timer9 hwmod */
 886 static struct omap_hwmod omap2430_timer9_hwmod = {
 887         .name           = "timer9",
 888         .mpu_irqs       = omap2430_timer9_mpu_irqs,
 889         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
 890         .main_clk       = "gpt9_fck",
 891         .prcm           = {
 892                 .omap2 = {
 893                         .prcm_reg_id = 1,
 894                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 895                         .module_offs = CORE_MOD,
 896                         .idlest_reg_id = 1,
 897                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 898                 },
 899         },
 900         .slaves         = omap2430_timer9_slaves,
 901         .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
 902         .class          = &omap2430_timer_hwmod_class,
 903         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 904 };
 905
 906 /* timer10 */
 907 static struct omap_hwmod omap2430_timer10_hwmod;
 908 static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
 909         { .irq = 46, },
 910 };
 911
 912 static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
 913         {
 914                 .pa_start       = 0x48086000,
 915                 .pa_end         = 0x48086000 + SZ_1K - 1,
 916                 .flags          = ADDR_TYPE_RT
 917         },
 918 };
 919
 920 /* l4_core -> timer10 */
 921 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
 922         .master         = &omap2430_l4_core_hwmod,
 923         .slave          = &omap2430_timer10_hwmod,
 924         .clk            = "gpt10_ick",
 925         .addr           = omap2430_timer10_addrs,
 926         .addr_cnt       = ARRAY_SIZE(omap2430_timer10_addrs),
 927         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 928 };
 929
 930 /* timer10 slave port */
 931 static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
 932         &omap2430_l4_core__timer10,
 933 };
 934
 935 /* timer10 hwmod */
 936 static struct omap_hwmod omap2430_timer10_hwmod = {
 937         .name           = "timer10",
 938         .mpu_irqs       = omap2430_timer10_mpu_irqs,
 939         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
 940         .main_clk       = "gpt10_fck",
 941         .prcm           = {
 942                 .omap2 = {
 943                         .prcm_reg_id = 1,
 944                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 945                         .module_offs = CORE_MOD,
 946                         .idlest_reg_id = 1,
 947                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 948                 },
 949         },
 950         .slaves         = omap2430_timer10_slaves,
 951         .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
 952         .class          = &omap2430_timer_hwmod_class,
 953         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 954 };
 955
 956 /* timer11 */
 957 static struct omap_hwmod omap2430_timer11_hwmod;
 958 static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
 959         { .irq = 47, },
 960 };
 961
 962 static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
 963         {
 964                 .pa_start       = 0x48088000,
 965                 .pa_end         = 0x48088000 + SZ_1K - 1,
 966                 .flags          = ADDR_TYPE_RT
 967         },
 968 };
 969
 970 /* l4_core -> timer11 */
 971 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
 972         .master         = &omap2430_l4_core_hwmod,
 973         .slave          = &omap2430_timer11_hwmod,
 974         .clk            = "gpt11_ick",
 975         .addr           = omap2430_timer11_addrs,
 976         .addr_cnt       = ARRAY_SIZE(omap2430_timer11_addrs),
 977         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 978 };
 979
 980 /* timer11 slave port */
 981 static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
 982         &omap2430_l4_core__timer11,
 983 };
 984
 985 /* timer11 hwmod */
 986 static struct omap_hwmod omap2430_timer11_hwmod = {
 987         .name           = "timer11",
 988         .mpu_irqs       = omap2430_timer11_mpu_irqs,
 989         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
 990         .main_clk       = "gpt11_fck",
 991         .prcm           = {
 992                 .omap2 = {
 993                         .prcm_reg_id = 1,
 994                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 995                         .module_offs = CORE_MOD,
 996                         .idlest_reg_id = 1,
 997                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 998                 },
 999         },
1000         .slaves         = omap2430_timer11_slaves,
1001         .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
1002         .class          = &omap2430_timer_hwmod_class,
1003         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1004 };
1005
1006 /* timer12 */
1007 static struct omap_hwmod omap2430_timer12_hwmod;
1008 static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
1009         { .irq = 48, },
1010 };
1011
1012 static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
1013         {
1014                 .pa_start       = 0x4808a000,
1015                 .pa_end         = 0x4808a000 + SZ_1K - 1,
1016                 .flags          = ADDR_TYPE_RT
1017         },
1018 };
1019
1020 /* l4_core -> timer12 */
1021 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
1022         .master         = &omap2430_l4_core_hwmod,
1023         .slave          = &omap2430_timer12_hwmod,
1024         .clk            = "gpt12_ick",
1025         .addr           = omap2430_timer12_addrs,
1026         .addr_cnt       = ARRAY_SIZE(omap2430_timer12_addrs),
1027         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1028 };
1029
1030 /* timer12 slave port */
1031 static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
1032         &omap2430_l4_core__timer12,
1033 };
1034
1035 /* timer12 hwmod */
1036 static struct omap_hwmod omap2430_timer12_hwmod = {
1037         .name           = "timer12",
1038         .mpu_irqs       = omap2430_timer12_mpu_irqs,
1039         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
1040         .main_clk       = "gpt12_fck",
1041         .prcm           = {
1042                 .omap2 = {
1043                         .prcm_reg_id = 1,
1044                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
1045                         .module_offs = CORE_MOD,
1046                         .idlest_reg_id = 1,
1047                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
1048                 },
1049         },
1050         .slaves         = omap2430_timer12_slaves,
1051         .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
1052         .class          = &omap2430_timer_hwmod_class,
1053         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1054 };
1055
1056 /* l4_wkup -> wd_timer2 */
1057 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
1058         {
1059                 .pa_start       = 0x49016000,
1060                 .pa_end         = 0x4901607f,
1061                 .flags          = ADDR_TYPE_RT
1062         },
1063 };
1064
1065 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
1066         .master         = &omap2430_l4_wkup_hwmod,
1067         .slave          = &omap2430_wd_timer2_hwmod,
1068         .clk            = "mpu_wdt_ick",
1069         .addr           = omap2430_wd_timer2_addrs,
1070         .addr_cnt       = ARRAY_SIZE(omap2430_wd_timer2_addrs),
1071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1072 };
1073
1074 /*
1075  * 'wd_timer' class
1076  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1077  * overflow condition
1078  */
1079
1080 static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
1081         .rev_offs       = 0x0,
1082         .sysc_offs      = 0x0010,
1083         .syss_offs      = 0x0014,
1084         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
1085                            SYSC_HAS_AUTOIDLE),
1086         .sysc_fields    = &omap_hwmod_sysc_type1,
1087 };
1088
1089 static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
1090         .name           = "wd_timer",
1091         .sysc           = &omap2430_wd_timer_sysc,
1092         .pre_shutdown   = &omap2_wd_timer_disable
1093 };
1094
1095 /* wd_timer2 */
1096 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
1097         &omap2430_l4_wkup__wd_timer2,
1098 };
1099
1100 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
1101         .name           = "wd_timer2",
1102         .class          = &omap2430_wd_timer_hwmod_class,
1103         .main_clk       = "mpu_wdt_fck",
1104         .prcm           = {
1105                 .omap2 = {
1106                         .prcm_reg_id = 1,
1107                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1108                         .module_offs = WKUP_MOD,
1109                         .idlest_reg_id = 1,
1110                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
1111                 },
1112         },
1113         .slaves         = omap2430_wd_timer2_slaves,
1114         .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
1115         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1116 };
1117
1118 /* UART */
1119
1120 static struct omap_hwmod_class_sysconfig uart_sysc = {
1121         .rev_offs       = 0x50,
1122         .sysc_offs      = 0x54,
1123         .syss_offs      = 0x58,
1124         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
1125                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1126                            SYSC_HAS_AUTOIDLE),
1127         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1128         .sysc_fields    = &omap_hwmod_sysc_type1,
1129 };
1130
1131 static struct omap_hwmod_class uart_class = {
1132         .name = "uart",
1133         .sysc = &uart_sysc,
1134 };
1135
1136 /* UART1 */
1137
1138 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1139         { .irq = INT_24XX_UART1_IRQ, },
1140 };
1141
1142 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1143         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1144         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1145 };
1146
1147 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
1148         &omap2_l4_core__uart1,
1149 };
1150
1151 static struct omap_hwmod omap2430_uart1_hwmod = {
1152         .name           = "uart1",
1153         .mpu_irqs       = uart1_mpu_irqs,
1154         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
1155         .sdma_reqs      = uart1_sdma_reqs,
1156         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
1157         .main_clk       = "uart1_fck",
1158         .prcm           = {
1159                 .omap2 = {
1160                         .module_offs = CORE_MOD,
1161                         .prcm_reg_id = 1,
1162                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
1163                         .idlest_reg_id = 1,
1164                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
1165                 },
1166         },
1167         .slaves         = omap2430_uart1_slaves,
1168         .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
1169         .class          = &uart_class,
1170         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1171 };
1172
1173 /* UART2 */
1174
1175 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1176         { .irq = INT_24XX_UART2_IRQ, },
1177 };
1178
1179 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1180         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1181         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1182 };
1183
1184 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
1185         &omap2_l4_core__uart2,
1186 };
1187
1188 static struct omap_hwmod omap2430_uart2_hwmod = {
1189         .name           = "uart2",
1190         .mpu_irqs       = uart2_mpu_irqs,
1191         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
1192         .sdma_reqs      = uart2_sdma_reqs,
1193         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
1194         .main_clk       = "uart2_fck",
1195         .prcm           = {
1196                 .omap2 = {
1197                         .module_offs = CORE_MOD,
1198                         .prcm_reg_id = 1,
1199                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
1200                         .idlest_reg_id = 1,
1201                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
1202                 },
1203         },
1204         .slaves         = omap2430_uart2_slaves,
1205         .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
1206         .class          = &uart_class,
1207         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1208 };
1209
1210 /* UART3 */
1211
1212 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1213         { .irq = INT_24XX_UART3_IRQ, },
1214 };
1215
1216 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1217         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1218         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1219 };
1220
1221 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
1222         &omap2_l4_core__uart3,
1223 };
1224
1225 static struct omap_hwmod omap2430_uart3_hwmod = {
1226         .name           = "uart3",
1227         .mpu_irqs       = uart3_mpu_irqs,
1228         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
1229         .sdma_reqs      = uart3_sdma_reqs,
1230         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
1231         .main_clk       = "uart3_fck",
1232         .prcm           = {
1233                 .omap2 = {
1234                         .module_offs = CORE_MOD,
1235                         .prcm_reg_id = 2,
1236                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
1237                         .idlest_reg_id = 2,
1238                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
1239                 },
1240         },
1241         .slaves         = omap2430_uart3_slaves,
1242         .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
1243         .class          = &uart_class,
1244         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1245 };
1246
1247 /*
1248  * 'dss' class
1249  * display sub-system
1250  */
1251
1252 static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
1253         .rev_offs       = 0x0000,
1254         .sysc_offs      = 0x0010,
1255         .syss_offs      = 0x0014,
1256         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1257         .sysc_fields    = &omap_hwmod_sysc_type1,
1258 };
1259
1260 static struct omap_hwmod_class omap2430_dss_hwmod_class = {
1261         .name = "dss",
1262         .sysc = &omap2430_dss_sysc,
1263 };
1264
1265 /* dss */
1266 static struct omap_hwmod_irq_info omap2430_dss_irqs[] = {
1267         { .irq = 25 },
1268 };
1269 static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
1270         { .name = "dispc", .dma_req = 5 },
1271 };
1272
1273 /* dss */
1274 /* dss master ports */
1275 static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
1276         &omap2430_dss__l3,
1277 };
1278
1279 static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
1280         {
1281                 .pa_start       = 0x48050000,
1282                 .pa_end         = 0x480503FF,
1283                 .flags          = ADDR_TYPE_RT
1284         },
1285 };
1286
1287 /* l4_core -> dss */
1288 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
1289         .master         = &omap2430_l4_core_hwmod,
1290         .slave          = &omap2430_dss_core_hwmod,
1291         .clk            = "dss_ick",
1292         .addr           = omap2430_dss_addrs,
1293         .addr_cnt       = ARRAY_SIZE(omap2430_dss_addrs),
1294         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1295 };
1296
1297 /* dss slave ports */
1298 static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
1299         &omap2430_l4_core__dss,
1300 };
1301
1302 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1303         { .role = "tv_clk", .clk = "dss_54m_fck" },
1304         { .role = "sys_clk", .clk = "dss2_fck" },
1305 };
1306
1307 static struct omap_hwmod omap2430_dss_core_hwmod = {
1308         .name           = "dss_core",
1309         .class          = &omap2430_dss_hwmod_class,
1310         .main_clk       = "dss1_fck", /* instead of dss_fck */
1311         .mpu_irqs       = omap2430_dss_irqs,
1312         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dss_irqs),
1313         .sdma_reqs      = omap2430_dss_sdma_chs,
1314         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_dss_sdma_chs),
1315         .prcm           = {
1316                 .omap2 = {
1317                         .prcm_reg_id = 1,
1318                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1319                         .module_offs = CORE_MOD,
1320                         .idlest_reg_id = 1,
1321                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1322                 },
1323         },
1324         .opt_clks       = dss_opt_clks,
1325         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1326         .slaves         = omap2430_dss_slaves,
1327         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
1328         .masters        = omap2430_dss_masters,
1329         .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
1330         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1331         .flags          = HWMOD_NO_IDLEST,
1332 };
1333
1334 /*
1335  * 'dispc' class
1336  * display controller
1337  */
1338
1339 static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
1340         .rev_offs       = 0x0000,
1341         .sysc_offs      = 0x0010,
1342         .syss_offs      = 0x0014,
1343         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1344                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1345         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1346                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1347         .sysc_fields    = &omap_hwmod_sysc_type1,
1348 };
1349
1350 static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
1351         .name = "dispc",
1352         .sysc = &omap2430_dispc_sysc,
1353 };
1354
1355 static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
1356         {
1357                 .pa_start       = 0x48050400,
1358                 .pa_end         = 0x480507FF,
1359                 .flags          = ADDR_TYPE_RT
1360         },
1361 };
1362
1363 /* l4_core -> dss_dispc */
1364 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
1365         .master         = &omap2430_l4_core_hwmod,
1366         .slave          = &omap2430_dss_dispc_hwmod,
1367         .clk            = "dss_ick",
1368         .addr           = omap2430_dss_dispc_addrs,
1369         .addr_cnt       = ARRAY_SIZE(omap2430_dss_dispc_addrs),
1370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1371 };
1372
1373 /* dss_dispc slave ports */
1374 static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
1375         &omap2430_l4_core__dss_dispc,
1376 };
1377
1378 static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1379         .name           = "dss_dispc",
1380         .class          = &omap2430_dispc_hwmod_class,
1381         .main_clk       = "dss1_fck",
1382         .prcm           = {
1383                 .omap2 = {
1384                         .prcm_reg_id = 1,
1385                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1386                         .module_offs = CORE_MOD,
1387                         .idlest_reg_id = 1,
1388                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1389                 },
1390         },
1391         .slaves         = omap2430_dss_dispc_slaves,
1392         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1393         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1394         .flags          = HWMOD_NO_IDLEST,
1395 };
1396
1397 /*
1398  * 'rfbi' class
1399  * remote frame buffer interface
1400  */
1401
1402 static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
1403         .rev_offs       = 0x0000,
1404         .sysc_offs      = 0x0010,
1405         .syss_offs      = 0x0014,
1406         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1407                            SYSC_HAS_AUTOIDLE),
1408         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1409         .sysc_fields    = &omap_hwmod_sysc_type1,
1410 };
1411
1412 static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
1413         .name = "rfbi",
1414         .sysc = &omap2430_rfbi_sysc,
1415 };
1416
1417 static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
1418         {
1419                 .pa_start       = 0x48050800,
1420                 .pa_end         = 0x48050BFF,
1421                 .flags          = ADDR_TYPE_RT
1422         },
1423 };
1424
1425 /* l4_core -> dss_rfbi */
1426 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1427         .master         = &omap2430_l4_core_hwmod,
1428         .slave          = &omap2430_dss_rfbi_hwmod,
1429         .clk            = "dss_ick",
1430         .addr           = omap2430_dss_rfbi_addrs,
1431         .addr_cnt       = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
1432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1433 };
1434
1435 /* dss_rfbi slave ports */
1436 static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1437         &omap2430_l4_core__dss_rfbi,
1438 };
1439
1440 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1441         .name           = "dss_rfbi",
1442         .class          = &omap2430_rfbi_hwmod_class,
1443         .main_clk       = "dss1_fck",
1444         .prcm           = {
1445                 .omap2 = {
1446                         .prcm_reg_id = 1,
1447                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1448                         .module_offs = CORE_MOD,
1449                 },
1450         },
1451         .slaves         = omap2430_dss_rfbi_slaves,
1452         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1453         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1454         .flags          = HWMOD_NO_IDLEST,
1455 };
1456
1457 /*
1458  * 'venc' class
1459  * video encoder
1460  */
1461
1462 static struct omap_hwmod_class omap2430_venc_hwmod_class = {
1463         .name = "venc",
1464 };
1465
1466 /* dss_venc */
1467 static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
1468         {
1469                 .pa_start       = 0x48050C00,
1470                 .pa_end         = 0x48050FFF,
1471                 .flags          = ADDR_TYPE_RT
1472         },
1473 };
1474
1475 /* l4_core -> dss_venc */
1476 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1477         .master         = &omap2430_l4_core_hwmod,
1478         .slave          = &omap2430_dss_venc_hwmod,
1479         .clk            = "dss_54m_fck",
1480         .addr           = omap2430_dss_venc_addrs,
1481         .addr_cnt       = ARRAY_SIZE(omap2430_dss_venc_addrs),
1482         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1483 };
1484
1485 /* dss_venc slave ports */
1486 static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1487         &omap2430_l4_core__dss_venc,
1488 };
1489
1490 static struct omap_hwmod omap2430_dss_venc_hwmod = {
1491         .name           = "dss_venc",
1492         .class          = &omap2430_venc_hwmod_class,
1493         .main_clk       = "dss1_fck",
1494         .prcm           = {
1495                 .omap2 = {
1496                         .prcm_reg_id = 1,
1497                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1498                         .module_offs = CORE_MOD,
1499                 },
1500         },
1501         .slaves         = omap2430_dss_venc_slaves,
1502         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
1503         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1504         .flags          = HWMOD_NO_IDLEST,
1505 };
1506
1507 /* I2C common */
1508 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1509         .rev_offs       = 0x00,
1510         .sysc_offs      = 0x20,
1511         .syss_offs      = 0x10,
1512         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1513         .sysc_fields    = &omap_hwmod_sysc_type1,
1514 };
1515
1516 static struct omap_hwmod_class i2c_class = {
1517         .name           = "i2c",
1518         .sysc           = &i2c_sysc,
1519 };
1520
1521 static struct omap_i2c_dev_attr i2c_dev_attr = {
1522         .fifo_depth     = 8, /* bytes */
1523 };
1524
1525 /* I2C1 */
1526
1527 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1528         { .irq = INT_24XX_I2C1_IRQ, },
1529 };
1530
1531 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1532         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1533         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1534 };
1535
1536 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1537         &omap2430_l4_core__i2c1,
1538 };
1539
1540 static struct omap_hwmod omap2430_i2c1_hwmod = {
1541         .name           = "i2c1",
1542         .mpu_irqs       = i2c1_mpu_irqs,
1543         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
1544         .sdma_reqs      = i2c1_sdma_reqs,
1545         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1546         .main_clk       = "i2chs1_fck",
1547         .prcm           = {
1548                 .omap2 = {
1549                         /*
1550                          * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
1551                          * I2CHS IP's do not follow the usual pattern.
1552                          * prcm_reg_id alone cannot be used to program
1553                          * the iclk and fclk. Needs to be handled using
1554                          * additonal flags when clk handling is moved
1555                          * to hwmod framework.
1556                          */
1557                         .module_offs = CORE_MOD,
1558                         .prcm_reg_id = 1,
1559                         .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
1560                         .idlest_reg_id = 1,
1561                         .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
1562                 },
1563         },
1564         .slaves         = omap2430_i2c1_slaves,
1565         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
1566         .class          = &i2c_class,
1567         .dev_attr       = &i2c_dev_attr,
1568         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1569 };
1570
1571 /* I2C2 */
1572
1573 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1574         { .irq = INT_24XX_I2C2_IRQ, },
1575 };
1576
1577 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1578         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1579         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1580 };
1581
1582 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1583         &omap2430_l4_core__i2c2,
1584 };
1585
1586 static struct omap_hwmod omap2430_i2c2_hwmod = {
1587         .name           = "i2c2",
1588         .mpu_irqs       = i2c2_mpu_irqs,
1589         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
1590         .sdma_reqs      = i2c2_sdma_reqs,
1591         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1592         .main_clk       = "i2chs2_fck",
1593         .prcm           = {
1594                 .omap2 = {
1595                         .module_offs = CORE_MOD,
1596                         .prcm_reg_id = 1,
1597                         .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
1598                         .idlest_reg_id = 1,
1599                         .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
1600                 },
1601         },
1602         .slaves         = omap2430_i2c2_slaves,
1603         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
1604         .class          = &i2c_class,
1605         .dev_attr       = &i2c_dev_attr,
1606         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1607 };
1608
1609 /* l4_wkup -> gpio1 */
1610 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1611         {
1612                 .pa_start       = 0x4900C000,
1613                 .pa_end         = 0x4900C1ff,
1614                 .flags          = ADDR_TYPE_RT
1615         },
1616 };
1617
1618 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1619         .master         = &omap2430_l4_wkup_hwmod,
1620         .slave          = &omap2430_gpio1_hwmod,
1621         .clk            = "gpios_ick",
1622         .addr           = omap2430_gpio1_addr_space,
1623         .addr_cnt       = ARRAY_SIZE(omap2430_gpio1_addr_space),
1624         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1625 };
1626
1627 /* l4_wkup -> gpio2 */
1628 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1629         {
1630                 .pa_start       = 0x4900E000,
1631                 .pa_end         = 0x4900E1ff,
1632                 .flags          = ADDR_TYPE_RT
1633         },
1634 };
1635
1636 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1637         .master         = &omap2430_l4_wkup_hwmod,
1638         .slave          = &omap2430_gpio2_hwmod,
1639         .clk            = "gpios_ick",
1640         .addr           = omap2430_gpio2_addr_space,
1641         .addr_cnt       = ARRAY_SIZE(omap2430_gpio2_addr_space),
1642         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1643 };
1644
1645 /* l4_wkup -> gpio3 */
1646 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1647         {
1648                 .pa_start       = 0x49010000,
1649                 .pa_end         = 0x490101ff,
1650                 .flags          = ADDR_TYPE_RT
1651         },
1652 };
1653
1654 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1655         .master         = &omap2430_l4_wkup_hwmod,
1656         .slave          = &omap2430_gpio3_hwmod,
1657         .clk            = "gpios_ick",
1658         .addr           = omap2430_gpio3_addr_space,
1659         .addr_cnt       = ARRAY_SIZE(omap2430_gpio3_addr_space),
1660         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1661 };
1662
1663 /* l4_wkup -> gpio4 */
1664 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1665         {
1666                 .pa_start       = 0x49012000,
1667                 .pa_end         = 0x490121ff,
1668                 .flags          = ADDR_TYPE_RT
1669         },
1670 };
1671
1672 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1673         .master         = &omap2430_l4_wkup_hwmod,
1674         .slave          = &omap2430_gpio4_hwmod,
1675         .clk            = "gpios_ick",
1676         .addr           = omap2430_gpio4_addr_space,
1677         .addr_cnt       = ARRAY_SIZE(omap2430_gpio4_addr_space),
1678         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1679 };
1680
1681 /* l4_core -> gpio5 */
1682 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1683         {
1684                 .pa_start       = 0x480B6000,
1685                 .pa_end         = 0x480B61ff,
1686                 .flags          = ADDR_TYPE_RT
1687         },
1688 };
1689
1690 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1691         .master         = &omap2430_l4_core_hwmod,
1692         .slave          = &omap2430_gpio5_hwmod,
1693         .clk            = "gpio5_ick",
1694         .addr           = omap2430_gpio5_addr_space,
1695         .addr_cnt       = ARRAY_SIZE(omap2430_gpio5_addr_space),
1696         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1697 };
1698
1699 /* gpio dev_attr */
1700 static struct omap_gpio_dev_attr gpio_dev_attr = {
1701         .bank_width = 32,
1702         .dbck_flag = false,
1703 };
1704
1705 static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
1706         .rev_offs       = 0x0000,
1707         .sysc_offs      = 0x0010,
1708         .syss_offs      = 0x0014,
1709         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1710                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1711         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1712         .sysc_fields    = &omap_hwmod_sysc_type1,
1713 };
1714
1715 /*
1716  * 'gpio' class
1717  * general purpose io module
1718  */
1719 static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
1720         .name = "gpio",
1721         .sysc = &omap243x_gpio_sysc,
1722         .rev = 0,
1723 };
1724
1725 /* gpio1 */
1726 static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
1727         { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1728 };
1729
1730 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1731         &omap2430_l4_wkup__gpio1,
1732 };
1733
1734 static struct omap_hwmod omap2430_gpio1_hwmod = {
1735         .name           = "gpio1",
1736         .mpu_irqs       = omap243x_gpio1_irqs,
1737         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio1_irqs),
1738         .main_clk       = "gpios_fck",
1739         .prcm           = {
1740                 .omap2 = {
1741                         .prcm_reg_id = 1,
1742                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1743                         .module_offs = WKUP_MOD,
1744                         .idlest_reg_id = 1,
1745                         .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1746                 },
1747         },
1748         .slaves         = omap2430_gpio1_slaves,
1749         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
1750         .class          = &omap243x_gpio_hwmod_class,
1751         .dev_attr       = &gpio_dev_attr,
1752         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1753 };
1754
1755 /* gpio2 */
1756 static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
1757         { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1758 };
1759
1760 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1761         &omap2430_l4_wkup__gpio2,
1762 };
1763
1764 static struct omap_hwmod omap2430_gpio2_hwmod = {
1765         .name           = "gpio2",
1766         .mpu_irqs       = omap243x_gpio2_irqs,
1767         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio2_irqs),
1768         .main_clk       = "gpios_fck",
1769         .prcm           = {
1770                 .omap2 = {
1771                         .prcm_reg_id = 1,
1772                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1773                         .module_offs = WKUP_MOD,
1774                         .idlest_reg_id = 1,
1775                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1776                 },
1777         },
1778         .slaves         = omap2430_gpio2_slaves,
1779         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
1780         .class          = &omap243x_gpio_hwmod_class,
1781         .dev_attr       = &gpio_dev_attr,
1782         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1783 };
1784
1785 /* gpio3 */
1786 static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
1787         { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1788 };
1789
1790 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1791         &omap2430_l4_wkup__gpio3,
1792 };
1793
1794 static struct omap_hwmod omap2430_gpio3_hwmod = {
1795         .name           = "gpio3",
1796         .mpu_irqs       = omap243x_gpio3_irqs,
1797         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio3_irqs),
1798         .main_clk       = "gpios_fck",
1799         .prcm           = {
1800                 .omap2 = {
1801                         .prcm_reg_id = 1,
1802                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1803                         .module_offs = WKUP_MOD,
1804                         .idlest_reg_id = 1,
1805                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1806                 },
1807         },
1808         .slaves         = omap2430_gpio3_slaves,
1809         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
1810         .class          = &omap243x_gpio_hwmod_class,
1811         .dev_attr       = &gpio_dev_attr,
1812         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1813 };
1814
1815 /* gpio4 */
1816 static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
1817         { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1818 };
1819
1820 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1821         &omap2430_l4_wkup__gpio4,
1822 };
1823
1824 static struct omap_hwmod omap2430_gpio4_hwmod = {
1825         .name           = "gpio4",
1826         .mpu_irqs       = omap243x_gpio4_irqs,
1827         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio4_irqs),
1828         .main_clk       = "gpios_fck",
1829         .prcm           = {
1830                 .omap2 = {
1831                         .prcm_reg_id = 1,
1832                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1833                         .module_offs = WKUP_MOD,
1834                         .idlest_reg_id = 1,
1835                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1836                 },
1837         },
1838         .slaves         = omap2430_gpio4_slaves,
1839         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
1840         .class          = &omap243x_gpio_hwmod_class,
1841         .dev_attr       = &gpio_dev_attr,
1842         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1843 };
1844
1845 /* gpio5 */
1846 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1847         { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1848 };
1849
1850 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1851         &omap2430_l4_core__gpio5,
1852 };
1853
1854 static struct omap_hwmod omap2430_gpio5_hwmod = {
1855         .name           = "gpio5",
1856         .mpu_irqs       = omap243x_gpio5_irqs,
1857         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio5_irqs),
1858         .main_clk       = "gpio5_fck",
1859         .prcm           = {
1860                 .omap2 = {
1861                         .prcm_reg_id = 2,
1862                         .module_bit = OMAP2430_EN_GPIO5_SHIFT,
1863                         .module_offs = CORE_MOD,
1864                         .idlest_reg_id = 2,
1865                         .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1866                 },
1867         },
1868         .slaves         = omap2430_gpio5_slaves,
1869         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
1870         .class          = &omap243x_gpio_hwmod_class,
1871         .dev_attr       = &gpio_dev_attr,
1872         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1873 };
1874
1875 /* dma_system */
1876 static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
1877         .rev_offs       = 0x0000,
1878         .sysc_offs      = 0x002c,
1879         .syss_offs      = 0x0028,
1880         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1881                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1882                            SYSC_HAS_AUTOIDLE),
1883         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1884         .sysc_fields    = &omap_hwmod_sysc_type1,
1885 };
1886
1887 static struct omap_hwmod_class omap2430_dma_hwmod_class = {
1888         .name = "dma",
1889         .sysc = &omap2430_dma_sysc,
1890 };
1891
1892 /* dma attributes */
1893 static struct omap_dma_dev_attr dma_dev_attr = {
1894         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1895                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1896         .lch_count = 32,
1897 };
1898
1899 static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
1900         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1901         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1902         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1903         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1904 };
1905
1906 static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
1907         {
1908                 .pa_start       = 0x48056000,
1909                 .pa_end         = 0x4a0560ff,
1910                 .flags          = ADDR_TYPE_RT
1911         },
1912 };
1913
1914 /* dma_system -> L3 */
1915 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1916         .master         = &omap2430_dma_system_hwmod,
1917         .slave          = &omap2430_l3_main_hwmod,
1918         .clk            = "core_l3_ck",
1919         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1920 };
1921
1922 /* dma_system master ports */
1923 static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1924         &omap2430_dma_system__l3,
1925 };
1926
1927 /* l4_core -> dma_system */
1928 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1929         .master         = &omap2430_l4_core_hwmod,
1930         .slave          = &omap2430_dma_system_hwmod,
1931         .clk            = "sdma_ick",
1932         .addr           = omap2430_dma_system_addrs,
1933         .addr_cnt       = ARRAY_SIZE(omap2430_dma_system_addrs),
1934         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1935 };
1936
1937 /* dma_system slave ports */
1938 static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1939         &omap2430_l4_core__dma_system,
1940 };
1941
1942 static struct omap_hwmod omap2430_dma_system_hwmod = {
1943         .name           = "dma",
1944         .class          = &omap2430_dma_hwmod_class,
1945         .mpu_irqs       = omap2430_dma_system_irqs,
1946         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dma_system_irqs),
1947         .main_clk       = "core_l3_ck",
1948         .slaves         = omap2430_dma_system_slaves,
1949         .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
1950         .masters        = omap2430_dma_system_masters,
1951         .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
1952         .dev_attr       = &dma_dev_attr,
1953         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1954         .flags          = HWMOD_NO_IDLEST,
1955 };
1956
1957 /*
1958  * 'mcspi' class
1959  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1960  * bus
1961  */
1962
1963 static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
1964         .rev_offs       = 0x0000,
1965         .sysc_offs      = 0x0010,
1966         .syss_offs      = 0x0014,
1967         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1968                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1969                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1970         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1971         .sysc_fields    = &omap_hwmod_sysc_type1,
1972 };
1973
1974 static struct omap_hwmod_class omap2430_mcspi_class = {
1975         .name = "mcspi",
1976         .sysc = &omap2430_mcspi_sysc,
1977         .rev = OMAP2_MCSPI_REV,
1978 };
1979
1980 /* mcspi1 */
1981 static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
1982         { .irq = 65 },
1983 };
1984
1985 static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
1986         { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
1987         { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
1988         { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
1989         { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
1990         { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
1991         { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
1992         { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
1993         { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
1994 };
1995
1996 static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
1997         &omap2430_l4_core__mcspi1,
1998 };
1999
2000 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2001         .num_chipselect = 4,
2002 };
2003
2004 static struct omap_hwmod omap2430_mcspi1_hwmod = {
2005         .name           = "mcspi1_hwmod",
2006         .mpu_irqs       = omap2430_mcspi1_mpu_irqs,
2007         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
2008         .sdma_reqs      = omap2430_mcspi1_sdma_reqs,
2009         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
2010         .main_clk       = "mcspi1_fck",
2011         .prcm           = {
2012                 .omap2 = {
2013                         .module_offs = CORE_MOD,
2014                         .prcm_reg_id = 1,
2015                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
2016                         .idlest_reg_id = 1,
2017                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
2018                 },
2019         },
2020         .slaves         = omap2430_mcspi1_slaves,
2021         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
2022         .class          = &omap2430_mcspi_class,
2023         .dev_attr       = &omap_mcspi1_dev_attr,
2024         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2025 };
2026
2027 /* mcspi2 */
2028 static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
2029         { .irq = 66 },
2030 };
2031
2032 static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
2033         { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
2034         { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
2035         { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
2036         { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
2037 };
2038
2039 static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
2040         &omap2430_l4_core__mcspi2,
2041 };
2042
2043 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2044         .num_chipselect = 2,
2045 };
2046
2047 static struct omap_hwmod omap2430_mcspi2_hwmod = {
2048         .name           = "mcspi2_hwmod",
2049         .mpu_irqs       = omap2430_mcspi2_mpu_irqs,
2050         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
2051         .sdma_reqs      = omap2430_mcspi2_sdma_reqs,
2052         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
2053         .main_clk       = "mcspi2_fck",
2054         .prcm           = {
2055                 .omap2 = {
2056                         .module_offs = CORE_MOD,
2057                         .prcm_reg_id = 1,
2058                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
2059                         .idlest_reg_id = 1,
2060                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
2061                 },
2062         },
2063         .slaves         = omap2430_mcspi2_slaves,
2064         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
2065         .class          = &omap2430_mcspi_class,
2066         .dev_attr       = &omap_mcspi2_dev_attr,
2067         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2068 };
2069
2070 /* mcspi3 */
2071 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
2072         { .irq = 91 },
2073 };
2074
2075 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
2076         { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
2077         { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
2078         { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
2079         { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
2080 };
2081
2082 static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
2083         &omap2430_l4_core__mcspi3,
2084 };
2085
2086 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2087         .num_chipselect = 2,
2088 };
2089
2090 static struct omap_hwmod omap2430_mcspi3_hwmod = {
2091         .name           = "mcspi3_hwmod",
2092         .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
2093         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
2094         .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
2095         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
2096         .main_clk       = "mcspi3_fck",
2097         .prcm           = {
2098                 .omap2 = {
2099                         .module_offs = CORE_MOD,
2100                         .prcm_reg_id = 2,
2101                         .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
2102                         .idlest_reg_id = 2,
2103                         .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
2104                 },
2105         },
2106         .slaves         = omap2430_mcspi3_slaves,
2107         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
2108         .class          = &omap2430_mcspi_class,
2109         .dev_attr       = &omap_mcspi3_dev_attr,
2110         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2111 };
2112
2113 /*
2114  * usbhsotg
2115  */
2116 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
2117         .rev_offs       = 0x0400,
2118         .sysc_offs      = 0x0404,
2119         .syss_offs      = 0x0408,
2120         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2121                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2122                           SYSC_HAS_AUTOIDLE),
2123         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2124                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2125         .sysc_fields    = &omap_hwmod_sysc_type1,
2126 };
2127
2128 static struct omap_hwmod_class usbotg_class = {
2129         .name = "usbotg",
2130         .sysc = &omap2430_usbhsotg_sysc,
2131 };
2132
2133 /* usb_otg_hs */
2134 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
2135
2136         { .name = "mc", .irq = 92 },
2137         { .name = "dma", .irq = 93 },
2138 };
2139
2140 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
2141         .name           = "usb_otg_hs",
2142         .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
2143         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
2144         .main_clk       = "usbhs_ick",
2145         .prcm           = {
2146                 .omap2 = {
2147                         .prcm_reg_id = 1,
2148                         .module_bit = OMAP2430_EN_USBHS_MASK,
2149                         .module_offs = CORE_MOD,
2150                         .idlest_reg_id = 1,
2151                         .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
2152                 },
2153         },
2154         .masters        = omap2430_usbhsotg_masters,
2155         .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
2156         .slaves         = omap2430_usbhsotg_slaves,
2157         .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
2158         .class          = &usbotg_class,
2159         /*
2160          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
2161          * broken when autoidle is enabled
2162          * workaround is to disable the autoidle bit at module level.
2163          */
2164         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2165                                 | HWMOD_SWSUP_MSTANDBY,
2166         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
2167 };
2168
2169
2170
2171 /* MMC/SD/SDIO common */
2172
2173 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
2174         .rev_offs       = 0x1fc,
2175         .sysc_offs      = 0x10,
2176         .syss_offs      = 0x14,
2177         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2178                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2179                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2180         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2181         .sysc_fields    = &omap_hwmod_sysc_type1,
2182 };
2183
2184 static struct omap_hwmod_class omap2430_mmc_class = {
2185         .name = "mmc",
2186         .sysc = &omap2430_mmc_sysc,
2187 };
2188
2189 /* MMC/SD/SDIO1 */
2190
2191 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
2192         { .irq = 83 },
2193 };
2194
2195 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
2196         { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
2197         { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
2198 };
2199
2200 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
2201         { .role = "dbck", .clk = "mmchsdb1_fck" },
2202 };
2203
2204 static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
2205         &omap2430_l4_core__mmc1,
2206 };
2207
2208 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2209         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2210 };
2211
2212 static struct omap_hwmod omap2430_mmc1_hwmod = {
2213         .name           = "mmc1",
2214         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2215         .mpu_irqs       = omap2430_mmc1_mpu_irqs,
2216         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
2217         .sdma_reqs      = omap2430_mmc1_sdma_reqs,
2218         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
2219         .opt_clks       = omap2430_mmc1_opt_clks,
2220         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
2221         .main_clk       = "mmchs1_fck",
2222         .prcm           = {
2223                 .omap2 = {
2224                         .module_offs = CORE_MOD,
2225                         .prcm_reg_id = 2,
2226                         .module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
2227                         .idlest_reg_id = 2,
2228                         .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
2229                 },
2230         },
2231         .dev_attr       = &mmc1_dev_attr,
2232         .slaves         = omap2430_mmc1_slaves,
2233         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
2234         .class          = &omap2430_mmc_class,
2235         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2236 };
2237
2238 /* MMC/SD/SDIO2 */
2239
2240 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
2241         { .irq = 86 },
2242 };
2243
2244 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
2245         { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
2246         { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
2247 };
2248
2249 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
2250         { .role = "dbck", .clk = "mmchsdb2_fck" },
2251 };
2252
2253 static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
2254         &omap2430_l4_core__mmc2,
2255 };
2256
2257 static struct omap_hwmod omap2430_mmc2_hwmod = {
2258         .name           = "mmc2",
2259         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2260         .mpu_irqs       = omap2430_mmc2_mpu_irqs,
2261         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
2262         .sdma_reqs      = omap2430_mmc2_sdma_reqs,
2263         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
2264         .opt_clks       = omap2430_mmc2_opt_clks,
2265         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
2266         .main_clk       = "mmchs2_fck",
2267         .prcm           = {
2268                 .omap2 = {
2269                         .module_offs = CORE_MOD,
2270                         .prcm_reg_id = 2,
2271                         .module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
2272                         .idlest_reg_id = 2,
2273                         .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
2274                 },
2275         },
2276         .slaves         = omap2430_mmc2_slaves,
2277         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
2278         .class          = &omap2430_mmc_class,
2279         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2280 };
2281
2282 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
2283         &omap2430_l3_main_hwmod,
2284         &omap2430_l4_core_hwmod,
2285         &omap2430_l4_wkup_hwmod,
2286         &omap2430_mpu_hwmod,
2287         &omap2430_iva_hwmod,
2288
2289         &omap2430_timer1_hwmod,
2290         &omap2430_timer2_hwmod,
2291         &omap2430_timer3_hwmod,
2292         &omap2430_timer4_hwmod,
2293         &omap2430_timer5_hwmod,
2294         &omap2430_timer6_hwmod,
2295         &omap2430_timer7_hwmod,
2296         &omap2430_timer8_hwmod,
2297         &omap2430_timer9_hwmod,
2298         &omap2430_timer10_hwmod,
2299         &omap2430_timer11_hwmod,
2300         &omap2430_timer12_hwmod,
2301
2302         &omap2430_wd_timer2_hwmod,
2303         &omap2430_uart1_hwmod,
2304         &omap2430_uart2_hwmod,
2305         &omap2430_uart3_hwmod,
2306         /* dss class */
2307         &omap2430_dss_core_hwmod,
2308         &omap2430_dss_dispc_hwmod,
2309         &omap2430_dss_rfbi_hwmod,
2310         &omap2430_dss_venc_hwmod,
2311         /* i2c class */
2312         &omap2430_i2c1_hwmod,
2313         &omap2430_i2c2_hwmod,
2314         &omap2430_mmc1_hwmod,
2315         &omap2430_mmc2_hwmod,
2316
2317         /* gpio class */
2318         &omap2430_gpio1_hwmod,
2319         &omap2430_gpio2_hwmod,
2320         &omap2430_gpio3_hwmod,
2321         &omap2430_gpio4_hwmod,
2322         &omap2430_gpio5_hwmod,
2323
2324         /* dma_system class*/
2325         &omap2430_dma_system_hwmod,
2326
2327         /* mcspi class */
2328         &omap2430_mcspi1_hwmod,
2329         &omap2430_mcspi2_hwmod,
2330         &omap2430_mcspi3_hwmod,
2331
2332         /* usbotg class*/
2333         &omap2430_usbhsotg_hwmod,
2334
2335         NULL,
2336 };
2337
2338 int __init omap2430_hwmod_init(void)
2339 {
2340         return omap_hwmod_register(omap2430_hwmods);
2341 }