arch/arm/mach-omap2/omap_hwmod_2430_data.c

   1 /*
   2  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcspi.h>
  22 #include <plat/dmtimer.h>
  23 #include <plat/l3_2xxx.h>
  24
  25 #include "omap_hwmod_common_data.h"
  26
  27 #include "prm-regbits-24xx.h"
  28 #include "cm-regbits-24xx.h"
  29 #include "wd_timer.h"
  30
  31 /*
  32  * OMAP2430 hardware module integration data
  33  *
  34  * ALl of the data in this section should be autogeneratable from the
  35  * TI hardware database or other technical documentation.  Data that
  36  * is driver-specific or driver-kernel integration-specific belongs
  37  * elsewhere.
  38  */
  39
  40 static struct omap_hwmod omap2430_mpu_hwmod;
  41 static struct omap_hwmod omap2430_iva_hwmod;
  42 static struct omap_hwmod omap2430_l3_main_hwmod;
  43 static struct omap_hwmod omap2430_l4_core_hwmod;
  44 static struct omap_hwmod omap2430_dss_core_hwmod;
  45 static struct omap_hwmod omap2430_dss_dispc_hwmod;
  46 static struct omap_hwmod omap2430_dss_rfbi_hwmod;
  47 static struct omap_hwmod omap2430_dss_venc_hwmod;
  48 static struct omap_hwmod omap2430_wd_timer2_hwmod;
  49 static struct omap_hwmod omap2430_gpio1_hwmod;
  50 static struct omap_hwmod omap2430_gpio2_hwmod;
  51 static struct omap_hwmod omap2430_gpio3_hwmod;
  52 static struct omap_hwmod omap2430_gpio4_hwmod;
  53 static struct omap_hwmod omap2430_gpio5_hwmod;
  54 static struct omap_hwmod omap2430_dma_system_hwmod;
  55 static struct omap_hwmod omap2430_mcspi1_hwmod;
  56 static struct omap_hwmod omap2430_mcspi2_hwmod;
  57 static struct omap_hwmod omap2430_mcspi3_hwmod;
  58
  59 /* L3 -> L4_CORE interface */
  60 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
  61         .master = &omap2430_l3_main_hwmod,
  62         .slave  = &omap2430_l4_core_hwmod,
  63         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  64 };
  65
  66 /* MPU -> L3 interface */
  67 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
  68         .master = &omap2430_mpu_hwmod,
  69         .slave  = &omap2430_l3_main_hwmod,
  70         .user   = OCP_USER_MPU,
  71 };
  72
  73 /* Slave interfaces on the L3 interconnect */
  74 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
  75         &omap2430_mpu__l3_main,
  76 };
  77
  78 /* DSS -> l3 */
  79 static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
  80         .master         = &omap2430_dss_core_hwmod,
  81         .slave          = &omap2430_l3_main_hwmod,
  82         .fw = {
  83                 .omap2 = {
  84                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  85                         .flags  = OMAP_FIREWALL_L3,
  86                 }
  87         },
  88         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  89 };
  90
  91 /* Master interfaces on the L3 interconnect */
  92 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
  93         &omap2430_l3_main__l4_core,
  94 };
  95
  96 /* L3 */
  97 static struct omap_hwmod omap2430_l3_main_hwmod = {
  98         .name           = "l3_main",
  99         .class          = &l3_hwmod_class,
 100         .masters        = omap2430_l3_main_masters,
 101         .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
 102         .slaves         = omap2430_l3_main_slaves,
 103         .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
 104         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 105         .flags          = HWMOD_NO_IDLEST,
 106 };
 107
 108 static struct omap_hwmod omap2430_l4_wkup_hwmod;
 109 static struct omap_hwmod omap2430_uart1_hwmod;
 110 static struct omap_hwmod omap2430_uart2_hwmod;
 111 static struct omap_hwmod omap2430_uart3_hwmod;
 112 static struct omap_hwmod omap2430_i2c1_hwmod;
 113 static struct omap_hwmod omap2430_i2c2_hwmod;
 114
 115 static struct omap_hwmod omap2430_usbhsotg_hwmod;
 116
 117 /* l3_core -> usbhsotg  interface */
 118 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
 119         .master         = &omap2430_usbhsotg_hwmod,
 120         .slave          = &omap2430_l3_main_hwmod,
 121         .clk            = "core_l3_ck",
 122         .user           = OCP_USER_MPU,
 123 };
 124
 125 /* I2C IP block address space length (in bytes) */
 126 #define OMAP2_I2C_AS_LEN                128
 127
 128 /* L4 CORE -> I2C1 interface */
 129 static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
 130         {
 131                 .pa_start       = 0x48070000,
 132                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 133                 .flags          = ADDR_TYPE_RT,
 134         },
 135 };
 136
 137 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
 138         .master         = &omap2430_l4_core_hwmod,
 139         .slave          = &omap2430_i2c1_hwmod,
 140         .clk            = "i2c1_ick",
 141         .addr           = omap2430_i2c1_addr_space,
 142         .addr_cnt       = ARRAY_SIZE(omap2430_i2c1_addr_space),
 143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 144 };
 145
 146 /* L4 CORE -> I2C2 interface */
 147 static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
 148         {
 149                 .pa_start       = 0x48072000,
 150                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 151                 .flags          = ADDR_TYPE_RT,
 152         },
 153 };
 154
 155 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
 156         .master         = &omap2430_l4_core_hwmod,
 157         .slave          = &omap2430_i2c2_hwmod,
 158         .clk            = "i2c2_ick",
 159         .addr           = omap2430_i2c2_addr_space,
 160         .addr_cnt       = ARRAY_SIZE(omap2430_i2c2_addr_space),
 161         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 162 };
 163
 164 /* L4_CORE -> L4_WKUP interface */
 165 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
 166         .master = &omap2430_l4_core_hwmod,
 167         .slave  = &omap2430_l4_wkup_hwmod,
 168         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 169 };
 170
 171 /* L4 CORE -> UART1 interface */
 172 static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
 173         {
 174                 .pa_start       = OMAP2_UART1_BASE,
 175                 .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
 176                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 177         },
 178 };
 179
 180 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 181         .master         = &omap2430_l4_core_hwmod,
 182         .slave          = &omap2430_uart1_hwmod,
 183         .clk            = "uart1_ick",
 184         .addr           = omap2430_uart1_addr_space,
 185         .addr_cnt       = ARRAY_SIZE(omap2430_uart1_addr_space),
 186         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 187 };
 188
 189 /* L4 CORE -> UART2 interface */
 190 static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
 191         {
 192                 .pa_start       = OMAP2_UART2_BASE,
 193                 .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
 194                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 195         },
 196 };
 197
 198 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 199         .master         = &omap2430_l4_core_hwmod,
 200         .slave          = &omap2430_uart2_hwmod,
 201         .clk            = "uart2_ick",
 202         .addr           = omap2430_uart2_addr_space,
 203         .addr_cnt       = ARRAY_SIZE(omap2430_uart2_addr_space),
 204         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 205 };
 206
 207 /* L4 PER -> UART3 interface */
 208 static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
 209         {
 210                 .pa_start       = OMAP2_UART3_BASE,
 211                 .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
 212                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 213         },
 214 };
 215
 216 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 217         .master         = &omap2430_l4_core_hwmod,
 218         .slave          = &omap2430_uart3_hwmod,
 219         .clk            = "uart3_ick",
 220         .addr           = omap2430_uart3_addr_space,
 221         .addr_cnt       = ARRAY_SIZE(omap2430_uart3_addr_space),
 222         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 223 };
 224
 225 /*
 226 * usbhsotg interface data
 227 */
 228 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
 229         {
 230                 .pa_start       = OMAP243X_HS_BASE,
 231                 .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
 232                 .flags          = ADDR_TYPE_RT
 233         },
 234 };
 235
 236 /*  l4_core ->usbhsotg  interface */
 237 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
 238         .master         = &omap2430_l4_core_hwmod,
 239         .slave          = &omap2430_usbhsotg_hwmod,
 240         .clk            = "usb_l4_ick",
 241         .addr           = omap2430_usbhsotg_addrs,
 242         .addr_cnt       = ARRAY_SIZE(omap2430_usbhsotg_addrs),
 243         .user           = OCP_USER_MPU,
 244 };
 245
 246 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
 247         &omap2430_usbhsotg__l3,
 248 };
 249
 250 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
 251         &omap2430_l4_core__usbhsotg,
 252 };
 253
 254 /* Slave interfaces on the L4_CORE interconnect */
 255 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
 256         &omap2430_l3_main__l4_core,
 257 };
 258
 259 /* Master interfaces on the L4_CORE interconnect */
 260 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
 261         &omap2430_l4_core__l4_wkup,
 262 };
 263
 264 /* L4 CORE */
 265 static struct omap_hwmod omap2430_l4_core_hwmod = {
 266         .name           = "l4_core",
 267         .class          = &l4_hwmod_class,
 268         .masters        = omap2430_l4_core_masters,
 269         .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
 270         .slaves         = omap2430_l4_core_slaves,
 271         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
 272         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 273         .flags          = HWMOD_NO_IDLEST,
 274 };
 275
 276 /* Slave interfaces on the L4_WKUP interconnect */
 277 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
 278         &omap2430_l4_core__l4_wkup,
 279         &omap2_l4_core__uart1,
 280         &omap2_l4_core__uart2,
 281         &omap2_l4_core__uart3,
 282 };
 283
 284 /* Master interfaces on the L4_WKUP interconnect */
 285 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 286 };
 287
 288 /* l4 core -> mcspi1 interface */
 289 static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
 290         {
 291                 .pa_start       = 0x48098000,
 292                 .pa_end         = 0x480980ff,
 293                 .flags          = ADDR_TYPE_RT,
 294         },
 295 };
 296
 297 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
 298         .master         = &omap2430_l4_core_hwmod,
 299         .slave          = &omap2430_mcspi1_hwmod,
 300         .clk            = "mcspi1_ick",
 301         .addr           = omap2430_mcspi1_addr_space,
 302         .addr_cnt       = ARRAY_SIZE(omap2430_mcspi1_addr_space),
 303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 304 };
 305
 306 /* l4 core -> mcspi2 interface */
 307 static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
 308         {
 309                 .pa_start       = 0x4809a000,
 310                 .pa_end         = 0x4809a0ff,
 311                 .flags          = ADDR_TYPE_RT,
 312         },
 313 };
 314
 315 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
 316         .master         = &omap2430_l4_core_hwmod,
 317         .slave          = &omap2430_mcspi2_hwmod,
 318         .clk            = "mcspi2_ick",
 319         .addr           = omap2430_mcspi2_addr_space,
 320         .addr_cnt       = ARRAY_SIZE(omap2430_mcspi2_addr_space),
 321         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 322 };
 323
 324 /* l4 core -> mcspi3 interface */
 325 static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
 326         {
 327                 .pa_start       = 0x480b8000,
 328                 .pa_end         = 0x480b80ff,
 329                 .flags          = ADDR_TYPE_RT,
 330         },
 331 };
 332
 333 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
 334         .master         = &omap2430_l4_core_hwmod,
 335         .slave          = &omap2430_mcspi3_hwmod,
 336         .clk            = "mcspi3_ick",
 337         .addr           = omap2430_mcspi3_addr_space,
 338         .addr_cnt       = ARRAY_SIZE(omap2430_mcspi3_addr_space),
 339         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 340 };
 341
 342 /* L4 WKUP */
 343 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
 344         .name           = "l4_wkup",
 345         .class          = &l4_hwmod_class,
 346         .masters        = omap2430_l4_wkup_masters,
 347         .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
 348         .slaves         = omap2430_l4_wkup_slaves,
 349         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
 350         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 351         .flags          = HWMOD_NO_IDLEST,
 352 };
 353
 354 /* Master interfaces on the MPU device */
 355 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
 356         &omap2430_mpu__l3_main,
 357 };
 358
 359 /* MPU */
 360 static struct omap_hwmod omap2430_mpu_hwmod = {
 361         .name           = "mpu",
 362         .class          = &mpu_hwmod_class,
 363         .main_clk       = "mpu_ck",
 364         .masters        = omap2430_mpu_masters,
 365         .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
 366         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 367 };
 368
 369 /*
 370  * IVA2_1 interface data
 371  */
 372
 373 /* IVA2 <- L3 interface */
 374 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
 375         .master         = &omap2430_l3_main_hwmod,
 376         .slave          = &omap2430_iva_hwmod,
 377         .clk            = "dsp_fck",
 378         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 379 };
 380
 381 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
 382         &omap2430_l3__iva,
 383 };
 384
 385 /*
 386  * IVA2 (IVA2)
 387  */
 388
 389 static struct omap_hwmod omap2430_iva_hwmod = {
 390         .name           = "iva",
 391         .class          = &iva_hwmod_class,
 392         .masters        = omap2430_iva_masters,
 393         .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
 394         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 395 };
 396
 397 /* Timer Common */
 398 static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
 399         .rev_offs       = 0x0000,
 400         .sysc_offs      = 0x0010,
 401         .syss_offs      = 0x0014,
 402         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 403                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 404                            SYSC_HAS_AUTOIDLE),
 405         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 406         .sysc_fields    = &omap_hwmod_sysc_type1,
 407 };
 408
 409 static struct omap_hwmod_class omap2430_timer_hwmod_class = {
 410         .name = "timer",
 411         .sysc = &omap2430_timer_sysc,
 412         .rev = OMAP_TIMER_IP_VERSION_1,
 413 };
 414
 415 /* timer1 */
 416 static struct omap_hwmod omap2430_timer1_hwmod;
 417 static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
 418         { .irq = 37, },
 419 };
 420
 421 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
 422         {
 423                 .pa_start       = 0x49018000,
 424                 .pa_end         = 0x49018000 + SZ_1K - 1,
 425                 .flags          = ADDR_TYPE_RT
 426         },
 427 };
 428
 429 /* l4_wkup -> timer1 */
 430 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
 431         .master         = &omap2430_l4_wkup_hwmod,
 432         .slave          = &omap2430_timer1_hwmod,
 433         .clk            = "gpt1_ick",
 434         .addr           = omap2430_timer1_addrs,
 435         .addr_cnt       = ARRAY_SIZE(omap2430_timer1_addrs),
 436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 437 };
 438
 439 /* timer1 slave port */
 440 static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
 441         &omap2430_l4_wkup__timer1,
 442 };
 443
 444 /* timer1 hwmod */
 445 static struct omap_hwmod omap2430_timer1_hwmod = {
 446         .name           = "timer1",
 447         .mpu_irqs       = omap2430_timer1_mpu_irqs,
 448         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
 449         .main_clk       = "gpt1_fck",
 450         .prcm           = {
 451                 .omap2 = {
 452                         .prcm_reg_id = 1,
 453                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 454                         .module_offs = WKUP_MOD,
 455                         .idlest_reg_id = 1,
 456                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 457                 },
 458         },
 459         .slaves         = omap2430_timer1_slaves,
 460         .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
 461         .class          = &omap2430_timer_hwmod_class,
 462         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 463 };
 464
 465 /* timer2 */
 466 static struct omap_hwmod omap2430_timer2_hwmod;
 467 static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
 468         { .irq = 38, },
 469 };
 470
 471 static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
 472         {
 473                 .pa_start       = 0x4802a000,
 474                 .pa_end         = 0x4802a000 + SZ_1K - 1,
 475                 .flags          = ADDR_TYPE_RT
 476         },
 477 };
 478
 479 /* l4_core -> timer2 */
 480 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
 481         .master         = &omap2430_l4_core_hwmod,
 482         .slave          = &omap2430_timer2_hwmod,
 483         .clk            = "gpt2_ick",
 484         .addr           = omap2430_timer2_addrs,
 485         .addr_cnt       = ARRAY_SIZE(omap2430_timer2_addrs),
 486         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 487 };
 488
 489 /* timer2 slave port */
 490 static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
 491         &omap2430_l4_core__timer2,
 492 };
 493
 494 /* timer2 hwmod */
 495 static struct omap_hwmod omap2430_timer2_hwmod = {
 496         .name           = "timer2",
 497         .mpu_irqs       = omap2430_timer2_mpu_irqs,
 498         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
 499         .main_clk       = "gpt2_fck",
 500         .prcm           = {
 501                 .omap2 = {
 502                         .prcm_reg_id = 1,
 503                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 504                         .module_offs = CORE_MOD,
 505                         .idlest_reg_id = 1,
 506                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 507                 },
 508         },
 509         .slaves         = omap2430_timer2_slaves,
 510         .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
 511         .class          = &omap2430_timer_hwmod_class,
 512         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 513 };
 514
 515 /* timer3 */
 516 static struct omap_hwmod omap2430_timer3_hwmod;
 517 static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
 518         { .irq = 39, },
 519 };
 520
 521 static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
 522         {
 523                 .pa_start       = 0x48078000,
 524                 .pa_end         = 0x48078000 + SZ_1K - 1,
 525                 .flags          = ADDR_TYPE_RT
 526         },
 527 };
 528
 529 /* l4_core -> timer3 */
 530 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
 531         .master         = &omap2430_l4_core_hwmod,
 532         .slave          = &omap2430_timer3_hwmod,
 533         .clk            = "gpt3_ick",
 534         .addr           = omap2430_timer3_addrs,
 535         .addr_cnt       = ARRAY_SIZE(omap2430_timer3_addrs),
 536         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 537 };
 538
 539 /* timer3 slave port */
 540 static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
 541         &omap2430_l4_core__timer3,
 542 };
 543
 544 /* timer3 hwmod */
 545 static struct omap_hwmod omap2430_timer3_hwmod = {
 546         .name           = "timer3",
 547         .mpu_irqs       = omap2430_timer3_mpu_irqs,
 548         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
 549         .main_clk       = "gpt3_fck",
 550         .prcm           = {
 551                 .omap2 = {
 552                         .prcm_reg_id = 1,
 553                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 554                         .module_offs = CORE_MOD,
 555                         .idlest_reg_id = 1,
 556                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 557                 },
 558         },
 559         .slaves         = omap2430_timer3_slaves,
 560         .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
 561         .class          = &omap2430_timer_hwmod_class,
 562         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 563 };
 564
 565 /* timer4 */
 566 static struct omap_hwmod omap2430_timer4_hwmod;
 567 static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
 568         { .irq = 40, },
 569 };
 570
 571 static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
 572         {
 573                 .pa_start       = 0x4807a000,
 574                 .pa_end         = 0x4807a000 + SZ_1K - 1,
 575                 .flags          = ADDR_TYPE_RT
 576         },
 577 };
 578
 579 /* l4_core -> timer4 */
 580 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
 581         .master         = &omap2430_l4_core_hwmod,
 582         .slave          = &omap2430_timer4_hwmod,
 583         .clk            = "gpt4_ick",
 584         .addr           = omap2430_timer4_addrs,
 585         .addr_cnt       = ARRAY_SIZE(omap2430_timer4_addrs),
 586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 587 };
 588
 589 /* timer4 slave port */
 590 static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
 591         &omap2430_l4_core__timer4,
 592 };
 593
 594 /* timer4 hwmod */
 595 static struct omap_hwmod omap2430_timer4_hwmod = {
 596         .name           = "timer4",
 597         .mpu_irqs       = omap2430_timer4_mpu_irqs,
 598         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
 599         .main_clk       = "gpt4_fck",
 600         .prcm           = {
 601                 .omap2 = {
 602                         .prcm_reg_id = 1,
 603                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 604                         .module_offs = CORE_MOD,
 605                         .idlest_reg_id = 1,
 606                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 607                 },
 608         },
 609         .slaves         = omap2430_timer4_slaves,
 610         .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
 611         .class          = &omap2430_timer_hwmod_class,
 612         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 613 };
 614
 615 /* timer5 */
 616 static struct omap_hwmod omap2430_timer5_hwmod;
 617 static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
 618         { .irq = 41, },
 619 };
 620
 621 static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
 622         {
 623                 .pa_start       = 0x4807c000,
 624                 .pa_end         = 0x4807c000 + SZ_1K - 1,
 625                 .flags          = ADDR_TYPE_RT
 626         },
 627 };
 628
 629 /* l4_core -> timer5 */
 630 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
 631         .master         = &omap2430_l4_core_hwmod,
 632         .slave          = &omap2430_timer5_hwmod,
 633         .clk            = "gpt5_ick",
 634         .addr           = omap2430_timer5_addrs,
 635         .addr_cnt       = ARRAY_SIZE(omap2430_timer5_addrs),
 636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 637 };
 638
 639 /* timer5 slave port */
 640 static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
 641         &omap2430_l4_core__timer5,
 642 };
 643
 644 /* timer5 hwmod */
 645 static struct omap_hwmod omap2430_timer5_hwmod = {
 646         .name           = "timer5",
 647         .mpu_irqs       = omap2430_timer5_mpu_irqs,
 648         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
 649         .main_clk       = "gpt5_fck",
 650         .prcm           = {
 651                 .omap2 = {
 652                         .prcm_reg_id = 1,
 653                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 654                         .module_offs = CORE_MOD,
 655                         .idlest_reg_id = 1,
 656                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 657                 },
 658         },
 659         .slaves         = omap2430_timer5_slaves,
 660         .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
 661         .class          = &omap2430_timer_hwmod_class,
 662         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 663 };
 664
 665 /* timer6 */
 666 static struct omap_hwmod omap2430_timer6_hwmod;
 667 static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
 668         { .irq = 42, },
 669 };
 670
 671 static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
 672         {
 673                 .pa_start       = 0x4807e000,
 674                 .pa_end         = 0x4807e000 + SZ_1K - 1,
 675                 .flags          = ADDR_TYPE_RT
 676         },
 677 };
 678
 679 /* l4_core -> timer6 */
 680 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
 681         .master         = &omap2430_l4_core_hwmod,
 682         .slave          = &omap2430_timer6_hwmod,
 683         .clk            = "gpt6_ick",
 684         .addr           = omap2430_timer6_addrs,
 685         .addr_cnt       = ARRAY_SIZE(omap2430_timer6_addrs),
 686         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 687 };
 688
 689 /* timer6 slave port */
 690 static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
 691         &omap2430_l4_core__timer6,
 692 };
 693
 694 /* timer6 hwmod */
 695 static struct omap_hwmod omap2430_timer6_hwmod = {
 696         .name           = "timer6",
 697         .mpu_irqs       = omap2430_timer6_mpu_irqs,
 698         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
 699         .main_clk       = "gpt6_fck",
 700         .prcm           = {
 701                 .omap2 = {
 702                         .prcm_reg_id = 1,
 703                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 704                         .module_offs = CORE_MOD,
 705                         .idlest_reg_id = 1,
 706                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 707                 },
 708         },
 709         .slaves         = omap2430_timer6_slaves,
 710         .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
 711         .class          = &omap2430_timer_hwmod_class,
 712         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 713 };
 714
 715 /* timer7 */
 716 static struct omap_hwmod omap2430_timer7_hwmod;
 717 static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
 718         { .irq = 43, },
 719 };
 720
 721 static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
 722         {
 723                 .pa_start       = 0x48080000,
 724                 .pa_end         = 0x48080000 + SZ_1K - 1,
 725                 .flags          = ADDR_TYPE_RT
 726         },
 727 };
 728
 729 /* l4_core -> timer7 */
 730 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
 731         .master         = &omap2430_l4_core_hwmod,
 732         .slave          = &omap2430_timer7_hwmod,
 733         .clk            = "gpt7_ick",
 734         .addr           = omap2430_timer7_addrs,
 735         .addr_cnt       = ARRAY_SIZE(omap2430_timer7_addrs),
 736         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 737 };
 738
 739 /* timer7 slave port */
 740 static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
 741         &omap2430_l4_core__timer7,
 742 };
 743
 744 /* timer7 hwmod */
 745 static struct omap_hwmod omap2430_timer7_hwmod = {
 746         .name           = "timer7",
 747         .mpu_irqs       = omap2430_timer7_mpu_irqs,
 748         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
 749         .main_clk       = "gpt7_fck",
 750         .prcm           = {
 751                 .omap2 = {
 752                         .prcm_reg_id = 1,
 753                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 754                         .module_offs = CORE_MOD,
 755                         .idlest_reg_id = 1,
 756                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 757                 },
 758         },
 759         .slaves         = omap2430_timer7_slaves,
 760         .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
 761         .class          = &omap2430_timer_hwmod_class,
 762         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 763 };
 764
 765 /* timer8 */
 766 static struct omap_hwmod omap2430_timer8_hwmod;
 767 static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
 768         { .irq = 44, },
 769 };
 770
 771 static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
 772         {
 773                 .pa_start       = 0x48082000,
 774                 .pa_end         = 0x48082000 + SZ_1K - 1,
 775                 .flags          = ADDR_TYPE_RT
 776         },
 777 };
 778
 779 /* l4_core -> timer8 */
 780 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
 781         .master         = &omap2430_l4_core_hwmod,
 782         .slave          = &omap2430_timer8_hwmod,
 783         .clk            = "gpt8_ick",
 784         .addr           = omap2430_timer8_addrs,
 785         .addr_cnt       = ARRAY_SIZE(omap2430_timer8_addrs),
 786         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 787 };
 788
 789 /* timer8 slave port */
 790 static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
 791         &omap2430_l4_core__timer8,
 792 };
 793
 794 /* timer8 hwmod */
 795 static struct omap_hwmod omap2430_timer8_hwmod = {
 796         .name           = "timer8",
 797         .mpu_irqs       = omap2430_timer8_mpu_irqs,
 798         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
 799         .main_clk       = "gpt8_fck",
 800         .prcm           = {
 801                 .omap2 = {
 802                         .prcm_reg_id = 1,
 803                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 804                         .module_offs = CORE_MOD,
 805                         .idlest_reg_id = 1,
 806                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 807                 },
 808         },
 809         .slaves         = omap2430_timer8_slaves,
 810         .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
 811         .class          = &omap2430_timer_hwmod_class,
 812         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 813 };
 814
 815 /* timer9 */
 816 static struct omap_hwmod omap2430_timer9_hwmod;
 817 static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
 818         { .irq = 45, },
 819 };
 820
 821 static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
 822         {
 823                 .pa_start       = 0x48084000,
 824                 .pa_end         = 0x48084000 + SZ_1K - 1,
 825                 .flags          = ADDR_TYPE_RT
 826         },
 827 };
 828
 829 /* l4_core -> timer9 */
 830 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
 831         .master         = &omap2430_l4_core_hwmod,
 832         .slave          = &omap2430_timer9_hwmod,
 833         .clk            = "gpt9_ick",
 834         .addr           = omap2430_timer9_addrs,
 835         .addr_cnt       = ARRAY_SIZE(omap2430_timer9_addrs),
 836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 837 };
 838
 839 /* timer9 slave port */
 840 static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
 841         &omap2430_l4_core__timer9,
 842 };
 843
 844 /* timer9 hwmod */
 845 static struct omap_hwmod omap2430_timer9_hwmod = {
 846         .name           = "timer9",
 847         .mpu_irqs       = omap2430_timer9_mpu_irqs,
 848         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
 849         .main_clk       = "gpt9_fck",
 850         .prcm           = {
 851                 .omap2 = {
 852                         .prcm_reg_id = 1,
 853                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 854                         .module_offs = CORE_MOD,
 855                         .idlest_reg_id = 1,
 856                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 857                 },
 858         },
 859         .slaves         = omap2430_timer9_slaves,
 860         .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
 861         .class          = &omap2430_timer_hwmod_class,
 862         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 863 };
 864
 865 /* timer10 */
 866 static struct omap_hwmod omap2430_timer10_hwmod;
 867 static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
 868         { .irq = 46, },
 869 };
 870
 871 static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
 872         {
 873                 .pa_start       = 0x48086000,
 874                 .pa_end         = 0x48086000 + SZ_1K - 1,
 875                 .flags          = ADDR_TYPE_RT
 876         },
 877 };
 878
 879 /* l4_core -> timer10 */
 880 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
 881         .master         = &omap2430_l4_core_hwmod,
 882         .slave          = &omap2430_timer10_hwmod,
 883         .clk            = "gpt10_ick",
 884         .addr           = omap2430_timer10_addrs,
 885         .addr_cnt       = ARRAY_SIZE(omap2430_timer10_addrs),
 886         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 887 };
 888
 889 /* timer10 slave port */
 890 static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
 891         &omap2430_l4_core__timer10,
 892 };
 893
 894 /* timer10 hwmod */
 895 static struct omap_hwmod omap2430_timer10_hwmod = {
 896         .name           = "timer10",
 897         .mpu_irqs       = omap2430_timer10_mpu_irqs,
 898         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
 899         .main_clk       = "gpt10_fck",
 900         .prcm           = {
 901                 .omap2 = {
 902                         .prcm_reg_id = 1,
 903                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 904                         .module_offs = CORE_MOD,
 905                         .idlest_reg_id = 1,
 906                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 907                 },
 908         },
 909         .slaves         = omap2430_timer10_slaves,
 910         .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
 911         .class          = &omap2430_timer_hwmod_class,
 912         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 913 };
 914
 915 /* timer11 */
 916 static struct omap_hwmod omap2430_timer11_hwmod;
 917 static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
 918         { .irq = 47, },
 919 };
 920
 921 static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
 922         {
 923                 .pa_start       = 0x48088000,
 924                 .pa_end         = 0x48088000 + SZ_1K - 1,
 925                 .flags          = ADDR_TYPE_RT
 926         },
 927 };
 928
 929 /* l4_core -> timer11 */
 930 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
 931         .master         = &omap2430_l4_core_hwmod,
 932         .slave          = &omap2430_timer11_hwmod,
 933         .clk            = "gpt11_ick",
 934         .addr           = omap2430_timer11_addrs,
 935         .addr_cnt       = ARRAY_SIZE(omap2430_timer11_addrs),
 936         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 937 };
 938
 939 /* timer11 slave port */
 940 static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
 941         &omap2430_l4_core__timer11,
 942 };
 943
 944 /* timer11 hwmod */
 945 static struct omap_hwmod omap2430_timer11_hwmod = {
 946         .name           = "timer11",
 947         .mpu_irqs       = omap2430_timer11_mpu_irqs,
 948         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
 949         .main_clk       = "gpt11_fck",
 950         .prcm           = {
 951                 .omap2 = {
 952                         .prcm_reg_id = 1,
 953                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 954                         .module_offs = CORE_MOD,
 955                         .idlest_reg_id = 1,
 956                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 957                 },
 958         },
 959         .slaves         = omap2430_timer11_slaves,
 960         .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
 961         .class          = &omap2430_timer_hwmod_class,
 962         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 963 };
 964
 965 /* timer12 */
 966 static struct omap_hwmod omap2430_timer12_hwmod;
 967 static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
 968         { .irq = 48, },
 969 };
 970
 971 static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
 972         {
 973                 .pa_start       = 0x4808a000,
 974                 .pa_end         = 0x4808a000 + SZ_1K - 1,
 975                 .flags          = ADDR_TYPE_RT
 976         },
 977 };
 978
 979 /* l4_core -> timer12 */
 980 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
 981         .master         = &omap2430_l4_core_hwmod,
 982         .slave          = &omap2430_timer12_hwmod,
 983         .clk            = "gpt12_ick",
 984         .addr           = omap2430_timer12_addrs,
 985         .addr_cnt       = ARRAY_SIZE(omap2430_timer12_addrs),
 986         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 987 };
 988
 989 /* timer12 slave port */
 990 static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
 991         &omap2430_l4_core__timer12,
 992 };
 993
 994 /* timer12 hwmod */
 995 static struct omap_hwmod omap2430_timer12_hwmod = {
 996         .name           = "timer12",
 997         .mpu_irqs       = omap2430_timer12_mpu_irqs,
 998         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
 999         .main_clk       = "gpt12_fck",
1000         .prcm           = {
1001                 .omap2 = {
1002                         .prcm_reg_id = 1,
1003                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
1004                         .module_offs = CORE_MOD,
1005                         .idlest_reg_id = 1,
1006                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
1007                 },
1008         },
1009         .slaves         = omap2430_timer12_slaves,
1010         .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
1011         .class          = &omap2430_timer_hwmod_class,
1012         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1013 };
1014
1015 /* l4_wkup -> wd_timer2 */
1016 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
1017         {
1018                 .pa_start       = 0x49016000,
1019                 .pa_end         = 0x4901607f,
1020                 .flags          = ADDR_TYPE_RT
1021         },
1022 };
1023
1024 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
1025         .master         = &omap2430_l4_wkup_hwmod,
1026         .slave          = &omap2430_wd_timer2_hwmod,
1027         .clk            = "mpu_wdt_ick",
1028         .addr           = omap2430_wd_timer2_addrs,
1029         .addr_cnt       = ARRAY_SIZE(omap2430_wd_timer2_addrs),
1030         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1031 };
1032
1033 /*
1034  * 'wd_timer' class
1035  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1036  * overflow condition
1037  */
1038
1039 static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
1040         .rev_offs       = 0x0,
1041         .sysc_offs      = 0x0010,
1042         .syss_offs      = 0x0014,
1043         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
1044                            SYSC_HAS_AUTOIDLE),
1045         .sysc_fields    = &omap_hwmod_sysc_type1,
1046 };
1047
1048 static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
1049         .name           = "wd_timer",
1050         .sysc           = &omap2430_wd_timer_sysc,
1051         .pre_shutdown   = &omap2_wd_timer_disable
1052 };
1053
1054 /* wd_timer2 */
1055 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
1056         &omap2430_l4_wkup__wd_timer2,
1057 };
1058
1059 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
1060         .name           = "wd_timer2",
1061         .class          = &omap2430_wd_timer_hwmod_class,
1062         .main_clk       = "mpu_wdt_fck",
1063         .prcm           = {
1064                 .omap2 = {
1065                         .prcm_reg_id = 1,
1066                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1067                         .module_offs = WKUP_MOD,
1068                         .idlest_reg_id = 1,
1069                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
1070                 },
1071         },
1072         .slaves         = omap2430_wd_timer2_slaves,
1073         .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
1074         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1075 };
1076
1077 /* UART */
1078
1079 static struct omap_hwmod_class_sysconfig uart_sysc = {
1080         .rev_offs       = 0x50,
1081         .sysc_offs      = 0x54,
1082         .syss_offs      = 0x58,
1083         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
1084                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1085                            SYSC_HAS_AUTOIDLE),
1086         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1087         .sysc_fields    = &omap_hwmod_sysc_type1,
1088 };
1089
1090 static struct omap_hwmod_class uart_class = {
1091         .name = "uart",
1092         .sysc = &uart_sysc,
1093 };
1094
1095 /* UART1 */
1096
1097 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1098         { .irq = INT_24XX_UART1_IRQ, },
1099 };
1100
1101 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1102         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1103         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1104 };
1105
1106 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
1107         &omap2_l4_core__uart1,
1108 };
1109
1110 static struct omap_hwmod omap2430_uart1_hwmod = {
1111         .name           = "uart1",
1112         .mpu_irqs       = uart1_mpu_irqs,
1113         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
1114         .sdma_reqs      = uart1_sdma_reqs,
1115         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
1116         .main_clk       = "uart1_fck",
1117         .prcm           = {
1118                 .omap2 = {
1119                         .module_offs = CORE_MOD,
1120                         .prcm_reg_id = 1,
1121                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
1122                         .idlest_reg_id = 1,
1123                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
1124                 },
1125         },
1126         .slaves         = omap2430_uart1_slaves,
1127         .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
1128         .class          = &uart_class,
1129         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1130 };
1131
1132 /* UART2 */
1133
1134 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1135         { .irq = INT_24XX_UART2_IRQ, },
1136 };
1137
1138 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1139         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1140         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1141 };
1142
1143 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
1144         &omap2_l4_core__uart2,
1145 };
1146
1147 static struct omap_hwmod omap2430_uart2_hwmod = {
1148         .name           = "uart2",
1149         .mpu_irqs       = uart2_mpu_irqs,
1150         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
1151         .sdma_reqs      = uart2_sdma_reqs,
1152         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
1153         .main_clk       = "uart2_fck",
1154         .prcm           = {
1155                 .omap2 = {
1156                         .module_offs = CORE_MOD,
1157                         .prcm_reg_id = 1,
1158                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
1159                         .idlest_reg_id = 1,
1160                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
1161                 },
1162         },
1163         .slaves         = omap2430_uart2_slaves,
1164         .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
1165         .class          = &uart_class,
1166         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1167 };
1168
1169 /* UART3 */
1170
1171 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1172         { .irq = INT_24XX_UART3_IRQ, },
1173 };
1174
1175 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1176         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1177         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1178 };
1179
1180 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
1181         &omap2_l4_core__uart3,
1182 };
1183
1184 static struct omap_hwmod omap2430_uart3_hwmod = {
1185         .name           = "uart3",
1186         .mpu_irqs       = uart3_mpu_irqs,
1187         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
1188         .sdma_reqs      = uart3_sdma_reqs,
1189         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
1190         .main_clk       = "uart3_fck",
1191         .prcm           = {
1192                 .omap2 = {
1193                         .module_offs = CORE_MOD,
1194                         .prcm_reg_id = 2,
1195                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
1196                         .idlest_reg_id = 2,
1197                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
1198                 },
1199         },
1200         .slaves         = omap2430_uart3_slaves,
1201         .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
1202         .class          = &uart_class,
1203         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1204 };
1205
1206 /*
1207  * 'dss' class
1208  * display sub-system
1209  */
1210
1211 static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
1212         .rev_offs       = 0x0000,
1213         .sysc_offs      = 0x0010,
1214         .syss_offs      = 0x0014,
1215         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1216         .sysc_fields    = &omap_hwmod_sysc_type1,
1217 };
1218
1219 static struct omap_hwmod_class omap2430_dss_hwmod_class = {
1220         .name = "dss",
1221         .sysc = &omap2430_dss_sysc,
1222 };
1223
1224 /* dss */
1225 static struct omap_hwmod_irq_info omap2430_dss_irqs[] = {
1226         { .irq = 25 },
1227 };
1228 static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
1229         { .name = "dispc", .dma_req = 5 },
1230 };
1231
1232 /* dss */
1233 /* dss master ports */
1234 static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
1235         &omap2430_dss__l3,
1236 };
1237
1238 static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
1239         {
1240                 .pa_start       = 0x48050000,
1241                 .pa_end         = 0x480503FF,
1242                 .flags          = ADDR_TYPE_RT
1243         },
1244 };
1245
1246 /* l4_core -> dss */
1247 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
1248         .master         = &omap2430_l4_core_hwmod,
1249         .slave          = &omap2430_dss_core_hwmod,
1250         .clk            = "dss_ick",
1251         .addr           = omap2430_dss_addrs,
1252         .addr_cnt       = ARRAY_SIZE(omap2430_dss_addrs),
1253         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1254 };
1255
1256 /* dss slave ports */
1257 static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
1258         &omap2430_l4_core__dss,
1259 };
1260
1261 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1262         { .role = "tv_clk", .clk = "dss_54m_fck" },
1263         { .role = "sys_clk", .clk = "dss2_fck" },
1264 };
1265
1266 static struct omap_hwmod omap2430_dss_core_hwmod = {
1267         .name           = "dss_core",
1268         .class          = &omap2430_dss_hwmod_class,
1269         .main_clk       = "dss1_fck", /* instead of dss_fck */
1270         .mpu_irqs       = omap2430_dss_irqs,
1271         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dss_irqs),
1272         .sdma_reqs      = omap2430_dss_sdma_chs,
1273         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_dss_sdma_chs),
1274         .prcm           = {
1275                 .omap2 = {
1276                         .prcm_reg_id = 1,
1277                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1278                         .module_offs = CORE_MOD,
1279                         .idlest_reg_id = 1,
1280                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1281                 },
1282         },
1283         .opt_clks       = dss_opt_clks,
1284         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1285         .slaves         = omap2430_dss_slaves,
1286         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
1287         .masters        = omap2430_dss_masters,
1288         .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
1289         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1290         .flags          = HWMOD_NO_IDLEST,
1291 };
1292
1293 /*
1294  * 'dispc' class
1295  * display controller
1296  */
1297
1298 static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
1299         .rev_offs       = 0x0000,
1300         .sysc_offs      = 0x0010,
1301         .syss_offs      = 0x0014,
1302         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1303                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1304         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1305                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1306         .sysc_fields    = &omap_hwmod_sysc_type1,
1307 };
1308
1309 static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
1310         .name = "dispc",
1311         .sysc = &omap2430_dispc_sysc,
1312 };
1313
1314 static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
1315         {
1316                 .pa_start       = 0x48050400,
1317                 .pa_end         = 0x480507FF,
1318                 .flags          = ADDR_TYPE_RT
1319         },
1320 };
1321
1322 /* l4_core -> dss_dispc */
1323 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
1324         .master         = &omap2430_l4_core_hwmod,
1325         .slave          = &omap2430_dss_dispc_hwmod,
1326         .clk            = "dss_ick",
1327         .addr           = omap2430_dss_dispc_addrs,
1328         .addr_cnt       = ARRAY_SIZE(omap2430_dss_dispc_addrs),
1329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1330 };
1331
1332 /* dss_dispc slave ports */
1333 static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
1334         &omap2430_l4_core__dss_dispc,
1335 };
1336
1337 static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1338         .name           = "dss_dispc",
1339         .class          = &omap2430_dispc_hwmod_class,
1340         .main_clk       = "dss1_fck",
1341         .prcm           = {
1342                 .omap2 = {
1343                         .prcm_reg_id = 1,
1344                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1345                         .module_offs = CORE_MOD,
1346                         .idlest_reg_id = 1,
1347                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1348                 },
1349         },
1350         .slaves         = omap2430_dss_dispc_slaves,
1351         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1352         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1353         .flags          = HWMOD_NO_IDLEST,
1354 };
1355
1356 /*
1357  * 'rfbi' class
1358  * remote frame buffer interface
1359  */
1360
1361 static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
1362         .rev_offs       = 0x0000,
1363         .sysc_offs      = 0x0010,
1364         .syss_offs      = 0x0014,
1365         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1366                            SYSC_HAS_AUTOIDLE),
1367         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1368         .sysc_fields    = &omap_hwmod_sysc_type1,
1369 };
1370
1371 static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
1372         .name = "rfbi",
1373         .sysc = &omap2430_rfbi_sysc,
1374 };
1375
1376 static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
1377         {
1378                 .pa_start       = 0x48050800,
1379                 .pa_end         = 0x48050BFF,
1380                 .flags          = ADDR_TYPE_RT
1381         },
1382 };
1383
1384 /* l4_core -> dss_rfbi */
1385 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1386         .master         = &omap2430_l4_core_hwmod,
1387         .slave          = &omap2430_dss_rfbi_hwmod,
1388         .clk            = "dss_ick",
1389         .addr           = omap2430_dss_rfbi_addrs,
1390         .addr_cnt       = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
1391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1392 };
1393
1394 /* dss_rfbi slave ports */
1395 static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1396         &omap2430_l4_core__dss_rfbi,
1397 };
1398
1399 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1400         .name           = "dss_rfbi",
1401         .class          = &omap2430_rfbi_hwmod_class,
1402         .main_clk       = "dss1_fck",
1403         .prcm           = {
1404                 .omap2 = {
1405                         .prcm_reg_id = 1,
1406                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1407                         .module_offs = CORE_MOD,
1408                 },
1409         },
1410         .slaves         = omap2430_dss_rfbi_slaves,
1411         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1412         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1413         .flags          = HWMOD_NO_IDLEST,
1414 };
1415
1416 /*
1417  * 'venc' class
1418  * video encoder
1419  */
1420
1421 static struct omap_hwmod_class omap2430_venc_hwmod_class = {
1422         .name = "venc",
1423 };
1424
1425 /* dss_venc */
1426 static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
1427         {
1428                 .pa_start       = 0x48050C00,
1429                 .pa_end         = 0x48050FFF,
1430                 .flags          = ADDR_TYPE_RT
1431         },
1432 };
1433
1434 /* l4_core -> dss_venc */
1435 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1436         .master         = &omap2430_l4_core_hwmod,
1437         .slave          = &omap2430_dss_venc_hwmod,
1438         .clk            = "dss_54m_fck",
1439         .addr           = omap2430_dss_venc_addrs,
1440         .addr_cnt       = ARRAY_SIZE(omap2430_dss_venc_addrs),
1441         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1442 };
1443
1444 /* dss_venc slave ports */
1445 static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1446         &omap2430_l4_core__dss_venc,
1447 };
1448
1449 static struct omap_hwmod omap2430_dss_venc_hwmod = {
1450         .name           = "dss_venc",
1451         .class          = &omap2430_venc_hwmod_class,
1452         .main_clk       = "dss1_fck",
1453         .prcm           = {
1454                 .omap2 = {
1455                         .prcm_reg_id = 1,
1456                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1457                         .module_offs = CORE_MOD,
1458                 },
1459         },
1460         .slaves         = omap2430_dss_venc_slaves,
1461         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
1462         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1463         .flags          = HWMOD_NO_IDLEST,
1464 };
1465
1466 /* I2C common */
1467 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1468         .rev_offs       = 0x00,
1469         .sysc_offs      = 0x20,
1470         .syss_offs      = 0x10,
1471         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1472         .sysc_fields    = &omap_hwmod_sysc_type1,
1473 };
1474
1475 static struct omap_hwmod_class i2c_class = {
1476         .name           = "i2c",
1477         .sysc           = &i2c_sysc,
1478 };
1479
1480 static struct omap_i2c_dev_attr i2c_dev_attr = {
1481         .fifo_depth     = 8, /* bytes */
1482 };
1483
1484 /* I2C1 */
1485
1486 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1487         { .irq = INT_24XX_I2C1_IRQ, },
1488 };
1489
1490 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1491         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1492         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1493 };
1494
1495 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1496         &omap2430_l4_core__i2c1,
1497 };
1498
1499 static struct omap_hwmod omap2430_i2c1_hwmod = {
1500         .name           = "i2c1",
1501         .mpu_irqs       = i2c1_mpu_irqs,
1502         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
1503         .sdma_reqs      = i2c1_sdma_reqs,
1504         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1505         .main_clk       = "i2chs1_fck",
1506         .prcm           = {
1507                 .omap2 = {
1508                         /*
1509                          * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
1510                          * I2CHS IP's do not follow the usual pattern.
1511                          * prcm_reg_id alone cannot be used to program
1512                          * the iclk and fclk. Needs to be handled using
1513                          * additonal flags when clk handling is moved
1514                          * to hwmod framework.
1515                          */
1516                         .module_offs = CORE_MOD,
1517                         .prcm_reg_id = 1,
1518                         .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
1519                         .idlest_reg_id = 1,
1520                         .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
1521                 },
1522         },
1523         .slaves         = omap2430_i2c1_slaves,
1524         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
1525         .class          = &i2c_class,
1526         .dev_attr       = &i2c_dev_attr,
1527         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1528 };
1529
1530 /* I2C2 */
1531
1532 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1533         { .irq = INT_24XX_I2C2_IRQ, },
1534 };
1535
1536 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1537         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1538         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1539 };
1540
1541 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1542         &omap2430_l4_core__i2c2,
1543 };
1544
1545 static struct omap_hwmod omap2430_i2c2_hwmod = {
1546         .name           = "i2c2",
1547         .mpu_irqs       = i2c2_mpu_irqs,
1548         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
1549         .sdma_reqs      = i2c2_sdma_reqs,
1550         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1551         .main_clk       = "i2chs2_fck",
1552         .prcm           = {
1553                 .omap2 = {
1554                         .module_offs = CORE_MOD,
1555                         .prcm_reg_id = 1,
1556                         .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
1557                         .idlest_reg_id = 1,
1558                         .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
1559                 },
1560         },
1561         .slaves         = omap2430_i2c2_slaves,
1562         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
1563         .class          = &i2c_class,
1564         .dev_attr       = &i2c_dev_attr,
1565         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1566 };
1567
1568 /* l4_wkup -> gpio1 */
1569 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1570         {
1571                 .pa_start       = 0x4900C000,
1572                 .pa_end         = 0x4900C1ff,
1573                 .flags          = ADDR_TYPE_RT
1574         },
1575 };
1576
1577 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1578         .master         = &omap2430_l4_wkup_hwmod,
1579         .slave          = &omap2430_gpio1_hwmod,
1580         .clk            = "gpios_ick",
1581         .addr           = omap2430_gpio1_addr_space,
1582         .addr_cnt       = ARRAY_SIZE(omap2430_gpio1_addr_space),
1583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1584 };
1585
1586 /* l4_wkup -> gpio2 */
1587 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1588         {
1589                 .pa_start       = 0x4900E000,
1590                 .pa_end         = 0x4900E1ff,
1591                 .flags          = ADDR_TYPE_RT
1592         },
1593 };
1594
1595 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1596         .master         = &omap2430_l4_wkup_hwmod,
1597         .slave          = &omap2430_gpio2_hwmod,
1598         .clk            = "gpios_ick",
1599         .addr           = omap2430_gpio2_addr_space,
1600         .addr_cnt       = ARRAY_SIZE(omap2430_gpio2_addr_space),
1601         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1602 };
1603
1604 /* l4_wkup -> gpio3 */
1605 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1606         {
1607                 .pa_start       = 0x49010000,
1608                 .pa_end         = 0x490101ff,
1609                 .flags          = ADDR_TYPE_RT
1610         },
1611 };
1612
1613 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1614         .master         = &omap2430_l4_wkup_hwmod,
1615         .slave          = &omap2430_gpio3_hwmod,
1616         .clk            = "gpios_ick",
1617         .addr           = omap2430_gpio3_addr_space,
1618         .addr_cnt       = ARRAY_SIZE(omap2430_gpio3_addr_space),
1619         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1620 };
1621
1622 /* l4_wkup -> gpio4 */
1623 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1624         {
1625                 .pa_start       = 0x49012000,
1626                 .pa_end         = 0x490121ff,
1627                 .flags          = ADDR_TYPE_RT
1628         },
1629 };
1630
1631 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1632         .master         = &omap2430_l4_wkup_hwmod,
1633         .slave          = &omap2430_gpio4_hwmod,
1634         .clk            = "gpios_ick",
1635         .addr           = omap2430_gpio4_addr_space,
1636         .addr_cnt       = ARRAY_SIZE(omap2430_gpio4_addr_space),
1637         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1638 };
1639
1640 /* l4_core -> gpio5 */
1641 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1642         {
1643                 .pa_start       = 0x480B6000,
1644                 .pa_end         = 0x480B61ff,
1645                 .flags          = ADDR_TYPE_RT
1646         },
1647 };
1648
1649 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1650         .master         = &omap2430_l4_core_hwmod,
1651         .slave          = &omap2430_gpio5_hwmod,
1652         .clk            = "gpio5_ick",
1653         .addr           = omap2430_gpio5_addr_space,
1654         .addr_cnt       = ARRAY_SIZE(omap2430_gpio5_addr_space),
1655         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1656 };
1657
1658 /* gpio dev_attr */
1659 static struct omap_gpio_dev_attr gpio_dev_attr = {
1660         .bank_width = 32,
1661         .dbck_flag = false,
1662 };
1663
1664 static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
1665         .rev_offs       = 0x0000,
1666         .sysc_offs      = 0x0010,
1667         .syss_offs      = 0x0014,
1668         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1669                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1670         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1671         .sysc_fields    = &omap_hwmod_sysc_type1,
1672 };
1673
1674 /*
1675  * 'gpio' class
1676  * general purpose io module
1677  */
1678 static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
1679         .name = "gpio",
1680         .sysc = &omap243x_gpio_sysc,
1681         .rev = 0,
1682 };
1683
1684 /* gpio1 */
1685 static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
1686         { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1687 };
1688
1689 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1690         &omap2430_l4_wkup__gpio1,
1691 };
1692
1693 static struct omap_hwmod omap2430_gpio1_hwmod = {
1694         .name           = "gpio1",
1695         .mpu_irqs       = omap243x_gpio1_irqs,
1696         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio1_irqs),
1697         .main_clk       = "gpios_fck",
1698         .prcm           = {
1699                 .omap2 = {
1700                         .prcm_reg_id = 1,
1701                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1702                         .module_offs = WKUP_MOD,
1703                         .idlest_reg_id = 1,
1704                         .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1705                 },
1706         },
1707         .slaves         = omap2430_gpio1_slaves,
1708         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
1709         .class          = &omap243x_gpio_hwmod_class,
1710         .dev_attr       = &gpio_dev_attr,
1711         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1712 };
1713
1714 /* gpio2 */
1715 static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
1716         { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1717 };
1718
1719 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1720         &omap2430_l4_wkup__gpio2,
1721 };
1722
1723 static struct omap_hwmod omap2430_gpio2_hwmod = {
1724         .name           = "gpio2",
1725         .mpu_irqs       = omap243x_gpio2_irqs,
1726         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio2_irqs),
1727         .main_clk       = "gpios_fck",
1728         .prcm           = {
1729                 .omap2 = {
1730                         .prcm_reg_id = 1,
1731                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1732                         .module_offs = WKUP_MOD,
1733                         .idlest_reg_id = 1,
1734                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1735                 },
1736         },
1737         .slaves         = omap2430_gpio2_slaves,
1738         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
1739         .class          = &omap243x_gpio_hwmod_class,
1740         .dev_attr       = &gpio_dev_attr,
1741         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1742 };
1743
1744 /* gpio3 */
1745 static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
1746         { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1747 };
1748
1749 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1750         &omap2430_l4_wkup__gpio3,
1751 };
1752
1753 static struct omap_hwmod omap2430_gpio3_hwmod = {
1754         .name           = "gpio3",
1755         .mpu_irqs       = omap243x_gpio3_irqs,
1756         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio3_irqs),
1757         .main_clk       = "gpios_fck",
1758         .prcm           = {
1759                 .omap2 = {
1760                         .prcm_reg_id = 1,
1761                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1762                         .module_offs = WKUP_MOD,
1763                         .idlest_reg_id = 1,
1764                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1765                 },
1766         },
1767         .slaves         = omap2430_gpio3_slaves,
1768         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
1769         .class          = &omap243x_gpio_hwmod_class,
1770         .dev_attr       = &gpio_dev_attr,
1771         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1772 };
1773
1774 /* gpio4 */
1775 static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
1776         { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1777 };
1778
1779 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1780         &omap2430_l4_wkup__gpio4,
1781 };
1782
1783 static struct omap_hwmod omap2430_gpio4_hwmod = {
1784         .name           = "gpio4",
1785         .mpu_irqs       = omap243x_gpio4_irqs,
1786         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio4_irqs),
1787         .main_clk       = "gpios_fck",
1788         .prcm           = {
1789                 .omap2 = {
1790                         .prcm_reg_id = 1,
1791                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1792                         .module_offs = WKUP_MOD,
1793                         .idlest_reg_id = 1,
1794                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1795                 },
1796         },
1797         .slaves         = omap2430_gpio4_slaves,
1798         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
1799         .class          = &omap243x_gpio_hwmod_class,
1800         .dev_attr       = &gpio_dev_attr,
1801         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1802 };
1803
1804 /* gpio5 */
1805 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1806         { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1807 };
1808
1809 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1810         &omap2430_l4_core__gpio5,
1811 };
1812
1813 static struct omap_hwmod omap2430_gpio5_hwmod = {
1814         .name           = "gpio5",
1815         .mpu_irqs       = omap243x_gpio5_irqs,
1816         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio5_irqs),
1817         .main_clk       = "gpio5_fck",
1818         .prcm           = {
1819                 .omap2 = {
1820                         .prcm_reg_id = 2,
1821                         .module_bit = OMAP2430_EN_GPIO5_SHIFT,
1822                         .module_offs = CORE_MOD,
1823                         .idlest_reg_id = 2,
1824                         .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1825                 },
1826         },
1827         .slaves         = omap2430_gpio5_slaves,
1828         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
1829         .class          = &omap243x_gpio_hwmod_class,
1830         .dev_attr       = &gpio_dev_attr,
1831         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1832 };
1833
1834 /* dma_system */
1835 static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
1836         .rev_offs       = 0x0000,
1837         .sysc_offs      = 0x002c,
1838         .syss_offs      = 0x0028,
1839         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1840                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1841                            SYSC_HAS_AUTOIDLE),
1842         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1843         .sysc_fields    = &omap_hwmod_sysc_type1,
1844 };
1845
1846 static struct omap_hwmod_class omap2430_dma_hwmod_class = {
1847         .name = "dma",
1848         .sysc = &omap2430_dma_sysc,
1849 };
1850
1851 /* dma attributes */
1852 static struct omap_dma_dev_attr dma_dev_attr = {
1853         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1854                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1855         .lch_count = 32,
1856 };
1857
1858 static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
1859         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1860         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1861         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1862         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1863 };
1864
1865 static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
1866         {
1867                 .pa_start       = 0x48056000,
1868                 .pa_end         = 0x4a0560ff,
1869                 .flags          = ADDR_TYPE_RT
1870         },
1871 };
1872
1873 /* dma_system -> L3 */
1874 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1875         .master         = &omap2430_dma_system_hwmod,
1876         .slave          = &omap2430_l3_main_hwmod,
1877         .clk            = "core_l3_ck",
1878         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1879 };
1880
1881 /* dma_system master ports */
1882 static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1883         &omap2430_dma_system__l3,
1884 };
1885
1886 /* l4_core -> dma_system */
1887 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1888         .master         = &omap2430_l4_core_hwmod,
1889         .slave          = &omap2430_dma_system_hwmod,
1890         .clk            = "sdma_ick",
1891         .addr           = omap2430_dma_system_addrs,
1892         .addr_cnt       = ARRAY_SIZE(omap2430_dma_system_addrs),
1893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1894 };
1895
1896 /* dma_system slave ports */
1897 static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1898         &omap2430_l4_core__dma_system,
1899 };
1900
1901 static struct omap_hwmod omap2430_dma_system_hwmod = {
1902         .name           = "dma",
1903         .class          = &omap2430_dma_hwmod_class,
1904         .mpu_irqs       = omap2430_dma_system_irqs,
1905         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dma_system_irqs),
1906         .main_clk       = "core_l3_ck",
1907         .slaves         = omap2430_dma_system_slaves,
1908         .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
1909         .masters        = omap2430_dma_system_masters,
1910         .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
1911         .dev_attr       = &dma_dev_attr,
1912         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1913         .flags          = HWMOD_NO_IDLEST,
1914 };
1915
1916 /*
1917  * 'mcspi' class
1918  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1919  * bus
1920  */
1921
1922 static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
1923         .rev_offs       = 0x0000,
1924         .sysc_offs      = 0x0010,
1925         .syss_offs      = 0x0014,
1926         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1927                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1928                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1929         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1930         .sysc_fields    = &omap_hwmod_sysc_type1,
1931 };
1932
1933 static struct omap_hwmod_class omap2430_mcspi_class = {
1934         .name = "mcspi",
1935         .sysc = &omap2430_mcspi_sysc,
1936         .rev = OMAP2_MCSPI_REV,
1937 };
1938
1939 /* mcspi1 */
1940 static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
1941         { .irq = 65 },
1942 };
1943
1944 static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
1945         { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
1946         { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
1947         { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
1948         { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
1949         { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
1950         { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
1951         { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
1952         { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
1953 };
1954
1955 static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
1956         &omap2430_l4_core__mcspi1,
1957 };
1958
1959 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1960         .num_chipselect = 4,
1961 };
1962
1963 static struct omap_hwmod omap2430_mcspi1_hwmod = {
1964         .name           = "mcspi1_hwmod",
1965         .mpu_irqs       = omap2430_mcspi1_mpu_irqs,
1966         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
1967         .sdma_reqs      = omap2430_mcspi1_sdma_reqs,
1968         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
1969         .main_clk       = "mcspi1_fck",
1970         .prcm           = {
1971                 .omap2 = {
1972                         .module_offs = CORE_MOD,
1973                         .prcm_reg_id = 1,
1974                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1975                         .idlest_reg_id = 1,
1976                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1977                 },
1978         },
1979         .slaves         = omap2430_mcspi1_slaves,
1980         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
1981         .class          = &omap2430_mcspi_class,
1982         .dev_attr       = &omap_mcspi1_dev_attr,
1983         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1984 };
1985
1986 /* mcspi2 */
1987 static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
1988         { .irq = 66 },
1989 };
1990
1991 static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
1992         { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
1993         { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
1994         { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
1995         { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
1996 };
1997
1998 static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
1999         &omap2430_l4_core__mcspi2,
2000 };
2001
2002 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2003         .num_chipselect = 2,
2004 };
2005
2006 static struct omap_hwmod omap2430_mcspi2_hwmod = {
2007         .name           = "mcspi2_hwmod",
2008         .mpu_irqs       = omap2430_mcspi2_mpu_irqs,
2009         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
2010         .sdma_reqs      = omap2430_mcspi2_sdma_reqs,
2011         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
2012         .main_clk       = "mcspi2_fck",
2013         .prcm           = {
2014                 .omap2 = {
2015                         .module_offs = CORE_MOD,
2016                         .prcm_reg_id = 1,
2017                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
2018                         .idlest_reg_id = 1,
2019                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
2020                 },
2021         },
2022         .slaves         = omap2430_mcspi2_slaves,
2023         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
2024         .class          = &omap2430_mcspi_class,
2025         .dev_attr       = &omap_mcspi2_dev_attr,
2026         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2027 };
2028
2029 /* mcspi3 */
2030 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
2031         { .irq = 91 },
2032 };
2033
2034 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
2035         { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
2036         { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
2037         { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
2038         { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
2039 };
2040
2041 static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
2042         &omap2430_l4_core__mcspi3,
2043 };
2044
2045 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2046         .num_chipselect = 2,
2047 };
2048
2049 static struct omap_hwmod omap2430_mcspi3_hwmod = {
2050         .name           = "mcspi3_hwmod",
2051         .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
2052         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
2053         .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
2054         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
2055         .main_clk       = "mcspi3_fck",
2056         .prcm           = {
2057                 .omap2 = {
2058                         .module_offs = CORE_MOD,
2059                         .prcm_reg_id = 2,
2060                         .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
2061                         .idlest_reg_id = 2,
2062                         .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
2063                 },
2064         },
2065         .slaves         = omap2430_mcspi3_slaves,
2066         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
2067         .class          = &omap2430_mcspi_class,
2068         .dev_attr       = &omap_mcspi3_dev_attr,
2069         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2070 };
2071
2072 /*
2073  * usbhsotg
2074  */
2075 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
2076         .rev_offs       = 0x0400,
2077         .sysc_offs      = 0x0404,
2078         .syss_offs      = 0x0408,
2079         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2080                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2081                           SYSC_HAS_AUTOIDLE),
2082         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2083                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2084         .sysc_fields    = &omap_hwmod_sysc_type1,
2085 };
2086
2087 static struct omap_hwmod_class usbotg_class = {
2088         .name = "usbotg",
2089         .sysc = &omap2430_usbhsotg_sysc,
2090 };
2091
2092 /* usb_otg_hs */
2093 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
2094
2095         { .name = "mc", .irq = 92 },
2096         { .name = "dma", .irq = 93 },
2097 };
2098
2099 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
2100         .name           = "usb_otg_hs",
2101         .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
2102         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
2103         .main_clk       = "usbhs_ick",
2104         .prcm           = {
2105                 .omap2 = {
2106                         .prcm_reg_id = 1,
2107                         .module_bit = OMAP2430_EN_USBHS_MASK,
2108                         .module_offs = CORE_MOD,
2109                         .idlest_reg_id = 1,
2110                         .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
2111                 },
2112         },
2113         .masters        = omap2430_usbhsotg_masters,
2114         .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
2115         .slaves         = omap2430_usbhsotg_slaves,
2116         .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
2117         .class          = &usbotg_class,
2118         /*
2119          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
2120          * broken when autoidle is enabled
2121          * workaround is to disable the autoidle bit at module level.
2122          */
2123         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2124                                 | HWMOD_SWSUP_MSTANDBY,
2125         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
2126 };
2127
2128
2129
2130 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
2131         &omap2430_l3_main_hwmod,
2132         &omap2430_l4_core_hwmod,
2133         &omap2430_l4_wkup_hwmod,
2134         &omap2430_mpu_hwmod,
2135         &omap2430_iva_hwmod,
2136
2137         &omap2430_timer1_hwmod,
2138         &omap2430_timer2_hwmod,
2139         &omap2430_timer3_hwmod,
2140         &omap2430_timer4_hwmod,
2141         &omap2430_timer5_hwmod,
2142         &omap2430_timer6_hwmod,
2143         &omap2430_timer7_hwmod,
2144         &omap2430_timer8_hwmod,
2145         &omap2430_timer9_hwmod,
2146         &omap2430_timer10_hwmod,
2147         &omap2430_timer11_hwmod,
2148         &omap2430_timer12_hwmod,
2149
2150         &omap2430_wd_timer2_hwmod,
2151         &omap2430_uart1_hwmod,
2152         &omap2430_uart2_hwmod,
2153         &omap2430_uart3_hwmod,
2154         /* dss class */
2155         &omap2430_dss_core_hwmod,
2156         &omap2430_dss_dispc_hwmod,
2157         &omap2430_dss_rfbi_hwmod,
2158         &omap2430_dss_venc_hwmod,
2159         /* i2c class */
2160         &omap2430_i2c1_hwmod,
2161         &omap2430_i2c2_hwmod,
2162
2163         /* gpio class */
2164         &omap2430_gpio1_hwmod,
2165         &omap2430_gpio2_hwmod,
2166         &omap2430_gpio3_hwmod,
2167         &omap2430_gpio4_hwmod,
2168         &omap2430_gpio5_hwmod,
2169
2170         /* dma_system class*/
2171         &omap2430_dma_system_hwmod,
2172
2173         /* mcspi class */
2174         &omap2430_mcspi1_hwmod,
2175         &omap2430_mcspi2_hwmod,
2176         &omap2430_mcspi3_hwmod,
2177
2178         /* usbotg class*/
2179         &omap2430_usbhsotg_hwmod,
2180
2181         NULL,
2182 };
2183
2184 int __init omap2430_hwmod_init(void)
2185 {
2186         return omap_hwmod_register(omap2430_hwmods);
2187 }