2 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
4 * Copyright (C) 2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <plat/omap_hwmod.h>
12 #include <plat/serial.h>
13 #include <linux/platform_data/gpio-omap.h>
15 #include <plat/dmtimer.h>
16 #include <linux/platform_data/spi-omap2-mcspi.h>
18 #include "omap_hwmod_common_data.h"
19 #include "cm-regbits-24xx.h"
20 #include "prm-regbits-24xx.h"
23 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
24 { .irq = 48 + OMAP_INTC_START, },
28 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
29 { .name = "dispc", .dma_req = 5 },
38 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
42 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
43 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
44 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
45 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
46 .sysc_fields = &omap_hwmod_sysc_type1,
49 struct omap_hwmod_class omap2_dispc_hwmod_class = {
51 .sysc = &omap2_dispc_sysc,
54 /* OMAP2xxx Timer Common */
55 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
59 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
60 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
62 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
63 .sysc_fields = &omap_hwmod_sysc_type1,
66 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
68 .sysc = &omap2xxx_timer_sysc,
73 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
77 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
81 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
82 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
83 .sysc_fields = &omap_hwmod_sysc_type1,
86 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
88 .sysc = &omap2xxx_wd_timer_sysc,
89 .pre_shutdown = &omap2_wd_timer_disable,
90 .reset = &omap2_wd_timer_reset,
95 * general purpose io module
97 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
101 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
102 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
103 SYSS_HAS_RESET_STATUS),
104 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
105 .sysc_fields = &omap_hwmod_sysc_type1,
108 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
110 .sysc = &omap2xxx_gpio_sysc,
115 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
119 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
120 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
121 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
122 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
123 .sysc_fields = &omap_hwmod_sysc_type1,
126 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
128 .sysc = &omap2xxx_dma_sysc,
133 * mailbox module allowing communication between the on-chip processors
134 * using a queued mailbox-interrupt mechanism.
137 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
141 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
142 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
143 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
144 .sysc_fields = &omap_hwmod_sysc_type1,
147 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
149 .sysc = &omap2xxx_mailbox_sysc,
154 * multichannel serial port interface (mcspi) / master/slave synchronous serial
158 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
162 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
163 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
164 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
165 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
166 .sysc_fields = &omap_hwmod_sysc_type1,
169 struct omap_hwmod_class omap2xxx_mcspi_class = {
171 .sysc = &omap2xxx_mcspi_sysc,
172 .rev = OMAP2_MCSPI_REV,
177 * general purpose memory controller
180 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
184 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
185 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
186 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
187 .sysc_fields = &omap_hwmod_sysc_type1,
190 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
192 .sysc = &omap2xxx_gpmc_sysc,
200 struct omap_hwmod omap2xxx_l3_main_hwmod = {
202 .class = &l3_hwmod_class,
203 .flags = HWMOD_NO_IDLEST,
207 struct omap_hwmod omap2xxx_l4_core_hwmod = {
209 .class = &l4_hwmod_class,
210 .flags = HWMOD_NO_IDLEST,
214 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
216 .class = &l4_hwmod_class,
217 .flags = HWMOD_NO_IDLEST,
221 static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
222 { .name = "pmu", .irq = 3 },
226 struct omap_hwmod omap2xxx_mpu_hwmod = {
228 .mpu_irqs = omap2xxx_mpu_irqs,
229 .class = &mpu_hwmod_class,
230 .main_clk = "mpu_ck",
234 struct omap_hwmod omap2xxx_iva_hwmod = {
236 .class = &iva_hwmod_class,
239 /* always-on timers dev attribute */
240 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
241 .timer_capability = OMAP_TIMER_ALWON,
244 /* pwm timers dev attribute */
245 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
246 .timer_capability = OMAP_TIMER_HAS_PWM,
249 /* timers with DSP interrupt dev attribute */
250 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
251 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
256 struct omap_hwmod omap2xxx_timer1_hwmod = {
258 .mpu_irqs = omap2_timer1_mpu_irqs,
259 .main_clk = "gpt1_fck",
263 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
264 .module_offs = WKUP_MOD,
266 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
269 .dev_attr = &capability_alwon_dev_attr,
270 .class = &omap2xxx_timer_hwmod_class,
275 struct omap_hwmod omap2xxx_timer2_hwmod = {
277 .mpu_irqs = omap2_timer2_mpu_irqs,
278 .main_clk = "gpt2_fck",
282 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
283 .module_offs = CORE_MOD,
285 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
288 .class = &omap2xxx_timer_hwmod_class,
293 struct omap_hwmod omap2xxx_timer3_hwmod = {
295 .mpu_irqs = omap2_timer3_mpu_irqs,
296 .main_clk = "gpt3_fck",
300 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
301 .module_offs = CORE_MOD,
303 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
306 .class = &omap2xxx_timer_hwmod_class,
311 struct omap_hwmod omap2xxx_timer4_hwmod = {
313 .mpu_irqs = omap2_timer4_mpu_irqs,
314 .main_clk = "gpt4_fck",
318 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
319 .module_offs = CORE_MOD,
321 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
324 .class = &omap2xxx_timer_hwmod_class,
329 struct omap_hwmod omap2xxx_timer5_hwmod = {
331 .mpu_irqs = omap2_timer5_mpu_irqs,
332 .main_clk = "gpt5_fck",
336 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
337 .module_offs = CORE_MOD,
339 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
342 .dev_attr = &capability_dsp_dev_attr,
343 .class = &omap2xxx_timer_hwmod_class,
348 struct omap_hwmod omap2xxx_timer6_hwmod = {
350 .mpu_irqs = omap2_timer6_mpu_irqs,
351 .main_clk = "gpt6_fck",
355 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
356 .module_offs = CORE_MOD,
358 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
361 .dev_attr = &capability_dsp_dev_attr,
362 .class = &omap2xxx_timer_hwmod_class,
367 struct omap_hwmod omap2xxx_timer7_hwmod = {
369 .mpu_irqs = omap2_timer7_mpu_irqs,
370 .main_clk = "gpt7_fck",
374 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
375 .module_offs = CORE_MOD,
377 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
380 .dev_attr = &capability_dsp_dev_attr,
381 .class = &omap2xxx_timer_hwmod_class,
386 struct omap_hwmod omap2xxx_timer8_hwmod = {
388 .mpu_irqs = omap2_timer8_mpu_irqs,
389 .main_clk = "gpt8_fck",
393 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
394 .module_offs = CORE_MOD,
396 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
399 .dev_attr = &capability_dsp_dev_attr,
400 .class = &omap2xxx_timer_hwmod_class,
405 struct omap_hwmod omap2xxx_timer9_hwmod = {
407 .mpu_irqs = omap2_timer9_mpu_irqs,
408 .main_clk = "gpt9_fck",
412 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
413 .module_offs = CORE_MOD,
415 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
418 .dev_attr = &capability_pwm_dev_attr,
419 .class = &omap2xxx_timer_hwmod_class,
424 struct omap_hwmod omap2xxx_timer10_hwmod = {
426 .mpu_irqs = omap2_timer10_mpu_irqs,
427 .main_clk = "gpt10_fck",
431 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
432 .module_offs = CORE_MOD,
434 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
437 .dev_attr = &capability_pwm_dev_attr,
438 .class = &omap2xxx_timer_hwmod_class,
443 struct omap_hwmod omap2xxx_timer11_hwmod = {
445 .mpu_irqs = omap2_timer11_mpu_irqs,
446 .main_clk = "gpt11_fck",
450 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
451 .module_offs = CORE_MOD,
453 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
456 .dev_attr = &capability_pwm_dev_attr,
457 .class = &omap2xxx_timer_hwmod_class,
462 struct omap_hwmod omap2xxx_timer12_hwmod = {
464 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
465 .main_clk = "gpt12_fck",
469 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
470 .module_offs = CORE_MOD,
472 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
475 .dev_attr = &capability_pwm_dev_attr,
476 .class = &omap2xxx_timer_hwmod_class,
480 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
482 .class = &omap2xxx_wd_timer_hwmod_class,
483 .main_clk = "mpu_wdt_fck",
487 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
488 .module_offs = WKUP_MOD,
490 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
497 struct omap_hwmod omap2xxx_uart1_hwmod = {
499 .mpu_irqs = omap2_uart1_mpu_irqs,
500 .sdma_reqs = omap2_uart1_sdma_reqs,
501 .main_clk = "uart1_fck",
504 .module_offs = CORE_MOD,
506 .module_bit = OMAP24XX_EN_UART1_SHIFT,
508 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
511 .class = &omap2_uart_class,
516 struct omap_hwmod omap2xxx_uart2_hwmod = {
518 .mpu_irqs = omap2_uart2_mpu_irqs,
519 .sdma_reqs = omap2_uart2_sdma_reqs,
520 .main_clk = "uart2_fck",
523 .module_offs = CORE_MOD,
525 .module_bit = OMAP24XX_EN_UART2_SHIFT,
527 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
530 .class = &omap2_uart_class,
535 struct omap_hwmod omap2xxx_uart3_hwmod = {
537 .mpu_irqs = omap2_uart3_mpu_irqs,
538 .sdma_reqs = omap2_uart3_sdma_reqs,
539 .main_clk = "uart3_fck",
542 .module_offs = CORE_MOD,
544 .module_bit = OMAP24XX_EN_UART3_SHIFT,
546 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
549 .class = &omap2_uart_class,
554 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
556 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
557 * driver does not use these clocks.
559 { .role = "tv_clk", .clk = "dss_54m_fck" },
560 { .role = "sys_clk", .clk = "dss2_fck" },
563 struct omap_hwmod omap2xxx_dss_core_hwmod = {
565 .class = &omap2_dss_hwmod_class,
566 .main_clk = "dss1_fck", /* instead of dss_fck */
567 .sdma_reqs = omap2xxx_dss_sdma_chs,
571 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
572 .module_offs = CORE_MOD,
574 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
577 .opt_clks = dss_opt_clks,
578 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
579 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
582 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
584 .class = &omap2_dispc_hwmod_class,
585 .mpu_irqs = omap2_dispc_irqs,
586 .main_clk = "dss1_fck",
590 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
591 .module_offs = CORE_MOD,
593 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
596 .flags = HWMOD_NO_IDLEST,
597 .dev_attr = &omap2_3_dss_dispc_dev_attr
600 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
601 { .role = "ick", .clk = "dss_ick" },
604 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
606 .class = &omap2_rfbi_hwmod_class,
607 .main_clk = "dss1_fck",
611 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
612 .module_offs = CORE_MOD,
615 .opt_clks = dss_rfbi_opt_clks,
616 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
617 .flags = HWMOD_NO_IDLEST,
620 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
622 .class = &omap2_venc_hwmod_class,
623 .main_clk = "dss_54m_fck",
627 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
628 .module_offs = CORE_MOD,
631 .flags = HWMOD_NO_IDLEST,
635 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
641 struct omap_hwmod omap2xxx_gpio1_hwmod = {
643 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
644 .mpu_irqs = omap2_gpio1_irqs,
645 .main_clk = "gpios_fck",
649 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
650 .module_offs = WKUP_MOD,
652 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
655 .class = &omap2xxx_gpio_hwmod_class,
656 .dev_attr = &omap2xxx_gpio_dev_attr,
660 struct omap_hwmod omap2xxx_gpio2_hwmod = {
662 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
663 .mpu_irqs = omap2_gpio2_irqs,
664 .main_clk = "gpios_fck",
668 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
669 .module_offs = WKUP_MOD,
671 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
674 .class = &omap2xxx_gpio_hwmod_class,
675 .dev_attr = &omap2xxx_gpio_dev_attr,
679 struct omap_hwmod omap2xxx_gpio3_hwmod = {
681 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
682 .mpu_irqs = omap2_gpio3_irqs,
683 .main_clk = "gpios_fck",
687 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
688 .module_offs = WKUP_MOD,
690 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
693 .class = &omap2xxx_gpio_hwmod_class,
694 .dev_attr = &omap2xxx_gpio_dev_attr,
698 struct omap_hwmod omap2xxx_gpio4_hwmod = {
700 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
701 .mpu_irqs = omap2_gpio4_irqs,
702 .main_clk = "gpios_fck",
706 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
707 .module_offs = WKUP_MOD,
709 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
712 .class = &omap2xxx_gpio_hwmod_class,
713 .dev_attr = &omap2xxx_gpio_dev_attr,
717 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
721 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
723 .mpu_irqs = omap2_mcspi1_mpu_irqs,
724 .sdma_reqs = omap2_mcspi1_sdma_reqs,
725 .main_clk = "mcspi1_fck",
728 .module_offs = CORE_MOD,
730 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
732 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
735 .class = &omap2xxx_mcspi_class,
736 .dev_attr = &omap_mcspi1_dev_attr,
740 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
744 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
746 .mpu_irqs = omap2_mcspi2_mpu_irqs,
747 .sdma_reqs = omap2_mcspi2_sdma_reqs,
748 .main_clk = "mcspi2_fck",
751 .module_offs = CORE_MOD,
753 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
755 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
758 .class = &omap2xxx_mcspi_class,
759 .dev_attr = &omap_mcspi2_dev_attr,
762 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
766 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
767 .name = "counter_32k",
768 .main_clk = "func_32k_ck",
771 .module_offs = WKUP_MOD,
773 .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
775 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
778 .class = &omap2xxx_counter_hwmod_class,
782 static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
787 struct omap_hwmod omap2xxx_gpmc_hwmod = {
789 .class = &omap2xxx_gpmc_hwmod_class,
790 .mpu_irqs = omap2xxx_gpmc_irqs,
791 .main_clk = "gpmc_fck",
793 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
794 * block. It is not being added due to any known bugs with
795 * resetting the GPMC IP block, but rather because any timings
796 * set by the bootloader are not being correctly programmed by
797 * the kernel from the board file or DT data.
798 * HWMOD_INIT_NO_RESET should be removed ASAP.
800 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
805 .module_bit = OMAP24XX_EN_GPMC_MASK,
806 .module_offs = CORE_MOD,
813 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
817 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
818 SYSS_HAS_RESET_STATUS),
819 .sysc_fields = &omap_hwmod_sysc_type1,
822 static struct omap_hwmod_class omap2_rng_hwmod_class = {
824 .sysc = &omap2_rng_sysc,
827 static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
832 struct omap_hwmod omap2xxx_rng_hwmod = {
834 .mpu_irqs = omap2_rng_mpu_irqs,
838 .module_offs = CORE_MOD,
840 .module_bit = OMAP24XX_EN_RNG_SHIFT,
842 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
846 * XXX The first read from the SYSSTATUS register of the RNG
847 * after the SYSCONFIG SOFTRESET bit is set triggers an
848 * imprecise external abort. It's unclear why this happens.
849 * Until this is analyzed, skip the IP block reset.
851 .flags = HWMOD_INIT_NO_RESET,
852 .class = &omap2_rng_hwmod_class,