2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/i2c-omap.h>
19 #include "omap_hwmod.h"
20 #include <linux/platform_data/gpio-omap.h>
21 #include <linux/platform_data/spi-omap2-mcspi.h>
23 #include "omap_hwmod_common_data.h"
28 #include "prm-regbits-33xx.h"
32 #include "omap_hwmod_33xx_43xx_common_data.h"
42 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
46 static struct omap_hwmod_class am33xx_emif_hwmod_class = {
48 .sysc = &am33xx_emif_sysc,
52 static struct omap_hwmod am33xx_emif_hwmod = {
54 .class = &am33xx_emif_hwmod_class,
55 .clkdm_name = "l3_clkdm",
56 .flags = HWMOD_INIT_NO_IDLE,
57 .main_clk = "dpll_ddr_m2_div2_ck",
60 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
61 .modulemode = MODULEMODE_SWCTRL,
67 static struct omap_hwmod am33xx_l4_hs_hwmod = {
69 .class = &am33xx_l4_hwmod_class,
70 .clkdm_name = "l4hs_clkdm",
71 .flags = HWMOD_INIT_NO_IDLE,
72 .main_clk = "l4hs_gclk",
75 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
76 .modulemode = MODULEMODE_SWCTRL,
81 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
82 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
86 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
88 .class = &am33xx_wkup_m3_hwmod_class,
89 .clkdm_name = "l4_wkup_aon_clkdm",
90 /* Keep hardreset asserted */
91 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
92 .main_clk = "dpll_core_m4_div2_ck",
95 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
96 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
97 .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
98 .modulemode = MODULEMODE_SWCTRL,
101 .rst_lines = am33xx_wkup_m3_resets,
102 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
107 * TouchScreen Controller (Anolog-To-Digital Converter)
109 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
112 .sysc_flags = SYSC_HAS_SIDLEMODE,
113 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
115 .sysc_fields = &omap_hwmod_sysc_type2,
118 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
120 .sysc = &am33xx_adc_tsc_sysc,
123 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
125 .class = &am33xx_adc_tsc_hwmod_class,
126 .clkdm_name = "l4_wkup_clkdm",
127 .main_clk = "adc_tsc_fck",
130 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
131 .modulemode = MODULEMODE_SWCTRL,
137 * Modules omap_hwmod structures
139 * The following IPs are excluded for the moment because:
140 * - They do not need an explicit SW control using omap_hwmod API.
141 * - They still need to be validated with the driver
142 * properly adapted to omap_hwmod / omap_device
144 * - cEFUSE (doesn't fall under any ocp_if)
152 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
156 static struct omap_hwmod am33xx_cefuse_hwmod = {
158 .class = &am33xx_cefuse_hwmod_class,
159 .clkdm_name = "l4_cefuse_clkdm",
160 .main_clk = "cefuse_fck",
163 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
164 .modulemode = MODULEMODE_SWCTRL,
172 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
176 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
178 .class = &am33xx_clkdiv32k_hwmod_class,
179 .clkdm_name = "clk_24mhz_clkdm",
180 .main_clk = "clkdiv32k_ick",
183 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
184 .modulemode = MODULEMODE_SWCTRL,
190 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
194 static struct omap_hwmod am33xx_ocpwp_hwmod = {
196 .class = &am33xx_ocpwp_hwmod_class,
197 .clkdm_name = "l4ls_clkdm",
198 .main_clk = "l4ls_gclk",
201 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
202 .modulemode = MODULEMODE_SWCTRL,
212 static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
213 { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
214 { .role = "dbg_clka", .clk = "dbg_clka_ck" },
217 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
221 static struct omap_hwmod am33xx_debugss_hwmod = {
223 .class = &am33xx_debugss_hwmod_class,
224 .clkdm_name = "l3_aon_clkdm",
225 .main_clk = "trace_clk_div_ck",
228 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
229 .modulemode = MODULEMODE_SWCTRL,
232 .opt_clks = debugss_opt_clks,
233 .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
236 static struct omap_hwmod am33xx_control_hwmod = {
238 .class = &am33xx_control_hwmod_class,
239 .clkdm_name = "l4_wkup_clkdm",
240 .flags = HWMOD_INIT_NO_IDLE,
241 .main_clk = "dpll_core_m4_div2_ck",
244 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
245 .modulemode = MODULEMODE_SWCTRL,
251 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
252 { .role = "dbclk", .clk = "gpio0_dbclk" },
255 static struct omap_hwmod am33xx_gpio0_hwmod = {
257 .class = &am33xx_gpio_hwmod_class,
258 .clkdm_name = "l4_wkup_clkdm",
259 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
260 .main_clk = "dpll_core_m4_div2_ck",
263 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
264 .modulemode = MODULEMODE_SWCTRL,
267 .opt_clks = gpio0_opt_clks,
268 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
269 .dev_attr = &gpio_dev_attr,
273 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
276 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
277 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
278 .sysc_fields = &omap_hwmod_sysc_type2,
281 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
286 static struct omap_hwmod am33xx_lcdc_hwmod = {
288 .class = &am33xx_lcdc_hwmod_class,
289 .clkdm_name = "lcdc_clkdm",
290 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
291 .main_clk = "lcd_gclk",
294 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
295 .modulemode = MODULEMODE_SWCTRL,
302 * high-speed on-the-go universal serial bus (usb_otg) controller
304 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
307 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
308 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
309 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
310 .sysc_fields = &omap_hwmod_sysc_type2,
313 static struct omap_hwmod_class am33xx_usbotg_class = {
315 .sysc = &am33xx_usbhsotg_sysc,
318 static struct omap_hwmod am33xx_usbss_hwmod = {
319 .name = "usb_otg_hs",
320 .class = &am33xx_usbotg_class,
321 .clkdm_name = "l3s_clkdm",
322 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
323 .main_clk = "usbotg_fck",
326 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
327 .modulemode = MODULEMODE_SWCTRL,
337 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
339 .pa_start = 0x4c000000,
340 .pa_end = 0x4c000fff,
341 .flags = ADDR_TYPE_RT
345 /* l3 main -> emif */
346 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
347 .master = &am33xx_l3_main_hwmod,
348 .slave = &am33xx_emif_hwmod,
349 .clk = "dpll_core_m4_ck",
350 .addr = am33xx_emif_addrs,
351 .user = OCP_USER_MPU | OCP_USER_SDMA,
354 /* l3 main -> l4 hs */
355 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
356 .master = &am33xx_l3_main_hwmod,
357 .slave = &am33xx_l4_hs_hwmod,
359 .user = OCP_USER_MPU | OCP_USER_SDMA,
362 /* wkup m3 -> l4 wkup */
363 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
364 .master = &am33xx_wkup_m3_hwmod,
365 .slave = &am33xx_l4_wkup_hwmod,
366 .clk = "dpll_core_m4_div2_ck",
367 .user = OCP_USER_MPU | OCP_USER_SDMA,
370 /* l4 wkup -> wkup m3 */
371 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
372 .master = &am33xx_l4_wkup_hwmod,
373 .slave = &am33xx_wkup_m3_hwmod,
374 .clk = "dpll_core_m4_div2_ck",
375 .user = OCP_USER_MPU | OCP_USER_SDMA,
378 /* l4 hs -> pru-icss */
379 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
380 .master = &am33xx_l4_hs_hwmod,
381 .slave = &am33xx_pruss_hwmod,
382 .clk = "dpll_core_m4_ck",
383 .user = OCP_USER_MPU | OCP_USER_SDMA,
386 /* l3_main -> debugss */
387 static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
389 .pa_start = 0x4b000000,
390 .pa_end = 0x4b000000 + SZ_16M - 1,
391 .flags = ADDR_TYPE_RT
396 static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
397 .master = &am33xx_l3_main_hwmod,
398 .slave = &am33xx_debugss_hwmod,
399 .clk = "dpll_core_m4_ck",
400 .addr = am33xx_debugss_addrs,
401 .user = OCP_USER_MPU,
404 /* l4 wkup -> smartreflex0 */
405 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
406 .master = &am33xx_l4_wkup_hwmod,
407 .slave = &am33xx_smartreflex0_hwmod,
408 .clk = "dpll_core_m4_div2_ck",
409 .user = OCP_USER_MPU,
412 /* l4 wkup -> smartreflex1 */
413 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
414 .master = &am33xx_l4_wkup_hwmod,
415 .slave = &am33xx_smartreflex1_hwmod,
416 .clk = "dpll_core_m4_div2_ck",
417 .user = OCP_USER_MPU,
420 /* l4 wkup -> control */
421 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
422 .master = &am33xx_l4_wkup_hwmod,
423 .slave = &am33xx_control_hwmod,
424 .clk = "dpll_core_m4_div2_ck",
425 .user = OCP_USER_MPU,
428 /* L4 WKUP -> I2C1 */
429 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
430 .master = &am33xx_l4_wkup_hwmod,
431 .slave = &am33xx_i2c1_hwmod,
432 .clk = "dpll_core_m4_div2_ck",
433 .user = OCP_USER_MPU,
436 /* L4 WKUP -> GPIO1 */
437 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
438 .master = &am33xx_l4_wkup_hwmod,
439 .slave = &am33xx_gpio0_hwmod,
440 .clk = "dpll_core_m4_div2_ck",
441 .user = OCP_USER_MPU | OCP_USER_SDMA,
444 /* L4 WKUP -> ADC_TSC */
445 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
447 .pa_start = 0x44E0D000,
448 .pa_end = 0x44E0D000 + SZ_8K - 1,
449 .flags = ADDR_TYPE_RT
454 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
455 .master = &am33xx_l4_wkup_hwmod,
456 .slave = &am33xx_adc_tsc_hwmod,
457 .clk = "dpll_core_m4_div2_ck",
458 .addr = am33xx_adc_tsc_addrs,
459 .user = OCP_USER_MPU,
462 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
463 .master = &am33xx_l4_hs_hwmod,
464 .slave = &am33xx_cpgmac0_hwmod,
465 .clk = "cpsw_125mhz_gclk",
466 .user = OCP_USER_MPU,
469 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
471 .pa_start = 0x4830E000,
472 .pa_end = 0x4830E000 + SZ_8K - 1,
473 .flags = ADDR_TYPE_RT,
478 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
479 .master = &am33xx_l3_main_hwmod,
480 .slave = &am33xx_lcdc_hwmod,
481 .clk = "dpll_core_m4_ck",
482 .addr = am33xx_lcdc_addr_space,
483 .user = OCP_USER_MPU,
486 /* l4 wkup -> timer1 */
487 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
488 .master = &am33xx_l4_wkup_hwmod,
489 .slave = &am33xx_timer1_hwmod,
490 .clk = "dpll_core_m4_div2_ck",
491 .user = OCP_USER_MPU,
494 /* l4 wkup -> uart1 */
495 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
496 .master = &am33xx_l4_wkup_hwmod,
497 .slave = &am33xx_uart1_hwmod,
498 .clk = "dpll_core_m4_div2_ck",
499 .user = OCP_USER_MPU,
502 /* l4 wkup -> wd_timer1 */
503 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
504 .master = &am33xx_l4_wkup_hwmod,
505 .slave = &am33xx_wd_timer1_hwmod,
506 .clk = "dpll_core_m4_div2_ck",
507 .user = OCP_USER_MPU,
511 /* l3 s -> USBSS interface */
512 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
513 .master = &am33xx_l3_s_hwmod,
514 .slave = &am33xx_usbss_hwmod,
516 .user = OCP_USER_MPU,
517 .flags = OCPIF_SWSUP_IDLE,
521 static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
524 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
525 .idlemodes = SIDLE_FORCE | SIDLE_NO,
526 .sysc_fields = &omap_hwmod_sysc_type1,
529 static struct omap_hwmod_class am33xx_rng_hwmod_class = {
531 .sysc = &am33xx_rng_sysc,
534 static struct omap_hwmod am33xx_rng_hwmod = {
536 .class = &am33xx_rng_hwmod_class,
537 .clkdm_name = "l4ls_clkdm",
538 .flags = HWMOD_SWSUP_SIDLE,
539 .main_clk = "rng_fck",
542 .clkctrl_offs = AM33XX_CM_PER_RNG_CLKCTRL_OFFSET,
543 .modulemode = MODULEMODE_SWCTRL,
548 static struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
549 .master = &am33xx_l4_ls_hwmod,
550 .slave = &am33xx_rng_hwmod,
552 .user = OCP_USER_MPU,
555 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
556 &am33xx_l3_main__emif,
557 &am33xx_mpu__l3_main,
560 &am33xx_l3_s__l4_wkup,
561 &am33xx_l3_main__l4_hs,
562 &am33xx_l3_main__l3_s,
563 &am33xx_l3_main__l3_instr,
564 &am33xx_l3_main__gfx,
565 &am33xx_l3_s__l3_main,
566 &am33xx_pruss__l3_main,
567 &am33xx_wkup_m3__l4_wkup,
568 &am33xx_gfx__l3_main,
569 &am33xx_l3_main__debugss,
570 &am33xx_l4_wkup__wkup_m3,
571 &am33xx_l4_wkup__control,
572 &am33xx_l4_wkup__smartreflex0,
573 &am33xx_l4_wkup__smartreflex1,
574 &am33xx_l4_wkup__uart1,
575 &am33xx_l4_wkup__timer1,
576 &am33xx_l4_wkup__rtc,
577 &am33xx_l4_wkup__i2c1,
578 &am33xx_l4_wkup__gpio0,
579 &am33xx_l4_wkup__adc_tsc,
580 &am33xx_l4_wkup__wd_timer1,
581 &am33xx_l4_hs__pruss,
582 &am33xx_l4_per__dcan0,
583 &am33xx_l4_per__dcan1,
584 &am33xx_l4_per__gpio1,
585 &am33xx_l4_per__gpio2,
586 &am33xx_l4_per__gpio3,
587 &am33xx_l4_per__i2c2,
588 &am33xx_l4_per__i2c3,
589 &am33xx_l4_per__mailbox,
590 &am33xx_l4_ls__mcasp0,
591 &am33xx_l4_ls__mcasp1,
595 &am33xx_l4_ls__timer2,
596 &am33xx_l4_ls__timer3,
597 &am33xx_l4_ls__timer4,
598 &am33xx_l4_ls__timer5,
599 &am33xx_l4_ls__timer6,
600 &am33xx_l4_ls__timer7,
601 &am33xx_l3_main__tpcc,
602 &am33xx_l4_ls__uart2,
603 &am33xx_l4_ls__uart3,
604 &am33xx_l4_ls__uart4,
605 &am33xx_l4_ls__uart5,
606 &am33xx_l4_ls__uart6,
607 &am33xx_l4_ls__spinlock,
609 &am33xx_l4_ls__epwmss0,
610 &am33xx_epwmss0__ecap0,
611 &am33xx_epwmss0__eqep0,
612 &am33xx_epwmss0__ehrpwm0,
613 &am33xx_l4_ls__epwmss1,
614 &am33xx_epwmss1__ecap1,
615 &am33xx_epwmss1__eqep1,
616 &am33xx_epwmss1__ehrpwm1,
617 &am33xx_l4_ls__epwmss2,
618 &am33xx_epwmss2__ecap2,
619 &am33xx_epwmss2__eqep2,
620 &am33xx_epwmss2__ehrpwm2,
622 &am33xx_l3_main__lcdc,
623 &am33xx_l4_ls__mcspi0,
624 &am33xx_l4_ls__mcspi1,
625 &am33xx_l3_main__tptc0,
626 &am33xx_l3_main__tptc1,
627 &am33xx_l3_main__tptc2,
628 &am33xx_l3_main__ocmc,
630 &am33xx_l4_hs__cpgmac0,
631 &am33xx_cpgmac0__mdio,
632 &am33xx_l3_main__sha0,
633 &am33xx_l3_main__aes0,
638 int __init am33xx_hwmod_init(void)
640 omap_hwmod_am33xx_reg();
642 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);