2 * Copyright (C) 2013 Texas Instruments Incorporated
4 * Hwmod present only in AM43x and those that differ other than register
5 * offsets as compared to AM335x.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_data/gpio-omap.h>
18 #include <linux/platform_data/spi-omap2-mcspi.h>
19 #include "omap_hwmod.h"
20 #include "omap_hwmod_33xx_43xx_common_data.h"
22 #include "omap_hwmod_common_data.h"
26 static struct omap_hwmod am43xx_l4_hs_hwmod = {
28 .class = &am33xx_l4_hwmod_class,
29 .clkdm_name = "l3_clkdm",
30 .flags = HWMOD_INIT_NO_IDLE,
31 .main_clk = "l4hs_gclk",
34 .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
35 .modulemode = MODULEMODE_SWCTRL,
40 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
41 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
44 static struct omap_hwmod am43xx_wkup_m3_hwmod = {
46 .class = &am33xx_wkup_m3_hwmod_class,
47 .clkdm_name = "l4_wkup_aon_clkdm",
48 /* Keep hardreset asserted */
49 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
50 .main_clk = "sys_clkin_ck",
53 .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
54 .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
55 .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
56 .modulemode = MODULEMODE_SWCTRL,
59 .rst_lines = am33xx_wkup_m3_resets,
60 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
63 static struct omap_hwmod am43xx_control_hwmod = {
65 .class = &am33xx_control_hwmod_class,
66 .clkdm_name = "l4_wkup_clkdm",
67 .flags = HWMOD_INIT_NO_IDLE,
68 .main_clk = "sys_clkin_ck",
71 .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
72 .modulemode = MODULEMODE_SWCTRL,
77 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
78 { .role = "dbclk", .clk = "gpio0_dbclk" },
81 static struct omap_hwmod am43xx_gpio0_hwmod = {
83 .class = &am33xx_gpio_hwmod_class,
84 .clkdm_name = "l4_wkup_clkdm",
85 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
86 .main_clk = "sys_clkin_ck",
89 .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
90 .modulemode = MODULEMODE_SWCTRL,
93 .opt_clks = gpio0_opt_clks,
94 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
95 .dev_attr = &gpio_dev_attr,
98 static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
101 .sysc_flags = SYSC_HAS_SIDLEMODE,
102 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
103 .sysc_fields = &omap_hwmod_sysc_type1,
106 static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
108 .sysc = &am43xx_synctimer_sysc,
111 static struct omap_hwmod am43xx_synctimer_hwmod = {
112 .name = "counter_32k",
113 .class = &am43xx_synctimer_hwmod_class,
114 .clkdm_name = "l4_wkup_aon_clkdm",
115 .flags = HWMOD_SWSUP_SIDLE,
116 .main_clk = "synctimer_32kclk",
119 .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
120 .modulemode = MODULEMODE_SWCTRL,
125 static struct omap_hwmod am43xx_timer8_hwmod = {
127 .class = &am33xx_timer_hwmod_class,
128 .clkdm_name = "l4ls_clkdm",
129 .main_clk = "timer8_fck",
132 .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
133 .modulemode = MODULEMODE_SWCTRL,
138 static struct omap_hwmod am43xx_timer9_hwmod = {
140 .class = &am33xx_timer_hwmod_class,
141 .clkdm_name = "l4ls_clkdm",
142 .main_clk = "timer9_fck",
145 .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
146 .modulemode = MODULEMODE_SWCTRL,
151 static struct omap_hwmod am43xx_timer10_hwmod = {
153 .class = &am33xx_timer_hwmod_class,
154 .clkdm_name = "l4ls_clkdm",
155 .main_clk = "timer10_fck",
158 .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
159 .modulemode = MODULEMODE_SWCTRL,
164 static struct omap_hwmod am43xx_timer11_hwmod = {
166 .class = &am33xx_timer_hwmod_class,
167 .clkdm_name = "l4ls_clkdm",
168 .main_clk = "timer11_fck",
171 .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
172 .modulemode = MODULEMODE_SWCTRL,
177 static struct omap_hwmod am43xx_epwmss3_hwmod = {
179 .class = &am33xx_epwmss_hwmod_class,
180 .clkdm_name = "l4ls_clkdm",
181 .main_clk = "l4ls_gclk",
184 .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
185 .modulemode = MODULEMODE_SWCTRL,
190 static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
192 .class = &am33xx_ehrpwm_hwmod_class,
193 .clkdm_name = "l4ls_clkdm",
194 .main_clk = "l4ls_gclk",
197 static struct omap_hwmod am43xx_epwmss4_hwmod = {
199 .class = &am33xx_epwmss_hwmod_class,
200 .clkdm_name = "l4ls_clkdm",
201 .main_clk = "l4ls_gclk",
204 .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
205 .modulemode = MODULEMODE_SWCTRL,
210 static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
212 .class = &am33xx_ehrpwm_hwmod_class,
213 .clkdm_name = "l4ls_clkdm",
214 .main_clk = "l4ls_gclk",
217 static struct omap_hwmod am43xx_epwmss5_hwmod = {
219 .class = &am33xx_epwmss_hwmod_class,
220 .clkdm_name = "l4ls_clkdm",
221 .main_clk = "l4ls_gclk",
224 .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
225 .modulemode = MODULEMODE_SWCTRL,
230 static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
232 .class = &am33xx_ehrpwm_hwmod_class,
233 .clkdm_name = "l4ls_clkdm",
234 .main_clk = "l4ls_gclk",
237 static struct omap_hwmod am43xx_spi2_hwmod = {
239 .class = &am33xx_spi_hwmod_class,
240 .clkdm_name = "l4ls_clkdm",
241 .main_clk = "dpll_per_m2_div4_ck",
244 .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
245 .modulemode = MODULEMODE_SWCTRL,
248 .dev_attr = &mcspi_attrib,
251 static struct omap_hwmod am43xx_spi3_hwmod = {
253 .class = &am33xx_spi_hwmod_class,
254 .clkdm_name = "l4ls_clkdm",
255 .main_clk = "dpll_per_m2_div4_ck",
258 .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
259 .modulemode = MODULEMODE_SWCTRL,
262 .dev_attr = &mcspi_attrib,
265 static struct omap_hwmod am43xx_spi4_hwmod = {
267 .class = &am33xx_spi_hwmod_class,
268 .clkdm_name = "l4ls_clkdm",
269 .main_clk = "dpll_per_m2_div4_ck",
272 .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
273 .modulemode = MODULEMODE_SWCTRL,
276 .dev_attr = &mcspi_attrib,
279 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
280 { .role = "dbclk", .clk = "gpio4_dbclk" },
283 static struct omap_hwmod am43xx_gpio4_hwmod = {
285 .class = &am33xx_gpio_hwmod_class,
286 .clkdm_name = "l4ls_clkdm",
287 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
288 .main_clk = "l4ls_gclk",
291 .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
292 .modulemode = MODULEMODE_SWCTRL,
295 .opt_clks = gpio4_opt_clks,
296 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
297 .dev_attr = &gpio_dev_attr,
300 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
301 { .role = "dbclk", .clk = "gpio5_dbclk" },
304 static struct omap_hwmod am43xx_gpio5_hwmod = {
306 .class = &am33xx_gpio_hwmod_class,
307 .clkdm_name = "l4ls_clkdm",
308 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
309 .main_clk = "l4ls_gclk",
312 .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
313 .modulemode = MODULEMODE_SWCTRL,
316 .opt_clks = gpio5_opt_clks,
317 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
318 .dev_attr = &gpio_dev_attr,
321 static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
325 static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
327 .class = &am43xx_ocp2scp_hwmod_class,
328 .clkdm_name = "l4ls_clkdm",
329 .main_clk = "l4ls_gclk",
332 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
333 .modulemode = MODULEMODE_SWCTRL,
338 static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
340 .class = &am43xx_ocp2scp_hwmod_class,
341 .clkdm_name = "l4ls_clkdm",
342 .main_clk = "l4ls_gclk",
345 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
346 .modulemode = MODULEMODE_SWCTRL,
351 static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
354 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
356 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
357 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
358 MSTANDBY_NO | MSTANDBY_SMART |
359 MSTANDBY_SMART_WKUP),
360 .sysc_fields = &omap_hwmod_sysc_type2,
363 static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
364 .name = "usb_otg_ss",
365 .sysc = &am43xx_usb_otg_ss_sysc,
368 static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
369 .name = "usb_otg_ss0",
370 .class = &am43xx_usb_otg_ss_hwmod_class,
371 .clkdm_name = "l3s_clkdm",
372 .main_clk = "l3s_gclk",
375 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
376 .modulemode = MODULEMODE_SWCTRL,
381 static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
382 .name = "usb_otg_ss1",
383 .class = &am43xx_usb_otg_ss_hwmod_class,
384 .clkdm_name = "l3s_clkdm",
385 .main_clk = "l3s_gclk",
388 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
389 .modulemode = MODULEMODE_SWCTRL,
394 static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
396 .sysc_flags = SYSC_HAS_SIDLEMODE,
397 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
399 .sysc_fields = &omap_hwmod_sysc_type2,
402 static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
404 .sysc = &am43xx_qspi_sysc,
407 static struct omap_hwmod am43xx_qspi_hwmod = {
409 .class = &am43xx_qspi_hwmod_class,
410 .clkdm_name = "l3s_clkdm",
411 .main_clk = "l3s_gclk",
414 .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
415 .modulemode = MODULEMODE_SWCTRL,
422 * TouchScreen Controller (Analog-To-Digital Converter)
424 static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
427 .sysc_flags = SYSC_HAS_SIDLEMODE,
428 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
430 .sysc_fields = &omap_hwmod_sysc_type2,
433 static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
435 .sysc = &am43xx_adc_tsc_sysc,
438 static struct omap_hwmod am43xx_adc_tsc_hwmod = {
440 .class = &am43xx_adc_tsc_hwmod_class,
441 .clkdm_name = "l3s_tsc_clkdm",
442 .main_clk = "adc_tsc_fck",
445 .clkctrl_offs = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
446 .modulemode = MODULEMODE_SWCTRL,
453 static struct omap_hwmod am43xx_dss_core_hwmod = {
455 .class = &omap2_dss_hwmod_class,
456 .clkdm_name = "dss_clkdm",
457 .main_clk = "disp_clk",
460 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
461 .modulemode = MODULEMODE_SWCTRL,
468 struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
470 .has_framedonetv_irq = 0
473 static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
477 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
478 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
479 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
480 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
481 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
482 .sysc_fields = &omap_hwmod_sysc_type1,
485 static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
487 .sysc = &am43xx_dispc_sysc,
490 static struct omap_hwmod am43xx_dss_dispc_hwmod = {
492 .class = &am43xx_dispc_hwmod_class,
493 .clkdm_name = "dss_clkdm",
494 .main_clk = "disp_clk",
497 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
500 .dev_attr = &am43xx_dss_dispc_dev_attr,
501 .parent_hwmod = &am43xx_dss_core_hwmod,
506 static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
508 .class = &omap2_rfbi_hwmod_class,
509 .clkdm_name = "dss_clkdm",
510 .main_clk = "disp_clk",
513 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
516 .parent_hwmod = &am43xx_dss_core_hwmod,
520 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
521 .master = &am33xx_l3_main_hwmod,
522 .slave = &am43xx_l4_hs_hwmod,
524 .user = OCP_USER_MPU | OCP_USER_SDMA,
527 static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
528 .master = &am43xx_wkup_m3_hwmod,
529 .slave = &am33xx_l4_wkup_hwmod,
530 .clk = "sys_clkin_ck",
531 .user = OCP_USER_MPU | OCP_USER_SDMA,
534 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
535 .master = &am33xx_l4_wkup_hwmod,
536 .slave = &am43xx_wkup_m3_hwmod,
537 .clk = "sys_clkin_ck",
538 .user = OCP_USER_MPU | OCP_USER_SDMA,
541 static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
542 .master = &am33xx_l3_main_hwmod,
543 .slave = &am33xx_pruss_hwmod,
544 .clk = "dpll_core_m4_ck",
545 .user = OCP_USER_MPU,
548 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
549 .master = &am33xx_l4_wkup_hwmod,
550 .slave = &am33xx_smartreflex0_hwmod,
551 .clk = "sys_clkin_ck",
552 .user = OCP_USER_MPU,
555 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
556 .master = &am33xx_l4_wkup_hwmod,
557 .slave = &am33xx_smartreflex1_hwmod,
558 .clk = "sys_clkin_ck",
559 .user = OCP_USER_MPU,
562 static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
563 .master = &am33xx_l4_wkup_hwmod,
564 .slave = &am43xx_control_hwmod,
565 .clk = "sys_clkin_ck",
566 .user = OCP_USER_MPU,
569 static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
570 .master = &am33xx_l4_wkup_hwmod,
571 .slave = &am33xx_i2c1_hwmod,
572 .clk = "sys_clkin_ck",
573 .user = OCP_USER_MPU,
576 static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
577 .master = &am33xx_l4_wkup_hwmod,
578 .slave = &am43xx_gpio0_hwmod,
579 .clk = "sys_clkin_ck",
580 .user = OCP_USER_MPU | OCP_USER_SDMA,
583 static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
584 .master = &am33xx_l4_wkup_hwmod,
585 .slave = &am43xx_adc_tsc_hwmod,
586 .clk = "dpll_core_m4_div2_ck",
587 .user = OCP_USER_MPU,
590 static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
591 .master = &am43xx_l4_hs_hwmod,
592 .slave = &am33xx_cpgmac0_hwmod,
593 .clk = "cpsw_125mhz_gclk",
594 .user = OCP_USER_MPU,
597 static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
598 .master = &am33xx_l4_wkup_hwmod,
599 .slave = &am33xx_timer1_hwmod,
600 .clk = "sys_clkin_ck",
601 .user = OCP_USER_MPU,
604 static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
605 .master = &am33xx_l4_wkup_hwmod,
606 .slave = &am33xx_uart1_hwmod,
607 .clk = "sys_clkin_ck",
608 .user = OCP_USER_MPU,
611 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
612 .master = &am33xx_l4_wkup_hwmod,
613 .slave = &am33xx_wd_timer1_hwmod,
614 .clk = "sys_clkin_ck",
615 .user = OCP_USER_MPU,
618 static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
619 .master = &am33xx_l4_wkup_hwmod,
620 .slave = &am43xx_synctimer_hwmod,
621 .clk = "sys_clkin_ck",
622 .user = OCP_USER_MPU,
625 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
626 .master = &am33xx_l4_ls_hwmod,
627 .slave = &am43xx_timer8_hwmod,
629 .user = OCP_USER_MPU,
632 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
633 .master = &am33xx_l4_ls_hwmod,
634 .slave = &am43xx_timer9_hwmod,
636 .user = OCP_USER_MPU,
639 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
640 .master = &am33xx_l4_ls_hwmod,
641 .slave = &am43xx_timer10_hwmod,
643 .user = OCP_USER_MPU,
646 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
647 .master = &am33xx_l4_ls_hwmod,
648 .slave = &am43xx_timer11_hwmod,
650 .user = OCP_USER_MPU,
653 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
654 .master = &am33xx_l4_ls_hwmod,
655 .slave = &am43xx_epwmss3_hwmod,
657 .user = OCP_USER_MPU,
660 static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
661 .master = &am43xx_epwmss3_hwmod,
662 .slave = &am43xx_ehrpwm3_hwmod,
664 .user = OCP_USER_MPU,
667 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
668 .master = &am33xx_l4_ls_hwmod,
669 .slave = &am43xx_epwmss4_hwmod,
671 .user = OCP_USER_MPU,
674 static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
675 .master = &am43xx_epwmss4_hwmod,
676 .slave = &am43xx_ehrpwm4_hwmod,
678 .user = OCP_USER_MPU,
681 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
682 .master = &am33xx_l4_ls_hwmod,
683 .slave = &am43xx_epwmss5_hwmod,
685 .user = OCP_USER_MPU,
688 static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
689 .master = &am43xx_epwmss5_hwmod,
690 .slave = &am43xx_ehrpwm5_hwmod,
692 .user = OCP_USER_MPU,
695 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
696 .master = &am33xx_l4_ls_hwmod,
697 .slave = &am43xx_spi2_hwmod,
699 .user = OCP_USER_MPU,
702 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
703 .master = &am33xx_l4_ls_hwmod,
704 .slave = &am43xx_spi3_hwmod,
706 .user = OCP_USER_MPU,
709 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
710 .master = &am33xx_l4_ls_hwmod,
711 .slave = &am43xx_spi4_hwmod,
713 .user = OCP_USER_MPU,
716 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
717 .master = &am33xx_l4_ls_hwmod,
718 .slave = &am43xx_gpio4_hwmod,
720 .user = OCP_USER_MPU | OCP_USER_SDMA,
723 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
724 .master = &am33xx_l4_ls_hwmod,
725 .slave = &am43xx_gpio5_hwmod,
727 .user = OCP_USER_MPU | OCP_USER_SDMA,
730 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
731 .master = &am33xx_l4_ls_hwmod,
732 .slave = &am43xx_ocp2scp0_hwmod,
734 .user = OCP_USER_MPU,
737 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
738 .master = &am33xx_l4_ls_hwmod,
739 .slave = &am43xx_ocp2scp1_hwmod,
741 .user = OCP_USER_MPU,
744 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
745 .master = &am33xx_l3_s_hwmod,
746 .slave = &am43xx_usb_otg_ss0_hwmod,
748 .user = OCP_USER_MPU | OCP_USER_SDMA,
751 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
752 .master = &am33xx_l3_s_hwmod,
753 .slave = &am43xx_usb_otg_ss1_hwmod,
755 .user = OCP_USER_MPU | OCP_USER_SDMA,
758 static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
759 .master = &am33xx_l3_s_hwmod,
760 .slave = &am43xx_qspi_hwmod,
762 .user = OCP_USER_MPU | OCP_USER_SDMA,
765 static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
766 .master = &am43xx_dss_core_hwmod,
767 .slave = &am33xx_l3_main_hwmod,
769 .user = OCP_USER_MPU | OCP_USER_SDMA,
772 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
773 .master = &am33xx_l4_ls_hwmod,
774 .slave = &am43xx_dss_core_hwmod,
776 .user = OCP_USER_MPU | OCP_USER_SDMA,
779 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
780 .master = &am33xx_l4_ls_hwmod,
781 .slave = &am43xx_dss_dispc_hwmod,
783 .user = OCP_USER_MPU | OCP_USER_SDMA,
786 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
787 .master = &am33xx_l4_ls_hwmod,
788 .slave = &am43xx_dss_rfbi_hwmod,
790 .user = OCP_USER_MPU | OCP_USER_SDMA,
793 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
794 &am33xx_l4_wkup__synctimer,
795 &am43xx_l4_ls__timer8,
796 &am43xx_l4_ls__timer9,
797 &am43xx_l4_ls__timer10,
798 &am43xx_l4_ls__timer11,
799 &am43xx_l4_ls__epwmss3,
800 &am43xx_epwmss3__ehrpwm3,
801 &am43xx_l4_ls__epwmss4,
802 &am43xx_epwmss4__ehrpwm4,
803 &am43xx_l4_ls__epwmss5,
804 &am43xx_epwmss5__ehrpwm5,
805 &am43xx_l4_ls__mcspi2,
806 &am43xx_l4_ls__mcspi3,
807 &am43xx_l4_ls__mcspi4,
808 &am43xx_l4_ls__gpio4,
809 &am43xx_l4_ls__gpio5,
810 &am43xx_l3_main__pruss,
811 &am33xx_mpu__l3_main,
814 &am33xx_l3_s__l4_wkup,
815 &am43xx_l3_main__l4_hs,
816 &am33xx_l3_main__l3_s,
817 &am33xx_l3_main__l3_instr,
818 &am33xx_l3_main__gfx,
819 &am33xx_l3_s__l3_main,
820 &am33xx_pruss__l3_main,
821 &am43xx_wkup_m3__l4_wkup,
822 &am33xx_gfx__l3_main,
823 &am43xx_l4_wkup__wkup_m3,
824 &am43xx_l4_wkup__control,
825 &am43xx_l4_wkup__smartreflex0,
826 &am43xx_l4_wkup__smartreflex1,
827 &am43xx_l4_wkup__uart1,
828 &am43xx_l4_wkup__timer1,
829 &am43xx_l4_wkup__i2c1,
830 &am43xx_l4_wkup__gpio0,
831 &am43xx_l4_wkup__wd_timer1,
832 &am43xx_l4_wkup__adc_tsc,
834 &am33xx_l4_per__dcan0,
835 &am33xx_l4_per__dcan1,
836 &am33xx_l4_per__gpio1,
837 &am33xx_l4_per__gpio2,
838 &am33xx_l4_per__gpio3,
839 &am33xx_l4_per__i2c2,
840 &am33xx_l4_per__i2c3,
841 &am33xx_l4_per__mailbox,
842 &am33xx_l4_ls__mcasp0,
843 &am33xx_l4_ls__mcasp1,
847 &am33xx_l4_ls__timer2,
848 &am33xx_l4_ls__timer3,
849 &am33xx_l4_ls__timer4,
850 &am33xx_l4_ls__timer5,
851 &am33xx_l4_ls__timer6,
852 &am33xx_l4_ls__timer7,
853 &am33xx_l3_main__tpcc,
854 &am33xx_l4_ls__uart2,
855 &am33xx_l4_ls__uart3,
856 &am33xx_l4_ls__uart4,
857 &am33xx_l4_ls__uart5,
858 &am33xx_l4_ls__uart6,
859 &am33xx_l4_ls__spinlock,
861 &am33xx_l4_ls__epwmss0,
862 &am33xx_epwmss0__ecap0,
863 &am33xx_epwmss0__eqep0,
864 &am33xx_epwmss0__ehrpwm0,
865 &am33xx_l4_ls__epwmss1,
866 &am33xx_epwmss1__ecap1,
867 &am33xx_epwmss1__eqep1,
868 &am33xx_epwmss1__ehrpwm1,
869 &am33xx_l4_ls__epwmss2,
870 &am33xx_epwmss2__ecap2,
871 &am33xx_epwmss2__eqep2,
872 &am33xx_epwmss2__ehrpwm2,
874 &am33xx_l4_ls__mcspi0,
875 &am33xx_l4_ls__mcspi1,
876 &am33xx_l3_main__tptc0,
877 &am33xx_l3_main__tptc1,
878 &am33xx_l3_main__tptc2,
879 &am33xx_l3_main__ocmc,
880 &am43xx_l4_hs__cpgmac0,
881 &am33xx_cpgmac0__mdio,
882 &am33xx_l3_main__sha0,
883 &am33xx_l3_main__aes0,
884 &am43xx_l4_ls__ocp2scp0,
885 &am43xx_l4_ls__ocp2scp1,
886 &am43xx_l3_s__usbotgss0,
887 &am43xx_l3_s__usbotgss1,
888 &am43xx_dss__l3_main,
890 &am43xx_l4_ls__dss_dispc,
891 &am43xx_l4_ls__dss_rfbi,
895 int __init am43xx_hwmod_init(void)
897 omap_hwmod_am43xx_reg();
899 return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);