arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/platform_data/omap_ocp2scp.h>
  25 #include <linux/i2c-omap.h>
  26
  27 #include <linux/omap-dma.h>
  28
  29 #include <linux/platform_data/spi-omap2-mcspi.h>
  30 #include <linux/platform_data/asoc-ti-mcbsp.h>
  31 #include <linux/platform_data/iommu-omap.h>
  32 #include <plat/dmtimer.h>
  33
  34 #include "omap_hwmod.h"
  35 #include "omap_hwmod_common_data.h"
  36 #include "cm1_44xx.h"
  37 #include "cm2_44xx.h"
  38 #include "prm44xx.h"
  39 #include "prm-regbits-44xx.h"
  40 #include "i2c.h"
  41 #include "mmc.h"
  42 #include "wd_timer.h"
  43
  44 /* Base offset for all OMAP4 interrupts external to MPUSS */
  45 #define OMAP44XX_IRQ_GIC_START  32
  46
  47 /* Base offset for all OMAP4 dma requests */
  48 #define OMAP44XX_DMA_REQ_START  1
  49
  50 /*
  51  * IP blocks
  52  */
  53
  54 /*
  55  * 'c2c_target_fw' class
  56  * instance(s): c2c_target_fw
  57  */
  58 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  59         .name   = "c2c_target_fw",
  60 };
  61
  62 /* c2c_target_fw */
  63 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  64         .name           = "c2c_target_fw",
  65         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  66         .clkdm_name     = "d2d_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  70                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  71                 },
  72         },
  73 };
  74
  75 /*
  76  * 'dmm' class
  77  * instance(s): dmm
  78  */
  79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  80         .name   = "dmm",
  81 };
  82
  83 /* dmm */
  84 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  85         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  86         { .irq = -1 }
  87 };
  88
  89 static struct omap_hwmod omap44xx_dmm_hwmod = {
  90         .name           = "dmm",
  91         .class          = &omap44xx_dmm_hwmod_class,
  92         .clkdm_name     = "l3_emif_clkdm",
  93         .mpu_irqs       = omap44xx_dmm_irqs,
  94         .prcm = {
  95                 .omap4 = {
  96                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  97                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  98                 },
  99         },
 100 };
 101
 102 /*
 103  * 'emif_fw' class
 104  * instance(s): emif_fw
 105  */
 106 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 107         .name   = "emif_fw",
 108 };
 109
 110 /* emif_fw */
 111 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 112         .name           = "emif_fw",
 113         .class          = &omap44xx_emif_fw_hwmod_class,
 114         .clkdm_name     = "l3_emif_clkdm",
 115         .prcm = {
 116                 .omap4 = {
 117                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 118                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 119                 },
 120         },
 121 };
 122
 123 /*
 124  * 'l3' class
 125  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 126  */
 127 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 128         .name   = "l3",
 129 };
 130
 131 /* l3_instr */
 132 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 133         .name           = "l3_instr",
 134         .class          = &omap44xx_l3_hwmod_class,
 135         .clkdm_name     = "l3_instr_clkdm",
 136         .prcm = {
 137                 .omap4 = {
 138                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 139                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 140                         .modulemode   = MODULEMODE_HWCTRL,
 141                 },
 142         },
 143 };
 144
 145 /* l3_main_1 */
 146 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 147         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 148         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 149         { .irq = -1 }
 150 };
 151
 152 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 153         .name           = "l3_main_1",
 154         .class          = &omap44xx_l3_hwmod_class,
 155         .clkdm_name     = "l3_1_clkdm",
 156         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 157         .prcm = {
 158                 .omap4 = {
 159                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 160                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 161                 },
 162         },
 163 };
 164
 165 /* l3_main_2 */
 166 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 167         .name           = "l3_main_2",
 168         .class          = &omap44xx_l3_hwmod_class,
 169         .clkdm_name     = "l3_2_clkdm",
 170         .prcm = {
 171                 .omap4 = {
 172                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 173                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 174                 },
 175         },
 176 };
 177
 178 /* l3_main_3 */
 179 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 180         .name           = "l3_main_3",
 181         .class          = &omap44xx_l3_hwmod_class,
 182         .clkdm_name     = "l3_instr_clkdm",
 183         .prcm = {
 184                 .omap4 = {
 185                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 186                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 187                         .modulemode   = MODULEMODE_HWCTRL,
 188                 },
 189         },
 190 };
 191
 192 /*
 193  * 'l4' class
 194  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 195  */
 196 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 197         .name   = "l4",
 198 };
 199
 200 /* l4_abe */
 201 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 202         .name           = "l4_abe",
 203         .class          = &omap44xx_l4_hwmod_class,
 204         .clkdm_name     = "abe_clkdm",
 205         .prcm = {
 206                 .omap4 = {
 207                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 208                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 209                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 210                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 211                 },
 212         },
 213 };
 214
 215 /* l4_cfg */
 216 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 217         .name           = "l4_cfg",
 218         .class          = &omap44xx_l4_hwmod_class,
 219         .clkdm_name     = "l4_cfg_clkdm",
 220         .prcm = {
 221                 .omap4 = {
 222                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 223                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 224                 },
 225         },
 226 };
 227
 228 /* l4_per */
 229 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 230         .name           = "l4_per",
 231         .class          = &omap44xx_l4_hwmod_class,
 232         .clkdm_name     = "l4_per_clkdm",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 236                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 237                 },
 238         },
 239 };
 240
 241 /* l4_wkup */
 242 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 243         .name           = "l4_wkup",
 244         .class          = &omap44xx_l4_hwmod_class,
 245         .clkdm_name     = "l4_wkup_clkdm",
 246         .prcm = {
 247                 .omap4 = {
 248                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 249                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 250                 },
 251         },
 252 };
 253
 254 /*
 255  * 'mpu_bus' class
 256  * instance(s): mpu_private
 257  */
 258 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 259         .name   = "mpu_bus",
 260 };
 261
 262 /* mpu_private */
 263 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 264         .name           = "mpu_private",
 265         .class          = &omap44xx_mpu_bus_hwmod_class,
 266         .clkdm_name     = "mpuss_clkdm",
 267         .prcm = {
 268                 .omap4 = {
 269                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 270                 },
 271         },
 272 };
 273
 274 /*
 275  * 'ocp_wp_noc' class
 276  * instance(s): ocp_wp_noc
 277  */
 278 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 279         .name   = "ocp_wp_noc",
 280 };
 281
 282 /* ocp_wp_noc */
 283 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 284         .name           = "ocp_wp_noc",
 285         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 286         .clkdm_name     = "l3_instr_clkdm",
 287         .prcm = {
 288                 .omap4 = {
 289                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 290                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 291                         .modulemode   = MODULEMODE_HWCTRL,
 292                 },
 293         },
 294 };
 295
 296 /*
 297  * Modules omap_hwmod structures
 298  *
 299  * The following IPs are excluded for the moment because:
 300  * - They do not need an explicit SW control using omap_hwmod API.
 301  * - They still need to be validated with the driver
 302  *   properly adapted to omap_hwmod / omap_device
 303  *
 304  * usim
 305  */
 306
 307 /*
 308  * 'aess' class
 309  * audio engine sub system
 310  */
 311
 312 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 313         .rev_offs       = 0x0000,
 314         .sysc_offs      = 0x0010,
 315         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 316         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 317                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 318                            MSTANDBY_SMART_WKUP),
 319         .sysc_fields    = &omap_hwmod_sysc_type2,
 320 };
 321
 322 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 323         .name   = "aess",
 324         .sysc   = &omap44xx_aess_sysc,
 325         .enable_preprogram = omap_hwmod_aess_preprogram,
 326 };
 327
 328 /* aess */
 329 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 330         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 331         { .irq = -1 }
 332 };
 333
 334 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 335         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 340         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 341         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 342         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 343         { .dma_req = -1 }
 344 };
 345
 346 static struct omap_hwmod omap44xx_aess_hwmod = {
 347         .name           = "aess",
 348         .class          = &omap44xx_aess_hwmod_class,
 349         .clkdm_name     = "abe_clkdm",
 350         .mpu_irqs       = omap44xx_aess_irqs,
 351         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 352         .main_clk       = "aess_fclk",
 353         .prcm = {
 354                 .omap4 = {
 355                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 356                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 357                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 358                         .modulemode   = MODULEMODE_SWCTRL,
 359                 },
 360         },
 361 };
 362
 363 /*
 364  * 'c2c' class
 365  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 366  * soc
 367  */
 368
 369 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 370         .name   = "c2c",
 371 };
 372
 373 /* c2c */
 374 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 375         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 376         { .irq = -1 }
 377 };
 378
 379 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 380         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 381         { .dma_req = -1 }
 382 };
 383
 384 static struct omap_hwmod omap44xx_c2c_hwmod = {
 385         .name           = "c2c",
 386         .class          = &omap44xx_c2c_hwmod_class,
 387         .clkdm_name     = "d2d_clkdm",
 388         .mpu_irqs       = omap44xx_c2c_irqs,
 389         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 390         .prcm = {
 391                 .omap4 = {
 392                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 393                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 394                 },
 395         },
 396 };
 397
 398 /*
 399  * 'counter' class
 400  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 401  */
 402
 403 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 404         .rev_offs       = 0x0000,
 405         .sysc_offs      = 0x0004,
 406         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 408         .sysc_fields    = &omap_hwmod_sysc_type1,
 409 };
 410
 411 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 412         .name   = "counter",
 413         .sysc   = &omap44xx_counter_sysc,
 414 };
 415
 416 /* counter_32k */
 417 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 418         .name           = "counter_32k",
 419         .class          = &omap44xx_counter_hwmod_class,
 420         .clkdm_name     = "l4_wkup_clkdm",
 421         .flags          = HWMOD_SWSUP_SIDLE,
 422         .main_clk       = "sys_32k_ck",
 423         .prcm = {
 424                 .omap4 = {
 425                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 426                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 427                 },
 428         },
 429 };
 430
 431 /*
 432  * 'ctrl_module' class
 433  * attila core control module + core pad control module + wkup pad control
 434  * module + attila wkup control module
 435  */
 436
 437 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 438         .rev_offs       = 0x0000,
 439         .sysc_offs      = 0x0010,
 440         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 441         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 442                            SIDLE_SMART_WKUP),
 443         .sysc_fields    = &omap_hwmod_sysc_type2,
 444 };
 445
 446 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 447         .name   = "ctrl_module",
 448         .sysc   = &omap44xx_ctrl_module_sysc,
 449 };
 450
 451 /* ctrl_module_core */
 452 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 453         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 454         { .irq = -1 }
 455 };
 456
 457 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 458         .name           = "ctrl_module_core",
 459         .class          = &omap44xx_ctrl_module_hwmod_class,
 460         .clkdm_name     = "l4_cfg_clkdm",
 461         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 462         .prcm = {
 463                 .omap4 = {
 464                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 465                 },
 466         },
 467 };
 468
 469 /* ctrl_module_pad_core */
 470 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 471         .name           = "ctrl_module_pad_core",
 472         .class          = &omap44xx_ctrl_module_hwmod_class,
 473         .clkdm_name     = "l4_cfg_clkdm",
 474         .prcm = {
 475                 .omap4 = {
 476                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 477                 },
 478         },
 479 };
 480
 481 /* ctrl_module_wkup */
 482 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 483         .name           = "ctrl_module_wkup",
 484         .class          = &omap44xx_ctrl_module_hwmod_class,
 485         .clkdm_name     = "l4_wkup_clkdm",
 486         .prcm = {
 487                 .omap4 = {
 488                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 489                 },
 490         },
 491 };
 492
 493 /* ctrl_module_pad_wkup */
 494 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 495         .name           = "ctrl_module_pad_wkup",
 496         .class          = &omap44xx_ctrl_module_hwmod_class,
 497         .clkdm_name     = "l4_wkup_clkdm",
 498         .prcm = {
 499                 .omap4 = {
 500                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 501                 },
 502         },
 503 };
 504
 505 /*
 506  * 'debugss' class
 507  * debug and emulation sub system
 508  */
 509
 510 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 511         .name   = "debugss",
 512 };
 513
 514 /* debugss */
 515 static struct omap_hwmod omap44xx_debugss_hwmod = {
 516         .name           = "debugss",
 517         .class          = &omap44xx_debugss_hwmod_class,
 518         .clkdm_name     = "emu_sys_clkdm",
 519         .main_clk       = "trace_clk_div_ck",
 520         .prcm = {
 521                 .omap4 = {
 522                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 523                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 524                 },
 525         },
 526 };
 527
 528 /*
 529  * 'dma' class
 530  * dma controller for data exchange between memory to memory (i.e. internal or
 531  * external memory) and gp peripherals to memory or memory to gp peripherals
 532  */
 533
 534 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 535         .rev_offs       = 0x0000,
 536         .sysc_offs      = 0x002c,
 537         .syss_offs      = 0x0028,
 538         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 539                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 540                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 541                            SYSS_HAS_RESET_STATUS),
 542         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 543                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 544         .sysc_fields    = &omap_hwmod_sysc_type1,
 545 };
 546
 547 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 548         .name   = "dma",
 549         .sysc   = &omap44xx_dma_sysc,
 550 };
 551
 552 /* dma dev_attr */
 553 static struct omap_dma_dev_attr dma_dev_attr = {
 554         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 555                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 556         .lch_count      = 32,
 557 };
 558
 559 /* dma_system */
 560 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 561         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 562         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 563         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 564         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 565         { .irq = -1 }
 566 };
 567
 568 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 569         .name           = "dma_system",
 570         .class          = &omap44xx_dma_hwmod_class,
 571         .clkdm_name     = "l3_dma_clkdm",
 572         .mpu_irqs       = omap44xx_dma_system_irqs,
 573         .main_clk       = "l3_div_ck",
 574         .prcm = {
 575                 .omap4 = {
 576                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 577                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 578                 },
 579         },
 580         .dev_attr       = &dma_dev_attr,
 581 };
 582
 583 /*
 584  * 'dmic' class
 585  * digital microphone controller
 586  */
 587
 588 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 589         .rev_offs       = 0x0000,
 590         .sysc_offs      = 0x0010,
 591         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 592                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 593         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 594                            SIDLE_SMART_WKUP),
 595         .sysc_fields    = &omap_hwmod_sysc_type2,
 596 };
 597
 598 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 599         .name   = "dmic",
 600         .sysc   = &omap44xx_dmic_sysc,
 601 };
 602
 603 /* dmic */
 604 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 605         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 606         { .irq = -1 }
 607 };
 608
 609 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 610         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 611         { .dma_req = -1 }
 612 };
 613
 614 static struct omap_hwmod omap44xx_dmic_hwmod = {
 615         .name           = "dmic",
 616         .class          = &omap44xx_dmic_hwmod_class,
 617         .clkdm_name     = "abe_clkdm",
 618         .mpu_irqs       = omap44xx_dmic_irqs,
 619         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 620         .main_clk       = "func_dmic_abe_gfclk",
 621         .prcm = {
 622                 .omap4 = {
 623                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 624                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 625                         .modulemode   = MODULEMODE_SWCTRL,
 626                 },
 627         },
 628 };
 629
 630 /*
 631  * 'dsp' class
 632  * dsp sub-system
 633  */
 634
 635 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 636         .name   = "dsp",
 637 };
 638
 639 /* dsp */
 640 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 641         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 642         { .irq = -1 }
 643 };
 644
 645 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 646         { .name = "dsp", .rst_shift = 0 },
 647 };
 648
 649 static struct omap_hwmod omap44xx_dsp_hwmod = {
 650         .name           = "dsp",
 651         .class          = &omap44xx_dsp_hwmod_class,
 652         .clkdm_name     = "tesla_clkdm",
 653         .mpu_irqs       = omap44xx_dsp_irqs,
 654         .rst_lines      = omap44xx_dsp_resets,
 655         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 656         .main_clk       = "dpll_iva_m4x2_ck",
 657         .prcm = {
 658                 .omap4 = {
 659                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 660                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 661                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 662                         .modulemode   = MODULEMODE_HWCTRL,
 663                 },
 664         },
 665 };
 666
 667 /*
 668  * 'dss' class
 669  * display sub-system
 670  */
 671
 672 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 673         .rev_offs       = 0x0000,
 674         .syss_offs      = 0x0014,
 675         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 676 };
 677
 678 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 679         .name   = "dss",
 680         .sysc   = &omap44xx_dss_sysc,
 681         .reset  = omap_dss_reset,
 682 };
 683
 684 /* dss */
 685 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 686         { .role = "sys_clk", .clk = "dss_sys_clk" },
 687         { .role = "tv_clk", .clk = "dss_tv_clk" },
 688         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 689 };
 690
 691 static struct omap_hwmod omap44xx_dss_hwmod = {
 692         .name           = "dss_core",
 693         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 694         .class          = &omap44xx_dss_hwmod_class,
 695         .clkdm_name     = "l3_dss_clkdm",
 696         .main_clk       = "dss_dss_clk",
 697         .prcm = {
 698                 .omap4 = {
 699                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 700                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 701                 },
 702         },
 703         .opt_clks       = dss_opt_clks,
 704         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 705 };
 706
 707 /*
 708  * 'dispc' class
 709  * display controller
 710  */
 711
 712 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 713         .rev_offs       = 0x0000,
 714         .sysc_offs      = 0x0010,
 715         .syss_offs      = 0x0014,
 716         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 717                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 718                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 719                            SYSS_HAS_RESET_STATUS),
 720         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 721                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 722         .sysc_fields    = &omap_hwmod_sysc_type1,
 723 };
 724
 725 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 726         .name   = "dispc",
 727         .sysc   = &omap44xx_dispc_sysc,
 728 };
 729
 730 /* dss_dispc */
 731 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 732         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 733         { .irq = -1 }
 734 };
 735
 736 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 737         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 738         { .dma_req = -1 }
 739 };
 740
 741 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 742         .manager_count          = 3,
 743         .has_framedonetv_irq    = 1
 744 };
 745
 746 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 747         .name           = "dss_dispc",
 748         .class          = &omap44xx_dispc_hwmod_class,
 749         .clkdm_name     = "l3_dss_clkdm",
 750         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 751         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 752         .main_clk       = "dss_dss_clk",
 753         .prcm = {
 754                 .omap4 = {
 755                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 756                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 757                 },
 758         },
 759         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 760 };
 761
 762 /*
 763  * 'dsi' class
 764  * display serial interface controller
 765  */
 766
 767 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 768         .rev_offs       = 0x0000,
 769         .sysc_offs      = 0x0010,
 770         .syss_offs      = 0x0014,
 771         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 772                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 773                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 774         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 775         .sysc_fields    = &omap_hwmod_sysc_type1,
 776 };
 777
 778 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 779         .name   = "dsi",
 780         .sysc   = &omap44xx_dsi_sysc,
 781 };
 782
 783 /* dss_dsi1 */
 784 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 785         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 786         { .irq = -1 }
 787 };
 788
 789 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 790         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 791         { .dma_req = -1 }
 792 };
 793
 794 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 795         { .role = "sys_clk", .clk = "dss_sys_clk" },
 796 };
 797
 798 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 799         .name           = "dss_dsi1",
 800         .class          = &omap44xx_dsi_hwmod_class,
 801         .clkdm_name     = "l3_dss_clkdm",
 802         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 803         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 804         .main_clk       = "dss_dss_clk",
 805         .prcm = {
 806                 .omap4 = {
 807                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 808                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 809                 },
 810         },
 811         .opt_clks       = dss_dsi1_opt_clks,
 812         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 813 };
 814
 815 /* dss_dsi2 */
 816 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 817         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 818         { .irq = -1 }
 819 };
 820
 821 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 822         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 823         { .dma_req = -1 }
 824 };
 825
 826 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 827         { .role = "sys_clk", .clk = "dss_sys_clk" },
 828 };
 829
 830 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 831         .name           = "dss_dsi2",
 832         .class          = &omap44xx_dsi_hwmod_class,
 833         .clkdm_name     = "l3_dss_clkdm",
 834         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 835         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 836         .main_clk       = "dss_dss_clk",
 837         .prcm = {
 838                 .omap4 = {
 839                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 840                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 841                 },
 842         },
 843         .opt_clks       = dss_dsi2_opt_clks,
 844         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 845 };
 846
 847 /*
 848  * 'hdmi' class
 849  * hdmi controller
 850  */
 851
 852 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 853         .rev_offs       = 0x0000,
 854         .sysc_offs      = 0x0010,
 855         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 856                            SYSC_HAS_SOFTRESET),
 857         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 858                            SIDLE_SMART_WKUP),
 859         .sysc_fields    = &omap_hwmod_sysc_type2,
 860 };
 861
 862 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 863         .name   = "hdmi",
 864         .sysc   = &omap44xx_hdmi_sysc,
 865 };
 866
 867 /* dss_hdmi */
 868 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 869         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 870         { .irq = -1 }
 871 };
 872
 873 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 874         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 875         { .dma_req = -1 }
 876 };
 877
 878 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 879         { .role = "sys_clk", .clk = "dss_sys_clk" },
 880 };
 881
 882 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 883         .name           = "dss_hdmi",
 884         .class          = &omap44xx_hdmi_hwmod_class,
 885         .clkdm_name     = "l3_dss_clkdm",
 886         /*
 887          * HDMI audio requires to use no-idle mode. Hence,
 888          * set idle mode by software.
 889          */
 890         .flags          = HWMOD_SWSUP_SIDLE,
 891         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 892         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 893         .main_clk       = "dss_48mhz_clk",
 894         .prcm = {
 895                 .omap4 = {
 896                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 897                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 898                 },
 899         },
 900         .opt_clks       = dss_hdmi_opt_clks,
 901         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 902 };
 903
 904 /*
 905  * 'rfbi' class
 906  * remote frame buffer interface
 907  */
 908
 909 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 910         .rev_offs       = 0x0000,
 911         .sysc_offs      = 0x0010,
 912         .syss_offs      = 0x0014,
 913         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 914                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 915         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 916         .sysc_fields    = &omap_hwmod_sysc_type1,
 917 };
 918
 919 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 920         .name   = "rfbi",
 921         .sysc   = &omap44xx_rfbi_sysc,
 922 };
 923
 924 /* dss_rfbi */
 925 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 926         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 927         { .dma_req = -1 }
 928 };
 929
 930 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 931         { .role = "ick", .clk = "dss_fck" },
 932 };
 933
 934 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 935         .name           = "dss_rfbi",
 936         .class          = &omap44xx_rfbi_hwmod_class,
 937         .clkdm_name     = "l3_dss_clkdm",
 938         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 939         .main_clk       = "dss_dss_clk",
 940         .prcm = {
 941                 .omap4 = {
 942                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 943                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 944                 },
 945         },
 946         .opt_clks       = dss_rfbi_opt_clks,
 947         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 948 };
 949
 950 /*
 951  * 'venc' class
 952  * video encoder
 953  */
 954
 955 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 956         .name   = "venc",
 957 };
 958
 959 /* dss_venc */
 960 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 961         .name           = "dss_venc",
 962         .class          = &omap44xx_venc_hwmod_class,
 963         .clkdm_name     = "l3_dss_clkdm",
 964         .main_clk       = "dss_tv_clk",
 965         .prcm = {
 966                 .omap4 = {
 967                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 968                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 969                 },
 970         },
 971 };
 972
 973 /*
 974  * 'elm' class
 975  * bch error location module
 976  */
 977
 978 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 979         .rev_offs       = 0x0000,
 980         .sysc_offs      = 0x0010,
 981         .syss_offs      = 0x0014,
 982         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 983                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 984                            SYSS_HAS_RESET_STATUS),
 985         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 986         .sysc_fields    = &omap_hwmod_sysc_type1,
 987 };
 988
 989 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 990         .name   = "elm",
 991         .sysc   = &omap44xx_elm_sysc,
 992 };
 993
 994 /* elm */
 995 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 996         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 997         { .irq = -1 }
 998 };
 999
1000 static struct omap_hwmod omap44xx_elm_hwmod = {
1001         .name           = "elm",
1002         .class          = &omap44xx_elm_hwmod_class,
1003         .clkdm_name     = "l4_per_clkdm",
1004         .mpu_irqs       = omap44xx_elm_irqs,
1005         .prcm = {
1006                 .omap4 = {
1007                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1008                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1009                 },
1010         },
1011 };
1012
1013 /*
1014  * 'emif' class
1015  * external memory interface no1
1016  */
1017
1018 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1019         .rev_offs       = 0x0000,
1020 };
1021
1022 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1023         .name   = "emif",
1024         .sysc   = &omap44xx_emif_sysc,
1025 };
1026
1027 /* emif1 */
1028 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1029         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1030         { .irq = -1 }
1031 };
1032
1033 static struct omap_hwmod omap44xx_emif1_hwmod = {
1034         .name           = "emif1",
1035         .class          = &omap44xx_emif_hwmod_class,
1036         .clkdm_name     = "l3_emif_clkdm",
1037         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1038         .mpu_irqs       = omap44xx_emif1_irqs,
1039         .main_clk       = "ddrphy_ck",
1040         .prcm = {
1041                 .omap4 = {
1042                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1043                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1044                         .modulemode   = MODULEMODE_HWCTRL,
1045                 },
1046         },
1047 };
1048
1049 /* emif2 */
1050 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1051         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1052         { .irq = -1 }
1053 };
1054
1055 static struct omap_hwmod omap44xx_emif2_hwmod = {
1056         .name           = "emif2",
1057         .class          = &omap44xx_emif_hwmod_class,
1058         .clkdm_name     = "l3_emif_clkdm",
1059         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1060         .mpu_irqs       = omap44xx_emif2_irqs,
1061         .main_clk       = "ddrphy_ck",
1062         .prcm = {
1063                 .omap4 = {
1064                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1065                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1066                         .modulemode   = MODULEMODE_HWCTRL,
1067                 },
1068         },
1069 };
1070
1071 /*
1072  * 'fdif' class
1073  * face detection hw accelerator module
1074  */
1075
1076 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1077         .rev_offs       = 0x0000,
1078         .sysc_offs      = 0x0010,
1079         /*
1080          * FDIF needs 100 OCP clk cycles delay after a softreset before
1081          * accessing sysconfig again.
1082          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1083          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1084          *
1085          * TODO: Indicate errata when available.
1086          */
1087         .srst_udelay    = 2,
1088         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1089                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1090         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1091                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1092         .sysc_fields    = &omap_hwmod_sysc_type2,
1093 };
1094
1095 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1096         .name   = "fdif",
1097         .sysc   = &omap44xx_fdif_sysc,
1098 };
1099
1100 /* fdif */
1101 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1102         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1103         { .irq = -1 }
1104 };
1105
1106 static struct omap_hwmod omap44xx_fdif_hwmod = {
1107         .name           = "fdif",
1108         .class          = &omap44xx_fdif_hwmod_class,
1109         .clkdm_name     = "iss_clkdm",
1110         .mpu_irqs       = omap44xx_fdif_irqs,
1111         .main_clk       = "fdif_fck",
1112         .prcm = {
1113                 .omap4 = {
1114                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1115                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1116                         .modulemode   = MODULEMODE_SWCTRL,
1117                 },
1118         },
1119 };
1120
1121 /*
1122  * 'gpio' class
1123  * general purpose io module
1124  */
1125
1126 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1127         .rev_offs       = 0x0000,
1128         .sysc_offs      = 0x0010,
1129         .syss_offs      = 0x0114,
1130         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1131                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1132                            SYSS_HAS_RESET_STATUS),
1133         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1134                            SIDLE_SMART_WKUP),
1135         .sysc_fields    = &omap_hwmod_sysc_type1,
1136 };
1137
1138 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1139         .name   = "gpio",
1140         .sysc   = &omap44xx_gpio_sysc,
1141         .rev    = 2,
1142 };
1143
1144 /* gpio dev_attr */
1145 static struct omap_gpio_dev_attr gpio_dev_attr = {
1146         .bank_width     = 32,
1147         .dbck_flag      = true,
1148 };
1149
1150 /* gpio1 */
1151 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1152         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1153         { .irq = -1 }
1154 };
1155
1156 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1157         { .role = "dbclk", .clk = "gpio1_dbclk" },
1158 };
1159
1160 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1161         .name           = "gpio1",
1162         .class          = &omap44xx_gpio_hwmod_class,
1163         .clkdm_name     = "l4_wkup_clkdm",
1164         .mpu_irqs       = omap44xx_gpio1_irqs,
1165         .main_clk       = "l4_wkup_clk_mux_ck",
1166         .prcm = {
1167                 .omap4 = {
1168                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1169                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1170                         .modulemode   = MODULEMODE_HWCTRL,
1171                 },
1172         },
1173         .opt_clks       = gpio1_opt_clks,
1174         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1175         .dev_attr       = &gpio_dev_attr,
1176 };
1177
1178 /* gpio2 */
1179 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1180         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1181         { .irq = -1 }
1182 };
1183
1184 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1185         { .role = "dbclk", .clk = "gpio2_dbclk" },
1186 };
1187
1188 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1189         .name           = "gpio2",
1190         .class          = &omap44xx_gpio_hwmod_class,
1191         .clkdm_name     = "l4_per_clkdm",
1192         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1193         .mpu_irqs       = omap44xx_gpio2_irqs,
1194         .main_clk       = "l4_div_ck",
1195         .prcm = {
1196                 .omap4 = {
1197                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1198                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1199                         .modulemode   = MODULEMODE_HWCTRL,
1200                 },
1201         },
1202         .opt_clks       = gpio2_opt_clks,
1203         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1204         .dev_attr       = &gpio_dev_attr,
1205 };
1206
1207 /* gpio3 */
1208 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1209         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1210         { .irq = -1 }
1211 };
1212
1213 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1214         { .role = "dbclk", .clk = "gpio3_dbclk" },
1215 };
1216
1217 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1218         .name           = "gpio3",
1219         .class          = &omap44xx_gpio_hwmod_class,
1220         .clkdm_name     = "l4_per_clkdm",
1221         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1222         .mpu_irqs       = omap44xx_gpio3_irqs,
1223         .main_clk       = "l4_div_ck",
1224         .prcm = {
1225                 .omap4 = {
1226                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1227                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1228                         .modulemode   = MODULEMODE_HWCTRL,
1229                 },
1230         },
1231         .opt_clks       = gpio3_opt_clks,
1232         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1233         .dev_attr       = &gpio_dev_attr,
1234 };
1235
1236 /* gpio4 */
1237 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1238         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1239         { .irq = -1 }
1240 };
1241
1242 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1243         { .role = "dbclk", .clk = "gpio4_dbclk" },
1244 };
1245
1246 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1247         .name           = "gpio4",
1248         .class          = &omap44xx_gpio_hwmod_class,
1249         .clkdm_name     = "l4_per_clkdm",
1250         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1251         .mpu_irqs       = omap44xx_gpio4_irqs,
1252         .main_clk       = "l4_div_ck",
1253         .prcm = {
1254                 .omap4 = {
1255                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1256                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1257                         .modulemode   = MODULEMODE_HWCTRL,
1258                 },
1259         },
1260         .opt_clks       = gpio4_opt_clks,
1261         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1262         .dev_attr       = &gpio_dev_attr,
1263 };
1264
1265 /* gpio5 */
1266 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1267         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1268         { .irq = -1 }
1269 };
1270
1271 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1272         { .role = "dbclk", .clk = "gpio5_dbclk" },
1273 };
1274
1275 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1276         .name           = "gpio5",
1277         .class          = &omap44xx_gpio_hwmod_class,
1278         .clkdm_name     = "l4_per_clkdm",
1279         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1280         .mpu_irqs       = omap44xx_gpio5_irqs,
1281         .main_clk       = "l4_div_ck",
1282         .prcm = {
1283                 .omap4 = {
1284                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1285                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1286                         .modulemode   = MODULEMODE_HWCTRL,
1287                 },
1288         },
1289         .opt_clks       = gpio5_opt_clks,
1290         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1291         .dev_attr       = &gpio_dev_attr,
1292 };
1293
1294 /* gpio6 */
1295 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1296         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1297         { .irq = -1 }
1298 };
1299
1300 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1301         { .role = "dbclk", .clk = "gpio6_dbclk" },
1302 };
1303
1304 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1305         .name           = "gpio6",
1306         .class          = &omap44xx_gpio_hwmod_class,
1307         .clkdm_name     = "l4_per_clkdm",
1308         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1309         .mpu_irqs       = omap44xx_gpio6_irqs,
1310         .main_clk       = "l4_div_ck",
1311         .prcm = {
1312                 .omap4 = {
1313                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1314                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1315                         .modulemode   = MODULEMODE_HWCTRL,
1316                 },
1317         },
1318         .opt_clks       = gpio6_opt_clks,
1319         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1320         .dev_attr       = &gpio_dev_attr,
1321 };
1322
1323 /*
1324  * 'gpmc' class
1325  * general purpose memory controller
1326  */
1327
1328 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1329         .rev_offs       = 0x0000,
1330         .sysc_offs      = 0x0010,
1331         .syss_offs      = 0x0014,
1332         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1333                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1334         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1335         .sysc_fields    = &omap_hwmod_sysc_type1,
1336 };
1337
1338 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1339         .name   = "gpmc",
1340         .sysc   = &omap44xx_gpmc_sysc,
1341 };
1342
1343 /* gpmc */
1344 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1345         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1346         { .irq = -1 }
1347 };
1348
1349 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1350         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1351         { .dma_req = -1 }
1352 };
1353
1354 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1355         .name           = "gpmc",
1356         .class          = &omap44xx_gpmc_hwmod_class,
1357         .clkdm_name     = "l3_2_clkdm",
1358         /*
1359          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1360          * block.  It is not being added due to any known bugs with
1361          * resetting the GPMC IP block, but rather because any timings
1362          * set by the bootloader are not being correctly programmed by
1363          * the kernel from the board file or DT data.
1364          * HWMOD_INIT_NO_RESET should be removed ASAP.
1365          */
1366         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1367         .mpu_irqs       = omap44xx_gpmc_irqs,
1368         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1369         .prcm = {
1370                 .omap4 = {
1371                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1372                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1373                         .modulemode   = MODULEMODE_HWCTRL,
1374                 },
1375         },
1376 };
1377
1378 /*
1379  * 'gpu' class
1380  * 2d/3d graphics accelerator
1381  */
1382
1383 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1384         .rev_offs       = 0x1fc00,
1385         .sysc_offs      = 0x1fc10,
1386         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1387         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1388                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1389                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1390         .sysc_fields    = &omap_hwmod_sysc_type2,
1391 };
1392
1393 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1394         .name   = "gpu",
1395         .sysc   = &omap44xx_gpu_sysc,
1396 };
1397
1398 /* gpu */
1399 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1400         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1401         { .irq = -1 }
1402 };
1403
1404 static struct omap_hwmod omap44xx_gpu_hwmod = {
1405         .name           = "gpu",
1406         .class          = &omap44xx_gpu_hwmod_class,
1407         .clkdm_name     = "l3_gfx_clkdm",
1408         .mpu_irqs       = omap44xx_gpu_irqs,
1409         .main_clk       = "sgx_clk_mux",
1410         .prcm = {
1411                 .omap4 = {
1412                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1413                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1414                         .modulemode   = MODULEMODE_SWCTRL,
1415                 },
1416         },
1417 };
1418
1419 /*
1420  * 'hdq1w' class
1421  * hdq / 1-wire serial interface controller
1422  */
1423
1424 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1425         .rev_offs       = 0x0000,
1426         .sysc_offs      = 0x0014,
1427         .syss_offs      = 0x0018,
1428         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1429                            SYSS_HAS_RESET_STATUS),
1430         .sysc_fields    = &omap_hwmod_sysc_type1,
1431 };
1432
1433 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1434         .name   = "hdq1w",
1435         .sysc   = &omap44xx_hdq1w_sysc,
1436 };
1437
1438 /* hdq1w */
1439 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1440         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1441         { .irq = -1 }
1442 };
1443
1444 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1445         .name           = "hdq1w",
1446         .class          = &omap44xx_hdq1w_hwmod_class,
1447         .clkdm_name     = "l4_per_clkdm",
1448         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1449         .mpu_irqs       = omap44xx_hdq1w_irqs,
1450         .main_clk       = "func_12m_fclk",
1451         .prcm = {
1452                 .omap4 = {
1453                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1454                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1455                         .modulemode   = MODULEMODE_SWCTRL,
1456                 },
1457         },
1458 };
1459
1460 /*
1461  * 'hsi' class
1462  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1463  * serial if)
1464  */
1465
1466 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1467         .rev_offs       = 0x0000,
1468         .sysc_offs      = 0x0010,
1469         .syss_offs      = 0x0014,
1470         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1471                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1472                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1473         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1474                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1475                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1476         .sysc_fields    = &omap_hwmod_sysc_type1,
1477 };
1478
1479 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1480         .name   = "hsi",
1481         .sysc   = &omap44xx_hsi_sysc,
1482 };
1483
1484 /* hsi */
1485 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1486         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1487         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1488         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1489         { .irq = -1 }
1490 };
1491
1492 static struct omap_hwmod omap44xx_hsi_hwmod = {
1493         .name           = "hsi",
1494         .class          = &omap44xx_hsi_hwmod_class,
1495         .clkdm_name     = "l3_init_clkdm",
1496         .mpu_irqs       = omap44xx_hsi_irqs,
1497         .main_clk       = "hsi_fck",
1498         .prcm = {
1499                 .omap4 = {
1500                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1501                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1502                         .modulemode   = MODULEMODE_HWCTRL,
1503                 },
1504         },
1505 };
1506
1507 /*
1508  * 'i2c' class
1509  * multimaster high-speed i2c controller
1510  */
1511
1512 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1513         .sysc_offs      = 0x0010,
1514         .syss_offs      = 0x0090,
1515         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1516                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1517                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1518         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1519                            SIDLE_SMART_WKUP),
1520         .clockact       = CLOCKACT_TEST_ICLK,
1521         .sysc_fields    = &omap_hwmod_sysc_type1,
1522 };
1523
1524 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1525         .name   = "i2c",
1526         .sysc   = &omap44xx_i2c_sysc,
1527         .rev    = OMAP_I2C_IP_VERSION_2,
1528         .reset  = &omap_i2c_reset,
1529 };
1530
1531 static struct omap_i2c_dev_attr i2c_dev_attr = {
1532         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1533 };
1534
1535 /* i2c1 */
1536 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1537         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1538         { .irq = -1 }
1539 };
1540
1541 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1542         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1543         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1544         { .dma_req = -1 }
1545 };
1546
1547 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1548         .name           = "i2c1",
1549         .class          = &omap44xx_i2c_hwmod_class,
1550         .clkdm_name     = "l4_per_clkdm",
1551         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1552         .mpu_irqs       = omap44xx_i2c1_irqs,
1553         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1554         .main_clk       = "func_96m_fclk",
1555         .prcm = {
1556                 .omap4 = {
1557                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1558                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1559                         .modulemode   = MODULEMODE_SWCTRL,
1560                 },
1561         },
1562         .dev_attr       = &i2c_dev_attr,
1563 };
1564
1565 /* i2c2 */
1566 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1567         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1568         { .irq = -1 }
1569 };
1570
1571 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1572         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1573         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1574         { .dma_req = -1 }
1575 };
1576
1577 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1578         .name           = "i2c2",
1579         .class          = &omap44xx_i2c_hwmod_class,
1580         .clkdm_name     = "l4_per_clkdm",
1581         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1582         .mpu_irqs       = omap44xx_i2c2_irqs,
1583         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1584         .main_clk       = "func_96m_fclk",
1585         .prcm = {
1586                 .omap4 = {
1587                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1588                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1589                         .modulemode   = MODULEMODE_SWCTRL,
1590                 },
1591         },
1592         .dev_attr       = &i2c_dev_attr,
1593 };
1594
1595 /* i2c3 */
1596 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1597         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1598         { .irq = -1 }
1599 };
1600
1601 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1602         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1603         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1604         { .dma_req = -1 }
1605 };
1606
1607 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1608         .name           = "i2c3",
1609         .class          = &omap44xx_i2c_hwmod_class,
1610         .clkdm_name     = "l4_per_clkdm",
1611         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1612         .mpu_irqs       = omap44xx_i2c3_irqs,
1613         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1614         .main_clk       = "func_96m_fclk",
1615         .prcm = {
1616                 .omap4 = {
1617                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1618                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1619                         .modulemode   = MODULEMODE_SWCTRL,
1620                 },
1621         },
1622         .dev_attr       = &i2c_dev_attr,
1623 };
1624
1625 /* i2c4 */
1626 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1627         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1628         { .irq = -1 }
1629 };
1630
1631 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1632         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1633         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1634         { .dma_req = -1 }
1635 };
1636
1637 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1638         .name           = "i2c4",
1639         .class          = &omap44xx_i2c_hwmod_class,
1640         .clkdm_name     = "l4_per_clkdm",
1641         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1642         .mpu_irqs       = omap44xx_i2c4_irqs,
1643         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1644         .main_clk       = "func_96m_fclk",
1645         .prcm = {
1646                 .omap4 = {
1647                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1648                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1649                         .modulemode   = MODULEMODE_SWCTRL,
1650                 },
1651         },
1652         .dev_attr       = &i2c_dev_attr,
1653 };
1654
1655 /*
1656  * 'ipu' class
1657  * imaging processor unit
1658  */
1659
1660 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1661         .name   = "ipu",
1662 };
1663
1664 /* ipu */
1665 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1666         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1667         { .irq = -1 }
1668 };
1669
1670 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1671         { .name = "cpu0", .rst_shift = 0 },
1672         { .name = "cpu1", .rst_shift = 1 },
1673 };
1674
1675 static struct omap_hwmod omap44xx_ipu_hwmod = {
1676         .name           = "ipu",
1677         .class          = &omap44xx_ipu_hwmod_class,
1678         .clkdm_name     = "ducati_clkdm",
1679         .mpu_irqs       = omap44xx_ipu_irqs,
1680         .rst_lines      = omap44xx_ipu_resets,
1681         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1682         .main_clk       = "ducati_clk_mux_ck",
1683         .prcm = {
1684                 .omap4 = {
1685                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1686                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1687                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1688                         .modulemode   = MODULEMODE_HWCTRL,
1689                 },
1690         },
1691 };
1692
1693 /*
1694  * 'iss' class
1695  * external images sensor pixel data processor
1696  */
1697
1698 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1699         .rev_offs       = 0x0000,
1700         .sysc_offs      = 0x0010,
1701         /*
1702          * ISS needs 100 OCP clk cycles delay after a softreset before
1703          * accessing sysconfig again.
1704          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1705          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1706          *
1707          * TODO: Indicate errata when available.
1708          */
1709         .srst_udelay    = 2,
1710         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1711                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1712         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1713                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1714                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1715         .sysc_fields    = &omap_hwmod_sysc_type2,
1716 };
1717
1718 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1719         .name   = "iss",
1720         .sysc   = &omap44xx_iss_sysc,
1721 };
1722
1723 /* iss */
1724 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1725         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1726         { .irq = -1 }
1727 };
1728
1729 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1730         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1731         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1732         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1733         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1734         { .dma_req = -1 }
1735 };
1736
1737 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1738         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1739 };
1740
1741 static struct omap_hwmod omap44xx_iss_hwmod = {
1742         .name           = "iss",
1743         .class          = &omap44xx_iss_hwmod_class,
1744         .clkdm_name     = "iss_clkdm",
1745         .mpu_irqs       = omap44xx_iss_irqs,
1746         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1747         .main_clk       = "ducati_clk_mux_ck",
1748         .prcm = {
1749                 .omap4 = {
1750                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1751                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1752                         .modulemode   = MODULEMODE_SWCTRL,
1753                 },
1754         },
1755         .opt_clks       = iss_opt_clks,
1756         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1757 };
1758
1759 /*
1760  * 'iva' class
1761  * multi-standard video encoder/decoder hardware accelerator
1762  */
1763
1764 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1765         .name   = "iva",
1766 };
1767
1768 /* iva */
1769 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1770         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1771         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1772         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1773         { .irq = -1 }
1774 };
1775
1776 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1777         { .name = "seq0", .rst_shift = 0 },
1778         { .name = "seq1", .rst_shift = 1 },
1779         { .name = "logic", .rst_shift = 2 },
1780 };
1781
1782 static struct omap_hwmod omap44xx_iva_hwmod = {
1783         .name           = "iva",
1784         .class          = &omap44xx_iva_hwmod_class,
1785         .clkdm_name     = "ivahd_clkdm",
1786         .mpu_irqs       = omap44xx_iva_irqs,
1787         .rst_lines      = omap44xx_iva_resets,
1788         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1789         .main_clk       = "dpll_iva_m5x2_ck",
1790         .prcm = {
1791                 .omap4 = {
1792                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1793                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1794                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1795                         .modulemode   = MODULEMODE_HWCTRL,
1796                 },
1797         },
1798 };
1799
1800 /*
1801  * 'kbd' class
1802  * keyboard controller
1803  */
1804
1805 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1806         .rev_offs       = 0x0000,
1807         .sysc_offs      = 0x0010,
1808         .syss_offs      = 0x0014,
1809         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1810                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1811                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1812                            SYSS_HAS_RESET_STATUS),
1813         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1814         .sysc_fields    = &omap_hwmod_sysc_type1,
1815 };
1816
1817 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1818         .name   = "kbd",
1819         .sysc   = &omap44xx_kbd_sysc,
1820 };
1821
1822 /* kbd */
1823 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1824         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1825         { .irq = -1 }
1826 };
1827
1828 static struct omap_hwmod omap44xx_kbd_hwmod = {
1829         .name           = "kbd",
1830         .class          = &omap44xx_kbd_hwmod_class,
1831         .clkdm_name     = "l4_wkup_clkdm",
1832         .mpu_irqs       = omap44xx_kbd_irqs,
1833         .main_clk       = "sys_32k_ck",
1834         .prcm = {
1835                 .omap4 = {
1836                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1837                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1838                         .modulemode   = MODULEMODE_SWCTRL,
1839                 },
1840         },
1841 };
1842
1843 /*
1844  * 'mailbox' class
1845  * mailbox module allowing communication between the on-chip processors using a
1846  * queued mailbox-interrupt mechanism.
1847  */
1848
1849 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1850         .rev_offs       = 0x0000,
1851         .sysc_offs      = 0x0010,
1852         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1853                            SYSC_HAS_SOFTRESET),
1854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1855         .sysc_fields    = &omap_hwmod_sysc_type2,
1856 };
1857
1858 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1859         .name   = "mailbox",
1860         .sysc   = &omap44xx_mailbox_sysc,
1861 };
1862
1863 /* mailbox */
1864 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1865         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1866         { .irq = -1 }
1867 };
1868
1869 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1870         .name           = "mailbox",
1871         .class          = &omap44xx_mailbox_hwmod_class,
1872         .clkdm_name     = "l4_cfg_clkdm",
1873         .mpu_irqs       = omap44xx_mailbox_irqs,
1874         .prcm = {
1875                 .omap4 = {
1876                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1877                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1878                 },
1879         },
1880 };
1881
1882 /*
1883  * 'mcasp' class
1884  * multi-channel audio serial port controller
1885  */
1886
1887 /* The IP is not compliant to type1 / type2 scheme */
1888 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1889         .sidle_shift    = 0,
1890 };
1891
1892 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1893         .sysc_offs      = 0x0004,
1894         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1895         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1896                            SIDLE_SMART_WKUP),
1897         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1898 };
1899
1900 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1901         .name   = "mcasp",
1902         .sysc   = &omap44xx_mcasp_sysc,
1903 };
1904
1905 /* mcasp */
1906 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1907         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1908         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1909         { .irq = -1 }
1910 };
1911
1912 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1913         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1914         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1915         { .dma_req = -1 }
1916 };
1917
1918 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1919         .name           = "mcasp",
1920         .class          = &omap44xx_mcasp_hwmod_class,
1921         .clkdm_name     = "abe_clkdm",
1922         .mpu_irqs       = omap44xx_mcasp_irqs,
1923         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1924         .main_clk       = "func_mcasp_abe_gfclk",
1925         .prcm = {
1926                 .omap4 = {
1927                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1928                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1929                         .modulemode   = MODULEMODE_SWCTRL,
1930                 },
1931         },
1932 };
1933
1934 /*
1935  * 'mcbsp' class
1936  * multi channel buffered serial port controller
1937  */
1938
1939 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1940         .sysc_offs      = 0x008c,
1941         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1942                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1943         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1944         .sysc_fields    = &omap_hwmod_sysc_type1,
1945 };
1946
1947 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1948         .name   = "mcbsp",
1949         .sysc   = &omap44xx_mcbsp_sysc,
1950         .rev    = MCBSP_CONFIG_TYPE4,
1951 };
1952
1953 /* mcbsp1 */
1954 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1955         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1956         { .irq = -1 }
1957 };
1958
1959 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1960         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1961         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1962         { .dma_req = -1 }
1963 };
1964
1965 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1966         { .role = "pad_fck", .clk = "pad_clks_ck" },
1967         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1968 };
1969
1970 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1971         .name           = "mcbsp1",
1972         .class          = &omap44xx_mcbsp_hwmod_class,
1973         .clkdm_name     = "abe_clkdm",
1974         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1975         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1976         .main_clk       = "func_mcbsp1_gfclk",
1977         .prcm = {
1978                 .omap4 = {
1979                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1980                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1981                         .modulemode   = MODULEMODE_SWCTRL,
1982                 },
1983         },
1984         .opt_clks       = mcbsp1_opt_clks,
1985         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1986 };
1987
1988 /* mcbsp2 */
1989 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1990         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1991         { .irq = -1 }
1992 };
1993
1994 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1995         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1996         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1997         { .dma_req = -1 }
1998 };
1999
2000 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2001         { .role = "pad_fck", .clk = "pad_clks_ck" },
2002         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2003 };
2004
2005 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2006         .name           = "mcbsp2",
2007         .class          = &omap44xx_mcbsp_hwmod_class,
2008         .clkdm_name     = "abe_clkdm",
2009         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2010         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2011         .main_clk       = "func_mcbsp2_gfclk",
2012         .prcm = {
2013                 .omap4 = {
2014                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2015                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2016                         .modulemode   = MODULEMODE_SWCTRL,
2017                 },
2018         },
2019         .opt_clks       = mcbsp2_opt_clks,
2020         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2021 };
2022
2023 /* mcbsp3 */
2024 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2025         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2026         { .irq = -1 }
2027 };
2028
2029 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2030         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2031         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2032         { .dma_req = -1 }
2033 };
2034
2035 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2036         { .role = "pad_fck", .clk = "pad_clks_ck" },
2037         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2038 };
2039
2040 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2041         .name           = "mcbsp3",
2042         .class          = &omap44xx_mcbsp_hwmod_class,
2043         .clkdm_name     = "abe_clkdm",
2044         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2045         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2046         .main_clk       = "func_mcbsp3_gfclk",
2047         .prcm = {
2048                 .omap4 = {
2049                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2050                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2051                         .modulemode   = MODULEMODE_SWCTRL,
2052                 },
2053         },
2054         .opt_clks       = mcbsp3_opt_clks,
2055         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2056 };
2057
2058 /* mcbsp4 */
2059 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2060         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2061         { .irq = -1 }
2062 };
2063
2064 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2065         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2066         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2067         { .dma_req = -1 }
2068 };
2069
2070 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2071         { .role = "pad_fck", .clk = "pad_clks_ck" },
2072         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2073 };
2074
2075 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2076         .name           = "mcbsp4",
2077         .class          = &omap44xx_mcbsp_hwmod_class,
2078         .clkdm_name     = "l4_per_clkdm",
2079         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2080         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2081         .main_clk       = "per_mcbsp4_gfclk",
2082         .prcm = {
2083                 .omap4 = {
2084                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2085                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2086                         .modulemode   = MODULEMODE_SWCTRL,
2087                 },
2088         },
2089         .opt_clks       = mcbsp4_opt_clks,
2090         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2091 };
2092
2093 /*
2094  * 'mcpdm' class
2095  * multi channel pdm controller (proprietary interface with phoenix power
2096  * ic)
2097  */
2098
2099 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2100         .rev_offs       = 0x0000,
2101         .sysc_offs      = 0x0010,
2102         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2103                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2104         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2105                            SIDLE_SMART_WKUP),
2106         .sysc_fields    = &omap_hwmod_sysc_type2,
2107 };
2108
2109 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2110         .name   = "mcpdm",
2111         .sysc   = &omap44xx_mcpdm_sysc,
2112 };
2113
2114 /* mcpdm */
2115 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2116         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2117         { .irq = -1 }
2118 };
2119
2120 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2121         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2122         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2123         { .dma_req = -1 }
2124 };
2125
2126 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2127         .name           = "mcpdm",
2128         .class          = &omap44xx_mcpdm_hwmod_class,
2129         .clkdm_name     = "abe_clkdm",
2130         /*
2131          * It's suspected that the McPDM requires an off-chip main
2132          * functional clock, controlled via I2C.  This IP block is
2133          * currently reset very early during boot, before I2C is
2134          * available, so it doesn't seem that we have any choice in
2135          * the kernel other than to avoid resetting it.
2136          *
2137          * Also, McPDM needs to be configured to NO_IDLE mode when it
2138          * is in used otherwise vital clocks will be gated which
2139          * results 'slow motion' audio playback.
2140          */
2141         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
2142         .mpu_irqs       = omap44xx_mcpdm_irqs,
2143         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2144         .main_clk       = "pad_clks_ck",
2145         .prcm = {
2146                 .omap4 = {
2147                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2148                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2149                         .modulemode   = MODULEMODE_SWCTRL,
2150                 },
2151         },
2152 };
2153
2154 /*
2155  * 'mcspi' class
2156  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2157  * bus
2158  */
2159
2160 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2161         .rev_offs       = 0x0000,
2162         .sysc_offs      = 0x0010,
2163         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2164                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2165         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2166                            SIDLE_SMART_WKUP),
2167         .sysc_fields    = &omap_hwmod_sysc_type2,
2168 };
2169
2170 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2171         .name   = "mcspi",
2172         .sysc   = &omap44xx_mcspi_sysc,
2173         .rev    = OMAP4_MCSPI_REV,
2174 };
2175
2176 /* mcspi1 */
2177 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2178         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2179         { .irq = -1 }
2180 };
2181
2182 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2183         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2184         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2185         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2186         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2187         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2188         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2189         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2190         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2191         { .dma_req = -1 }
2192 };
2193
2194 /* mcspi1 dev_attr */
2195 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2196         .num_chipselect = 4,
2197 };
2198
2199 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2200         .name           = "mcspi1",
2201         .class          = &omap44xx_mcspi_hwmod_class,
2202         .clkdm_name     = "l4_per_clkdm",
2203         .mpu_irqs       = omap44xx_mcspi1_irqs,
2204         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2205         .main_clk       = "func_48m_fclk",
2206         .prcm = {
2207                 .omap4 = {
2208                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2209                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2210                         .modulemode   = MODULEMODE_SWCTRL,
2211                 },
2212         },
2213         .dev_attr       = &mcspi1_dev_attr,
2214 };
2215
2216 /* mcspi2 */
2217 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2218         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2219         { .irq = -1 }
2220 };
2221
2222 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2223         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2224         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2225         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2226         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2227         { .dma_req = -1 }
2228 };
2229
2230 /* mcspi2 dev_attr */
2231 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2232         .num_chipselect = 2,
2233 };
2234
2235 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2236         .name           = "mcspi2",
2237         .class          = &omap44xx_mcspi_hwmod_class,
2238         .clkdm_name     = "l4_per_clkdm",
2239         .mpu_irqs       = omap44xx_mcspi2_irqs,
2240         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2241         .main_clk       = "func_48m_fclk",
2242         .prcm = {
2243                 .omap4 = {
2244                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2245                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2246                         .modulemode   = MODULEMODE_SWCTRL,
2247                 },
2248         },
2249         .dev_attr       = &mcspi2_dev_attr,
2250 };
2251
2252 /* mcspi3 */
2253 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2254         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2255         { .irq = -1 }
2256 };
2257
2258 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2259         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2260         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2261         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2262         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2263         { .dma_req = -1 }
2264 };
2265
2266 /* mcspi3 dev_attr */
2267 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2268         .num_chipselect = 2,
2269 };
2270
2271 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2272         .name           = "mcspi3",
2273         .class          = &omap44xx_mcspi_hwmod_class,
2274         .clkdm_name     = "l4_per_clkdm",
2275         .mpu_irqs       = omap44xx_mcspi3_irqs,
2276         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2277         .main_clk       = "func_48m_fclk",
2278         .prcm = {
2279                 .omap4 = {
2280                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2281                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2282                         .modulemode   = MODULEMODE_SWCTRL,
2283                 },
2284         },
2285         .dev_attr       = &mcspi3_dev_attr,
2286 };
2287
2288 /* mcspi4 */
2289 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2290         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2291         { .irq = -1 }
2292 };
2293
2294 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2295         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2296         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2297         { .dma_req = -1 }
2298 };
2299
2300 /* mcspi4 dev_attr */
2301 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2302         .num_chipselect = 1,
2303 };
2304
2305 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2306         .name           = "mcspi4",
2307         .class          = &omap44xx_mcspi_hwmod_class,
2308         .clkdm_name     = "l4_per_clkdm",
2309         .mpu_irqs       = omap44xx_mcspi4_irqs,
2310         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2311         .main_clk       = "func_48m_fclk",
2312         .prcm = {
2313                 .omap4 = {
2314                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2315                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2316                         .modulemode   = MODULEMODE_SWCTRL,
2317                 },
2318         },
2319         .dev_attr       = &mcspi4_dev_attr,
2320 };
2321
2322 /*
2323  * 'mmc' class
2324  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2325  */
2326
2327 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2328         .rev_offs       = 0x0000,
2329         .sysc_offs      = 0x0010,
2330         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2331                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2332                            SYSC_HAS_SOFTRESET),
2333         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2334                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2335                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2336         .sysc_fields    = &omap_hwmod_sysc_type2,
2337 };
2338
2339 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2340         .name   = "mmc",
2341         .sysc   = &omap44xx_mmc_sysc,
2342 };
2343
2344 /* mmc1 */
2345 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2346         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2347         { .irq = -1 }
2348 };
2349
2350 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2351         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2352         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2353         { .dma_req = -1 }
2354 };
2355
2356 /* mmc1 dev_attr */
2357 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2358         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2359 };
2360
2361 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2362         .name           = "mmc1",
2363         .class          = &omap44xx_mmc_hwmod_class,
2364         .clkdm_name     = "l3_init_clkdm",
2365         .mpu_irqs       = omap44xx_mmc1_irqs,
2366         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2367         .main_clk       = "hsmmc1_fclk",
2368         .prcm = {
2369                 .omap4 = {
2370                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2371                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2372                         .modulemode   = MODULEMODE_SWCTRL,
2373                 },
2374         },
2375         .dev_attr       = &mmc1_dev_attr,
2376 };
2377
2378 /* mmc2 */
2379 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2380         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2381         { .irq = -1 }
2382 };
2383
2384 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2385         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2386         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2387         { .dma_req = -1 }
2388 };
2389
2390 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2391         .name           = "mmc2",
2392         .class          = &omap44xx_mmc_hwmod_class,
2393         .clkdm_name     = "l3_init_clkdm",
2394         .mpu_irqs       = omap44xx_mmc2_irqs,
2395         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2396         .main_clk       = "hsmmc2_fclk",
2397         .prcm = {
2398                 .omap4 = {
2399                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2400                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2401                         .modulemode   = MODULEMODE_SWCTRL,
2402                 },
2403         },
2404 };
2405
2406 /* mmc3 */
2407 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2408         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2409         { .irq = -1 }
2410 };
2411
2412 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2413         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2414         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2415         { .dma_req = -1 }
2416 };
2417
2418 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2419         .name           = "mmc3",
2420         .class          = &omap44xx_mmc_hwmod_class,
2421         .clkdm_name     = "l4_per_clkdm",
2422         .mpu_irqs       = omap44xx_mmc3_irqs,
2423         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2424         .main_clk       = "func_48m_fclk",
2425         .prcm = {
2426                 .omap4 = {
2427                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2428                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2429                         .modulemode   = MODULEMODE_SWCTRL,
2430                 },
2431         },
2432 };
2433
2434 /* mmc4 */
2435 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2436         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2437         { .irq = -1 }
2438 };
2439
2440 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2441         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2442         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2443         { .dma_req = -1 }
2444 };
2445
2446 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2447         .name           = "mmc4",
2448         .class          = &omap44xx_mmc_hwmod_class,
2449         .clkdm_name     = "l4_per_clkdm",
2450         .mpu_irqs       = omap44xx_mmc4_irqs,
2451         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2452         .main_clk       = "func_48m_fclk",
2453         .prcm = {
2454                 .omap4 = {
2455                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2456                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2457                         .modulemode   = MODULEMODE_SWCTRL,
2458                 },
2459         },
2460 };
2461
2462 /* mmc5 */
2463 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2464         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2465         { .irq = -1 }
2466 };
2467
2468 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2469         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2470         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2471         { .dma_req = -1 }
2472 };
2473
2474 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2475         .name           = "mmc5",
2476         .class          = &omap44xx_mmc_hwmod_class,
2477         .clkdm_name     = "l4_per_clkdm",
2478         .mpu_irqs       = omap44xx_mmc5_irqs,
2479         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2480         .main_clk       = "func_48m_fclk",
2481         .prcm = {
2482                 .omap4 = {
2483                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2484                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2485                         .modulemode   = MODULEMODE_SWCTRL,
2486                 },
2487         },
2488 };
2489
2490 /*
2491  * 'mmu' class
2492  * The memory management unit performs virtual to physical address translation
2493  * for its requestors.
2494  */
2495
2496 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2497         .rev_offs       = 0x000,
2498         .sysc_offs      = 0x010,
2499         .syss_offs      = 0x014,
2500         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2501                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2502         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2503         .sysc_fields    = &omap_hwmod_sysc_type1,
2504 };
2505
2506 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2507         .name = "mmu",
2508         .sysc = &mmu_sysc,
2509 };
2510
2511 /* mmu ipu */
2512
2513 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2514         .da_start       = 0x0,
2515         .da_end         = 0xfffff000,
2516         .nr_tlb_entries = 32,
2517 };
2518
2519 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2520 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2521         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2522         { .irq = -1 }
2523 };
2524
2525 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2526         { .name = "mmu_cache", .rst_shift = 2 },
2527 };
2528
2529 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2530         {
2531                 .pa_start       = 0x55082000,
2532                 .pa_end         = 0x550820ff,
2533                 .flags          = ADDR_TYPE_RT,
2534         },
2535         { }
2536 };
2537
2538 /* l3_main_2 -> mmu_ipu */
2539 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2540         .master         = &omap44xx_l3_main_2_hwmod,
2541         .slave          = &omap44xx_mmu_ipu_hwmod,
2542         .clk            = "l3_div_ck",
2543         .addr           = omap44xx_mmu_ipu_addrs,
2544         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2545 };
2546
2547 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2548         .name           = "mmu_ipu",
2549         .class          = &omap44xx_mmu_hwmod_class,
2550         .clkdm_name     = "ducati_clkdm",
2551         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2552         .rst_lines      = omap44xx_mmu_ipu_resets,
2553         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2554         .main_clk       = "ducati_clk_mux_ck",
2555         .prcm = {
2556                 .omap4 = {
2557                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2558                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2559                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2560                         .modulemode   = MODULEMODE_HWCTRL,
2561                 },
2562         },
2563         .dev_attr       = &mmu_ipu_dev_attr,
2564 };
2565
2566 /* mmu dsp */
2567
2568 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2569         .da_start       = 0x0,
2570         .da_end         = 0xfffff000,
2571         .nr_tlb_entries = 32,
2572 };
2573
2574 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2575 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2576         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2577         { .irq = -1 }
2578 };
2579
2580 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2581         { .name = "mmu_cache", .rst_shift = 1 },
2582 };
2583
2584 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2585         {
2586                 .pa_start       = 0x4a066000,
2587                 .pa_end         = 0x4a0660ff,
2588                 .flags          = ADDR_TYPE_RT,
2589         },
2590         { }
2591 };
2592
2593 /* l4_cfg -> dsp */
2594 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2595         .master         = &omap44xx_l4_cfg_hwmod,
2596         .slave          = &omap44xx_mmu_dsp_hwmod,
2597         .clk            = "l4_div_ck",
2598         .addr           = omap44xx_mmu_dsp_addrs,
2599         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2600 };
2601
2602 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2603         .name           = "mmu_dsp",
2604         .class          = &omap44xx_mmu_hwmod_class,
2605         .clkdm_name     = "tesla_clkdm",
2606         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2607         .rst_lines      = omap44xx_mmu_dsp_resets,
2608         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2609         .main_clk       = "dpll_iva_m4x2_ck",
2610         .prcm = {
2611                 .omap4 = {
2612                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2613                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2614                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2615                         .modulemode   = MODULEMODE_HWCTRL,
2616                 },
2617         },
2618         .dev_attr       = &mmu_dsp_dev_attr,
2619 };
2620
2621 /*
2622  * 'mpu' class
2623  * mpu sub-system
2624  */
2625
2626 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2627         .name   = "mpu",
2628 };
2629
2630 /* mpu */
2631 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2632         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2633         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2634         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2635         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2636         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2637         { .irq = -1 }
2638 };
2639
2640 static struct omap_hwmod omap44xx_mpu_hwmod = {
2641         .name           = "mpu",
2642         .class          = &omap44xx_mpu_hwmod_class,
2643         .clkdm_name     = "mpuss_clkdm",
2644         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2645         .mpu_irqs       = omap44xx_mpu_irqs,
2646         .main_clk       = "dpll_mpu_m2_ck",
2647         .prcm = {
2648                 .omap4 = {
2649                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2650                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2651                 },
2652         },
2653 };
2654
2655 /*
2656  * 'ocmc_ram' class
2657  * top-level core on-chip ram
2658  */
2659
2660 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2661         .name   = "ocmc_ram",
2662 };
2663
2664 /* ocmc_ram */
2665 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2666         .name           = "ocmc_ram",
2667         .class          = &omap44xx_ocmc_ram_hwmod_class,
2668         .clkdm_name     = "l3_2_clkdm",
2669         .prcm = {
2670                 .omap4 = {
2671                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2672                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2673                 },
2674         },
2675 };
2676
2677 /*
2678  * 'ocp2scp' class
2679  * bridge to transform ocp interface protocol to scp (serial control port)
2680  * protocol
2681  */
2682
2683 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2684         .rev_offs       = 0x0000,
2685         .sysc_offs      = 0x0010,
2686         .syss_offs      = 0x0014,
2687         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2688                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2689         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2690         .sysc_fields    = &omap_hwmod_sysc_type1,
2691 };
2692
2693 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2694         .name   = "ocp2scp",
2695         .sysc   = &omap44xx_ocp2scp_sysc,
2696 };
2697
2698 /* ocp2scp dev_attr */
2699 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2700         {
2701                 .name           = "usb_phy",
2702                 .start          = 0x4a0ad080,
2703                 .end            = 0x4a0ae000,
2704                 .flags          = IORESOURCE_MEM,
2705         },
2706         { }
2707 };
2708
2709 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2710         {
2711                 .drv_name       = "omap-usb2",
2712                 .res            = omap44xx_usb_phy_and_pll_addrs,
2713         },
2714         { }
2715 };
2716
2717 /* ocp2scp_usb_phy */
2718 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2719         .name           = "ocp2scp_usb_phy",
2720         .class          = &omap44xx_ocp2scp_hwmod_class,
2721         .clkdm_name     = "l3_init_clkdm",
2722         /*
2723          * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2724          * block as an "optional clock," and normally should never be
2725          * specified as the main_clk for an OMAP IP block.  However it
2726          * turns out that this clock is actually the main clock for
2727          * the ocp2scp_usb_phy IP block:
2728          * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2729          * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2730          * to be the best workaround.
2731          */
2732         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2733         .prcm = {
2734                 .omap4 = {
2735                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2736                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2737                         .modulemode   = MODULEMODE_HWCTRL,
2738                 },
2739         },
2740         .dev_attr       = ocp2scp_dev_attr,
2741 };
2742
2743 /*
2744  * 'prcm' class
2745  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2746  * + clock manager 1 (in always on power domain) + local prm in mpu
2747  */
2748
2749 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2750         .name   = "prcm",
2751 };
2752
2753 /* prcm_mpu */
2754 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2755         .name           = "prcm_mpu",
2756         .class          = &omap44xx_prcm_hwmod_class,
2757         .clkdm_name     = "l4_wkup_clkdm",
2758         .flags          = HWMOD_NO_IDLEST,
2759         .prcm = {
2760                 .omap4 = {
2761                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2762                 },
2763         },
2764 };
2765
2766 /* cm_core_aon */
2767 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2768         .name           = "cm_core_aon",
2769         .class          = &omap44xx_prcm_hwmod_class,
2770         .flags          = HWMOD_NO_IDLEST,
2771         .prcm = {
2772                 .omap4 = {
2773                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2774                 },
2775         },
2776 };
2777
2778 /* cm_core */
2779 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2780         .name           = "cm_core",
2781         .class          = &omap44xx_prcm_hwmod_class,
2782         .flags          = HWMOD_NO_IDLEST,
2783         .prcm = {
2784                 .omap4 = {
2785                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2786                 },
2787         },
2788 };
2789
2790 /* prm */
2791 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2792         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2793         { .irq = -1 }
2794 };
2795
2796 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2797         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2798         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2799 };
2800
2801 static struct omap_hwmod omap44xx_prm_hwmod = {
2802         .name           = "prm",
2803         .class          = &omap44xx_prcm_hwmod_class,
2804         .mpu_irqs       = omap44xx_prm_irqs,
2805         .rst_lines      = omap44xx_prm_resets,
2806         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2807 };
2808
2809 /*
2810  * 'scrm' class
2811  * system clock and reset manager
2812  */
2813
2814 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2815         .name   = "scrm",
2816 };
2817
2818 /* scrm */
2819 static struct omap_hwmod omap44xx_scrm_hwmod = {
2820         .name           = "scrm",
2821         .class          = &omap44xx_scrm_hwmod_class,
2822         .clkdm_name     = "l4_wkup_clkdm",
2823         .prcm = {
2824                 .omap4 = {
2825                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2826                 },
2827         },
2828 };
2829
2830 /*
2831  * 'sl2if' class
2832  * shared level 2 memory interface
2833  */
2834
2835 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2836         .name   = "sl2if",
2837 };
2838
2839 /* sl2if */
2840 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2841         .name           = "sl2if",
2842         .class          = &omap44xx_sl2if_hwmod_class,
2843         .clkdm_name     = "ivahd_clkdm",
2844         .prcm = {
2845                 .omap4 = {
2846                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2847                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2848                         .modulemode   = MODULEMODE_HWCTRL,
2849                 },
2850         },
2851 };
2852
2853 /*
2854  * 'slimbus' class
2855  * bidirectional, multi-drop, multi-channel two-line serial interface between
2856  * the device and external components
2857  */
2858
2859 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2860         .rev_offs       = 0x0000,
2861         .sysc_offs      = 0x0010,
2862         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2863                            SYSC_HAS_SOFTRESET),
2864         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2865                            SIDLE_SMART_WKUP),
2866         .sysc_fields    = &omap_hwmod_sysc_type2,
2867 };
2868
2869 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2870         .name   = "slimbus",
2871         .sysc   = &omap44xx_slimbus_sysc,
2872 };
2873
2874 /* slimbus1 */
2875 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2876         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2877         { .irq = -1 }
2878 };
2879
2880 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2881         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2882         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2883         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2884         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2885         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2886         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2887         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2888         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2889         { .dma_req = -1 }
2890 };
2891
2892 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2893         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2894         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2895         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2896         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2897 };
2898
2899 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2900         .name           = "slimbus1",
2901         .class          = &omap44xx_slimbus_hwmod_class,
2902         .clkdm_name     = "abe_clkdm",
2903         .mpu_irqs       = omap44xx_slimbus1_irqs,
2904         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2905         .prcm = {
2906                 .omap4 = {
2907                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2908                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2909                         .modulemode   = MODULEMODE_SWCTRL,
2910                 },
2911         },
2912         .opt_clks       = slimbus1_opt_clks,
2913         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2914 };
2915
2916 /* slimbus2 */
2917 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2918         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2919         { .irq = -1 }
2920 };
2921
2922 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2923         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2924         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2925         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2926         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2927         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2928         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2929         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2930         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2931         { .dma_req = -1 }
2932 };
2933
2934 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2935         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2936         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2937         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2938 };
2939
2940 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2941         .name           = "slimbus2",
2942         .class          = &omap44xx_slimbus_hwmod_class,
2943         .clkdm_name     = "l4_per_clkdm",
2944         .mpu_irqs       = omap44xx_slimbus2_irqs,
2945         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2946         .prcm = {
2947                 .omap4 = {
2948                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2949                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2950                         .modulemode   = MODULEMODE_SWCTRL,
2951                 },
2952         },
2953         .opt_clks       = slimbus2_opt_clks,
2954         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2955 };
2956
2957 /*
2958  * 'smartreflex' class
2959  * smartreflex module (monitor silicon performance and outputs a measure of
2960  * performance error)
2961  */
2962
2963 /* The IP is not compliant to type1 / type2 scheme */
2964 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2965         .sidle_shift    = 24,
2966         .enwkup_shift   = 26,
2967 };
2968
2969 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2970         .sysc_offs      = 0x0038,
2971         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2972         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2973                            SIDLE_SMART_WKUP),
2974         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2975 };
2976
2977 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2978         .name   = "smartreflex",
2979         .sysc   = &omap44xx_smartreflex_sysc,
2980         .rev    = 2,
2981 };
2982
2983 /* smartreflex_core */
2984 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2985         .sensor_voltdm_name   = "core",
2986 };
2987
2988 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2989         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2990         { .irq = -1 }
2991 };
2992
2993 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2994         .name           = "smartreflex_core",
2995         .class          = &omap44xx_smartreflex_hwmod_class,
2996         .clkdm_name     = "l4_ao_clkdm",
2997         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2998
2999         .main_clk       = "smartreflex_core_fck",
3000         .prcm = {
3001                 .omap4 = {
3002                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
3003                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
3004                         .modulemode   = MODULEMODE_SWCTRL,
3005                 },
3006         },
3007         .dev_attr       = &smartreflex_core_dev_attr,
3008 };
3009
3010 /* smartreflex_iva */
3011 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3012         .sensor_voltdm_name     = "iva",
3013 };
3014
3015 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3016         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3017         { .irq = -1 }
3018 };
3019
3020 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3021         .name           = "smartreflex_iva",
3022         .class          = &omap44xx_smartreflex_hwmod_class,
3023         .clkdm_name     = "l4_ao_clkdm",
3024         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3025         .main_clk       = "smartreflex_iva_fck",
3026         .prcm = {
3027                 .omap4 = {
3028                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3029                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3030                         .modulemode   = MODULEMODE_SWCTRL,
3031                 },
3032         },
3033         .dev_attr       = &smartreflex_iva_dev_attr,
3034 };
3035
3036 /* smartreflex_mpu */
3037 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3038         .sensor_voltdm_name     = "mpu",
3039 };
3040
3041 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3042         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3043         { .irq = -1 }
3044 };
3045
3046 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3047         .name           = "smartreflex_mpu",
3048         .class          = &omap44xx_smartreflex_hwmod_class,
3049         .clkdm_name     = "l4_ao_clkdm",
3050         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3051         .main_clk       = "smartreflex_mpu_fck",
3052         .prcm = {
3053                 .omap4 = {
3054                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3055                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3056                         .modulemode   = MODULEMODE_SWCTRL,
3057                 },
3058         },
3059         .dev_attr       = &smartreflex_mpu_dev_attr,
3060 };
3061
3062 /*
3063  * 'spinlock' class
3064  * spinlock provides hardware assistance for synchronizing the processes
3065  * running on multiple processors
3066  */
3067
3068 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3069         .rev_offs       = 0x0000,
3070         .sysc_offs      = 0x0010,
3071         .syss_offs      = 0x0014,
3072         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3073                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3074                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3075         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3076                            SIDLE_SMART_WKUP),
3077         .sysc_fields    = &omap_hwmod_sysc_type1,
3078 };
3079
3080 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3081         .name   = "spinlock",
3082         .sysc   = &omap44xx_spinlock_sysc,
3083 };
3084
3085 /* spinlock */
3086 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3087         .name           = "spinlock",
3088         .class          = &omap44xx_spinlock_hwmod_class,
3089         .clkdm_name     = "l4_cfg_clkdm",
3090         .prcm = {
3091                 .omap4 = {
3092                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3093                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3094                 },
3095         },
3096 };
3097
3098 /*
3099  * 'timer' class
3100  * general purpose timer module with accurate 1ms tick
3101  * This class contains several variants: ['timer_1ms', 'timer']
3102  */
3103
3104 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3105         .rev_offs       = 0x0000,
3106         .sysc_offs      = 0x0010,
3107         .syss_offs      = 0x0014,
3108         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3109                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3110                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3111                            SYSS_HAS_RESET_STATUS),
3112         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3113         .clockact       = CLOCKACT_TEST_ICLK,
3114         .sysc_fields    = &omap_hwmod_sysc_type1,
3115 };
3116
3117 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3118         .name   = "timer",
3119         .sysc   = &omap44xx_timer_1ms_sysc,
3120 };
3121
3122 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3123         .rev_offs       = 0x0000,
3124         .sysc_offs      = 0x0010,
3125         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3126                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3127         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3128                            SIDLE_SMART_WKUP),
3129         .sysc_fields    = &omap_hwmod_sysc_type2,
3130 };
3131
3132 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3133         .name   = "timer",
3134         .sysc   = &omap44xx_timer_sysc,
3135 };
3136
3137 /* always-on timers dev attribute */
3138 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3139         .timer_capability       = OMAP_TIMER_ALWON,
3140 };
3141
3142 /* pwm timers dev attribute */
3143 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3144         .timer_capability       = OMAP_TIMER_HAS_PWM,
3145 };
3146
3147 /* timers with DSP interrupt dev attribute */
3148 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3149         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3150 };
3151
3152 /* pwm timers with DSP interrupt dev attribute */
3153 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3154         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3155 };
3156
3157 /* timer1 */
3158 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3159         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3160         { .irq = -1 }
3161 };
3162
3163 static struct omap_hwmod omap44xx_timer1_hwmod = {
3164         .name           = "timer1",
3165         .class          = &omap44xx_timer_1ms_hwmod_class,
3166         .clkdm_name     = "l4_wkup_clkdm",
3167         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3168         .mpu_irqs       = omap44xx_timer1_irqs,
3169         .main_clk       = "dmt1_clk_mux",
3170         .prcm = {
3171                 .omap4 = {
3172                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3173                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3174                         .modulemode   = MODULEMODE_SWCTRL,
3175                 },
3176         },
3177         .dev_attr       = &capability_alwon_dev_attr,
3178 };
3179
3180 /* timer2 */
3181 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3182         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3183         { .irq = -1 }
3184 };
3185
3186 static struct omap_hwmod omap44xx_timer2_hwmod = {
3187         .name           = "timer2",
3188         .class          = &omap44xx_timer_1ms_hwmod_class,
3189         .clkdm_name     = "l4_per_clkdm",
3190         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3191         .mpu_irqs       = omap44xx_timer2_irqs,
3192         .main_clk       = "cm2_dm2_mux",
3193         .prcm = {
3194                 .omap4 = {
3195                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3196                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3197                         .modulemode   = MODULEMODE_SWCTRL,
3198                 },
3199         },
3200 };
3201
3202 /* timer3 */
3203 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3204         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3205         { .irq = -1 }
3206 };
3207
3208 static struct omap_hwmod omap44xx_timer3_hwmod = {
3209         .name           = "timer3",
3210         .class          = &omap44xx_timer_hwmod_class,
3211         .clkdm_name     = "l4_per_clkdm",
3212         .mpu_irqs       = omap44xx_timer3_irqs,
3213         .main_clk       = "cm2_dm3_mux",
3214         .prcm = {
3215                 .omap4 = {
3216                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3217                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3218                         .modulemode   = MODULEMODE_SWCTRL,
3219                 },
3220         },
3221 };
3222
3223 /* timer4 */
3224 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3225         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3226         { .irq = -1 }
3227 };
3228
3229 static struct omap_hwmod omap44xx_timer4_hwmod = {
3230         .name           = "timer4",
3231         .class          = &omap44xx_timer_hwmod_class,
3232         .clkdm_name     = "l4_per_clkdm",
3233         .mpu_irqs       = omap44xx_timer4_irqs,
3234         .main_clk       = "cm2_dm4_mux",
3235         .prcm = {
3236                 .omap4 = {
3237                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3238                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3239                         .modulemode   = MODULEMODE_SWCTRL,
3240                 },
3241         },
3242 };
3243
3244 /* timer5 */
3245 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3246         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3247         { .irq = -1 }
3248 };
3249
3250 static struct omap_hwmod omap44xx_timer5_hwmod = {
3251         .name           = "timer5",
3252         .class          = &omap44xx_timer_hwmod_class,
3253         .clkdm_name     = "abe_clkdm",
3254         .mpu_irqs       = omap44xx_timer5_irqs,
3255         .main_clk       = "timer5_sync_mux",
3256         .prcm = {
3257                 .omap4 = {
3258                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3259                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3260                         .modulemode   = MODULEMODE_SWCTRL,
3261                 },
3262         },
3263         .dev_attr       = &capability_dsp_dev_attr,
3264 };
3265
3266 /* timer6 */
3267 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3268         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3269         { .irq = -1 }
3270 };
3271
3272 static struct omap_hwmod omap44xx_timer6_hwmod = {
3273         .name           = "timer6",
3274         .class          = &omap44xx_timer_hwmod_class,
3275         .clkdm_name     = "abe_clkdm",
3276         .mpu_irqs       = omap44xx_timer6_irqs,
3277         .main_clk       = "timer6_sync_mux",
3278         .prcm = {
3279                 .omap4 = {
3280                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3281                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3282                         .modulemode   = MODULEMODE_SWCTRL,
3283                 },
3284         },
3285         .dev_attr       = &capability_dsp_dev_attr,
3286 };
3287
3288 /* timer7 */
3289 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3290         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3291         { .irq = -1 }
3292 };
3293
3294 static struct omap_hwmod omap44xx_timer7_hwmod = {
3295         .name           = "timer7",
3296         .class          = &omap44xx_timer_hwmod_class,
3297         .clkdm_name     = "abe_clkdm",
3298         .mpu_irqs       = omap44xx_timer7_irqs,
3299         .main_clk       = "timer7_sync_mux",
3300         .prcm = {
3301                 .omap4 = {
3302                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3303                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3304                         .modulemode   = MODULEMODE_SWCTRL,
3305                 },
3306         },
3307         .dev_attr       = &capability_dsp_dev_attr,
3308 };
3309
3310 /* timer8 */
3311 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3312         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3313         { .irq = -1 }
3314 };
3315
3316 static struct omap_hwmod omap44xx_timer8_hwmod = {
3317         .name           = "timer8",
3318         .class          = &omap44xx_timer_hwmod_class,
3319         .clkdm_name     = "abe_clkdm",
3320         .mpu_irqs       = omap44xx_timer8_irqs,
3321         .main_clk       = "timer8_sync_mux",
3322         .prcm = {
3323                 .omap4 = {
3324                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3325                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3326                         .modulemode   = MODULEMODE_SWCTRL,
3327                 },
3328         },
3329         .dev_attr       = &capability_dsp_pwm_dev_attr,
3330 };
3331
3332 /* timer9 */
3333 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3334         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3335         { .irq = -1 }
3336 };
3337
3338 static struct omap_hwmod omap44xx_timer9_hwmod = {
3339         .name           = "timer9",
3340         .class          = &omap44xx_timer_hwmod_class,
3341         .clkdm_name     = "l4_per_clkdm",
3342         .mpu_irqs       = omap44xx_timer9_irqs,
3343         .main_clk       = "cm2_dm9_mux",
3344         .prcm = {
3345                 .omap4 = {
3346                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3347                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3348                         .modulemode   = MODULEMODE_SWCTRL,
3349                 },
3350         },
3351         .dev_attr       = &capability_pwm_dev_attr,
3352 };
3353
3354 /* timer10 */
3355 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3356         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3357         { .irq = -1 }
3358 };
3359
3360 static struct omap_hwmod omap44xx_timer10_hwmod = {
3361         .name           = "timer10",
3362         .class          = &omap44xx_timer_1ms_hwmod_class,
3363         .clkdm_name     = "l4_per_clkdm",
3364         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3365         .mpu_irqs       = omap44xx_timer10_irqs,
3366         .main_clk       = "cm2_dm10_mux",
3367         .prcm = {
3368                 .omap4 = {
3369                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3370                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3371                         .modulemode   = MODULEMODE_SWCTRL,
3372                 },
3373         },
3374         .dev_attr       = &capability_pwm_dev_attr,
3375 };
3376
3377 /* timer11 */
3378 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3379         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3380         { .irq = -1 }
3381 };
3382
3383 static struct omap_hwmod omap44xx_timer11_hwmod = {
3384         .name           = "timer11",
3385         .class          = &omap44xx_timer_hwmod_class,
3386         .clkdm_name     = "l4_per_clkdm",
3387         .mpu_irqs       = omap44xx_timer11_irqs,
3388         .main_clk       = "cm2_dm11_mux",
3389         .prcm = {
3390                 .omap4 = {
3391                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3392                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3393                         .modulemode   = MODULEMODE_SWCTRL,
3394                 },
3395         },
3396         .dev_attr       = &capability_pwm_dev_attr,
3397 };
3398
3399 /*
3400  * 'uart' class
3401  * universal asynchronous receiver/transmitter (uart)
3402  */
3403
3404 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3405         .rev_offs       = 0x0050,
3406         .sysc_offs      = 0x0054,
3407         .syss_offs      = 0x0058,
3408         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3409                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3410                            SYSS_HAS_RESET_STATUS),
3411         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3412                            SIDLE_SMART_WKUP),
3413         .sysc_fields    = &omap_hwmod_sysc_type1,
3414 };
3415
3416 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3417         .name   = "uart",
3418         .sysc   = &omap44xx_uart_sysc,
3419 };
3420
3421 /* uart1 */
3422 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3423         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3424         { .irq = -1 }
3425 };
3426
3427 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3428         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3429         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3430         { .dma_req = -1 }
3431 };
3432
3433 static struct omap_hwmod omap44xx_uart1_hwmod = {
3434         .name           = "uart1",
3435         .class          = &omap44xx_uart_hwmod_class,
3436         .clkdm_name     = "l4_per_clkdm",
3437         .mpu_irqs       = omap44xx_uart1_irqs,
3438         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3439         .main_clk       = "func_48m_fclk",
3440         .prcm = {
3441                 .omap4 = {
3442                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3443                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3444                         .modulemode   = MODULEMODE_SWCTRL,
3445                 },
3446         },
3447 };
3448
3449 /* uart2 */
3450 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3451         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3452         { .irq = -1 }
3453 };
3454
3455 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3456         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3457         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3458         { .dma_req = -1 }
3459 };
3460
3461 static struct omap_hwmod omap44xx_uart2_hwmod = {
3462         .name           = "uart2",
3463         .class          = &omap44xx_uart_hwmod_class,
3464         .clkdm_name     = "l4_per_clkdm",
3465         .mpu_irqs       = omap44xx_uart2_irqs,
3466         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3467         .main_clk       = "func_48m_fclk",
3468         .prcm = {
3469                 .omap4 = {
3470                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3471                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3472                         .modulemode   = MODULEMODE_SWCTRL,
3473                 },
3474         },
3475 };
3476
3477 /* uart3 */
3478 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3479         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3480         { .irq = -1 }
3481 };
3482
3483 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3484         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3485         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3486         { .dma_req = -1 }
3487 };
3488
3489 static struct omap_hwmod omap44xx_uart3_hwmod = {
3490         .name           = "uart3",
3491         .class          = &omap44xx_uart_hwmod_class,
3492         .clkdm_name     = "l4_per_clkdm",
3493         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3494         .mpu_irqs       = omap44xx_uart3_irqs,
3495         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3496         .main_clk       = "func_48m_fclk",
3497         .prcm = {
3498                 .omap4 = {
3499                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3500                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3501                         .modulemode   = MODULEMODE_SWCTRL,
3502                 },
3503         },
3504 };
3505
3506 /* uart4 */
3507 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3508         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3509         { .irq = -1 }
3510 };
3511
3512 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3513         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3514         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3515         { .dma_req = -1 }
3516 };
3517
3518 static struct omap_hwmod omap44xx_uart4_hwmod = {
3519         .name           = "uart4",
3520         .class          = &omap44xx_uart_hwmod_class,
3521         .clkdm_name     = "l4_per_clkdm",
3522         .mpu_irqs       = omap44xx_uart4_irqs,
3523         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3524         .main_clk       = "func_48m_fclk",
3525         .prcm = {
3526                 .omap4 = {
3527                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3528                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3529                         .modulemode   = MODULEMODE_SWCTRL,
3530                 },
3531         },
3532 };
3533
3534 /*
3535  * 'usb_host_fs' class
3536  * full-speed usb host controller
3537  */
3538
3539 /* The IP is not compliant to type1 / type2 scheme */
3540 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3541         .midle_shift    = 4,
3542         .sidle_shift    = 2,
3543         .srst_shift     = 1,
3544 };
3545
3546 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3547         .rev_offs       = 0x0000,
3548         .sysc_offs      = 0x0210,
3549         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3550                            SYSC_HAS_SOFTRESET),
3551         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3552                            SIDLE_SMART_WKUP),
3553         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3554 };
3555
3556 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3557         .name   = "usb_host_fs",
3558         .sysc   = &omap44xx_usb_host_fs_sysc,
3559 };
3560
3561 /* usb_host_fs */
3562 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3563         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3564         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3565         { .irq = -1 }
3566 };
3567
3568 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3569         .name           = "usb_host_fs",
3570         .class          = &omap44xx_usb_host_fs_hwmod_class,
3571         .clkdm_name     = "l3_init_clkdm",
3572         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3573         .main_clk       = "usb_host_fs_fck",
3574         .prcm = {
3575                 .omap4 = {
3576                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3577                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3578                         .modulemode   = MODULEMODE_SWCTRL,
3579                 },
3580         },
3581 };
3582
3583 /*
3584  * 'usb_host_hs' class
3585  * high-speed multi-port usb host controller
3586  */
3587
3588 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3589         .rev_offs       = 0x0000,
3590         .sysc_offs      = 0x0010,
3591         .syss_offs      = 0x0014,
3592         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3593                            SYSC_HAS_SOFTRESET),
3594         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3595                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3596                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3597         .sysc_fields    = &omap_hwmod_sysc_type2,
3598 };
3599
3600 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3601         .name   = "usb_host_hs",
3602         .sysc   = &omap44xx_usb_host_hs_sysc,
3603 };
3604
3605 /* usb_host_hs */
3606 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3607         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3608         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3609         { .irq = -1 }
3610 };
3611
3612 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3613         .name           = "usb_host_hs",
3614         .class          = &omap44xx_usb_host_hs_hwmod_class,
3615         .clkdm_name     = "l3_init_clkdm",
3616         .main_clk       = "usb_host_hs_fck",
3617         .prcm = {
3618                 .omap4 = {
3619                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3620                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3621                         .modulemode   = MODULEMODE_SWCTRL,
3622                 },
3623         },
3624         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3625
3626         /*
3627          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3628          * id: i660
3629          *
3630          * Description:
3631          * In the following configuration :
3632          * - USBHOST module is set to smart-idle mode
3633          * - PRCM asserts idle_req to the USBHOST module ( This typically
3634          *   happens when the system is going to a low power mode : all ports
3635          *   have been suspended, the master part of the USBHOST module has
3636          *   entered the standby state, and SW has cut the functional clocks)
3637          * - an USBHOST interrupt occurs before the module is able to answer
3638          *   idle_ack, typically a remote wakeup IRQ.
3639          * Then the USB HOST module will enter a deadlock situation where it
3640          * is no more accessible nor functional.
3641          *
3642          * Workaround:
3643          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3644          */
3645
3646         /*
3647          * Errata: USB host EHCI may stall when entering smart-standby mode
3648          * Id: i571
3649          *
3650          * Description:
3651          * When the USBHOST module is set to smart-standby mode, and when it is
3652          * ready to enter the standby state (i.e. all ports are suspended and
3653          * all attached devices are in suspend mode), then it can wrongly assert
3654          * the Mstandby signal too early while there are still some residual OCP
3655          * transactions ongoing. If this condition occurs, the internal state
3656          * machine may go to an undefined state and the USB link may be stuck
3657          * upon the next resume.
3658          *
3659          * Workaround:
3660          * Don't use smart standby; use only force standby,
3661          * hence HWMOD_SWSUP_MSTANDBY
3662          */
3663
3664         /*
3665          * During system boot; If the hwmod framework resets the module
3666          * the module will have smart idle settings; which can lead to deadlock
3667          * (above Errata Id:i660); so, dont reset the module during boot;
3668          * Use HWMOD_INIT_NO_RESET.
3669          */
3670
3671         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3672                           HWMOD_INIT_NO_RESET,
3673 };
3674
3675 /*
3676  * 'usb_otg_hs' class
3677  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3678  */
3679
3680 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3681         .rev_offs       = 0x0400,
3682         .sysc_offs      = 0x0404,
3683         .syss_offs      = 0x0408,
3684         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3685                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3686                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3687         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3688                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3689                            MSTANDBY_SMART),
3690         .sysc_fields    = &omap_hwmod_sysc_type1,
3691 };
3692
3693 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3694         .name   = "usb_otg_hs",
3695         .sysc   = &omap44xx_usb_otg_hs_sysc,
3696 };
3697
3698 /* usb_otg_hs */
3699 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3700         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3701         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3702         { .irq = -1 }
3703 };
3704
3705 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3706         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3707 };
3708
3709 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3710         .name           = "usb_otg_hs",
3711         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3712         .clkdm_name     = "l3_init_clkdm",
3713         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3714         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3715         .main_clk       = "usb_otg_hs_ick",
3716         .prcm = {
3717                 .omap4 = {
3718                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3719                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3720                         .modulemode   = MODULEMODE_HWCTRL,
3721                 },
3722         },
3723         .opt_clks       = usb_otg_hs_opt_clks,
3724         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3725 };
3726
3727 /*
3728  * 'usb_tll_hs' class
3729  * usb_tll_hs module is the adapter on the usb_host_hs ports
3730  */
3731
3732 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3733         .rev_offs       = 0x0000,
3734         .sysc_offs      = 0x0010,
3735         .syss_offs      = 0x0014,
3736         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3737                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3738                            SYSC_HAS_AUTOIDLE),
3739         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3740         .sysc_fields    = &omap_hwmod_sysc_type1,
3741 };
3742
3743 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3744         .name   = "usb_tll_hs",
3745         .sysc   = &omap44xx_usb_tll_hs_sysc,
3746 };
3747
3748 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3749         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3750         { .irq = -1 }
3751 };
3752
3753 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3754         .name           = "usb_tll_hs",
3755         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3756         .clkdm_name     = "l3_init_clkdm",
3757         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3758         .main_clk       = "usb_tll_hs_ick",
3759         .prcm = {
3760                 .omap4 = {
3761                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3762                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3763                         .modulemode   = MODULEMODE_HWCTRL,
3764                 },
3765         },
3766 };
3767
3768 /*
3769  * 'wd_timer' class
3770  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3771  * overflow condition
3772  */
3773
3774 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3775         .rev_offs       = 0x0000,
3776         .sysc_offs      = 0x0010,
3777         .syss_offs      = 0x0014,
3778         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3779                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3780         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3781                            SIDLE_SMART_WKUP),
3782         .sysc_fields    = &omap_hwmod_sysc_type1,
3783 };
3784
3785 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3786         .name           = "wd_timer",
3787         .sysc           = &omap44xx_wd_timer_sysc,
3788         .pre_shutdown   = &omap2_wd_timer_disable,
3789         .reset          = &omap2_wd_timer_reset,
3790 };
3791
3792 /* wd_timer2 */
3793 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3794         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3795         { .irq = -1 }
3796 };
3797
3798 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3799         .name           = "wd_timer2",
3800         .class          = &omap44xx_wd_timer_hwmod_class,
3801         .clkdm_name     = "l4_wkup_clkdm",
3802         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3803         .main_clk       = "sys_32k_ck",
3804         .prcm = {
3805                 .omap4 = {
3806                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3807                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3808                         .modulemode   = MODULEMODE_SWCTRL,
3809                 },
3810         },
3811 };
3812
3813 /* wd_timer3 */
3814 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3815         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3816         { .irq = -1 }
3817 };
3818
3819 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3820         .name           = "wd_timer3",
3821         .class          = &omap44xx_wd_timer_hwmod_class,
3822         .clkdm_name     = "abe_clkdm",
3823         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3824         .main_clk       = "sys_32k_ck",
3825         .prcm = {
3826                 .omap4 = {
3827                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3828                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3829                         .modulemode   = MODULEMODE_SWCTRL,
3830                 },
3831         },
3832 };
3833
3834
3835 /*
3836  * interfaces
3837  */
3838
3839 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3840         {
3841                 .pa_start       = 0x4a204000,
3842                 .pa_end         = 0x4a2040ff,
3843                 .flags          = ADDR_TYPE_RT
3844         },
3845         { }
3846 };
3847
3848 /* c2c -> c2c_target_fw */
3849 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3850         .master         = &omap44xx_c2c_hwmod,
3851         .slave          = &omap44xx_c2c_target_fw_hwmod,
3852         .clk            = "div_core_ck",
3853         .addr           = omap44xx_c2c_target_fw_addrs,
3854         .user           = OCP_USER_MPU,
3855 };
3856
3857 /* l4_cfg -> c2c_target_fw */
3858 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3859         .master         = &omap44xx_l4_cfg_hwmod,
3860         .slave          = &omap44xx_c2c_target_fw_hwmod,
3861         .clk            = "l4_div_ck",
3862         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3863 };
3864
3865 /* l3_main_1 -> dmm */
3866 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3867         .master         = &omap44xx_l3_main_1_hwmod,
3868         .slave          = &omap44xx_dmm_hwmod,
3869         .clk            = "l3_div_ck",
3870         .user           = OCP_USER_SDMA,
3871 };
3872
3873 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3874         {
3875                 .pa_start       = 0x4e000000,
3876                 .pa_end         = 0x4e0007ff,
3877                 .flags          = ADDR_TYPE_RT
3878         },
3879         { }
3880 };
3881
3882 /* mpu -> dmm */
3883 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3884         .master         = &omap44xx_mpu_hwmod,
3885         .slave          = &omap44xx_dmm_hwmod,
3886         .clk            = "l3_div_ck",
3887         .addr           = omap44xx_dmm_addrs,
3888         .user           = OCP_USER_MPU,
3889 };
3890
3891 /* c2c -> emif_fw */
3892 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3893         .master         = &omap44xx_c2c_hwmod,
3894         .slave          = &omap44xx_emif_fw_hwmod,
3895         .clk            = "div_core_ck",
3896         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3897 };
3898
3899 /* dmm -> emif_fw */
3900 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3901         .master         = &omap44xx_dmm_hwmod,
3902         .slave          = &omap44xx_emif_fw_hwmod,
3903         .clk            = "l3_div_ck",
3904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3905 };
3906
3907 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3908         {
3909                 .pa_start       = 0x4a20c000,
3910                 .pa_end         = 0x4a20c0ff,
3911                 .flags          = ADDR_TYPE_RT
3912         },
3913         { }
3914 };
3915
3916 /* l4_cfg -> emif_fw */
3917 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3918         .master         = &omap44xx_l4_cfg_hwmod,
3919         .slave          = &omap44xx_emif_fw_hwmod,
3920         .clk            = "l4_div_ck",
3921         .addr           = omap44xx_emif_fw_addrs,
3922         .user           = OCP_USER_MPU,
3923 };
3924
3925 /* iva -> l3_instr */
3926 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3927         .master         = &omap44xx_iva_hwmod,
3928         .slave          = &omap44xx_l3_instr_hwmod,
3929         .clk            = "l3_div_ck",
3930         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3931 };
3932
3933 /* l3_main_3 -> l3_instr */
3934 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3935         .master         = &omap44xx_l3_main_3_hwmod,
3936         .slave          = &omap44xx_l3_instr_hwmod,
3937         .clk            = "l3_div_ck",
3938         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3939 };
3940
3941 /* ocp_wp_noc -> l3_instr */
3942 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3943         .master         = &omap44xx_ocp_wp_noc_hwmod,
3944         .slave          = &omap44xx_l3_instr_hwmod,
3945         .clk            = "l3_div_ck",
3946         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3947 };
3948
3949 /* dsp -> l3_main_1 */
3950 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3951         .master         = &omap44xx_dsp_hwmod,
3952         .slave          = &omap44xx_l3_main_1_hwmod,
3953         .clk            = "l3_div_ck",
3954         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3955 };
3956
3957 /* dss -> l3_main_1 */
3958 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3959         .master         = &omap44xx_dss_hwmod,
3960         .slave          = &omap44xx_l3_main_1_hwmod,
3961         .clk            = "l3_div_ck",
3962         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3963 };
3964
3965 /* l3_main_2 -> l3_main_1 */
3966 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3967         .master         = &omap44xx_l3_main_2_hwmod,
3968         .slave          = &omap44xx_l3_main_1_hwmod,
3969         .clk            = "l3_div_ck",
3970         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3971 };
3972
3973 /* l4_cfg -> l3_main_1 */
3974 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3975         .master         = &omap44xx_l4_cfg_hwmod,
3976         .slave          = &omap44xx_l3_main_1_hwmod,
3977         .clk            = "l4_div_ck",
3978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3979 };
3980
3981 /* mmc1 -> l3_main_1 */
3982 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3983         .master         = &omap44xx_mmc1_hwmod,
3984         .slave          = &omap44xx_l3_main_1_hwmod,
3985         .clk            = "l3_div_ck",
3986         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3987 };
3988
3989 /* mmc2 -> l3_main_1 */
3990 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3991         .master         = &omap44xx_mmc2_hwmod,
3992         .slave          = &omap44xx_l3_main_1_hwmod,
3993         .clk            = "l3_div_ck",
3994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3995 };
3996
3997 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3998         {
3999                 .pa_start       = 0x44000000,
4000                 .pa_end         = 0x44000fff,
4001                 .flags          = ADDR_TYPE_RT
4002         },
4003         { }
4004 };
4005
4006 /* mpu -> l3_main_1 */
4007 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
4008         .master         = &omap44xx_mpu_hwmod,
4009         .slave          = &omap44xx_l3_main_1_hwmod,
4010         .clk            = "l3_div_ck",
4011         .addr           = omap44xx_l3_main_1_addrs,
4012         .user           = OCP_USER_MPU,
4013 };
4014
4015 /* c2c_target_fw -> l3_main_2 */
4016 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
4017         .master         = &omap44xx_c2c_target_fw_hwmod,
4018         .slave          = &omap44xx_l3_main_2_hwmod,
4019         .clk            = "l3_div_ck",
4020         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4021 };
4022
4023 /* debugss -> l3_main_2 */
4024 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
4025         .master         = &omap44xx_debugss_hwmod,
4026         .slave          = &omap44xx_l3_main_2_hwmod,
4027         .clk            = "dbgclk_mux_ck",
4028         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4029 };
4030
4031 /* dma_system -> l3_main_2 */
4032 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
4033         .master         = &omap44xx_dma_system_hwmod,
4034         .slave          = &omap44xx_l3_main_2_hwmod,
4035         .clk            = "l3_div_ck",
4036         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4037 };
4038
4039 /* fdif -> l3_main_2 */
4040 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
4041         .master         = &omap44xx_fdif_hwmod,
4042         .slave          = &omap44xx_l3_main_2_hwmod,
4043         .clk            = "l3_div_ck",
4044         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4045 };
4046
4047 /* gpu -> l3_main_2 */
4048 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4049         .master         = &omap44xx_gpu_hwmod,
4050         .slave          = &omap44xx_l3_main_2_hwmod,
4051         .clk            = "l3_div_ck",
4052         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4053 };
4054
4055 /* hsi -> l3_main_2 */
4056 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4057         .master         = &omap44xx_hsi_hwmod,
4058         .slave          = &omap44xx_l3_main_2_hwmod,
4059         .clk            = "l3_div_ck",
4060         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4061 };
4062
4063 /* ipu -> l3_main_2 */
4064 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4065         .master         = &omap44xx_ipu_hwmod,
4066         .slave          = &omap44xx_l3_main_2_hwmod,
4067         .clk            = "l3_div_ck",
4068         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4069 };
4070
4071 /* iss -> l3_main_2 */
4072 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4073         .master         = &omap44xx_iss_hwmod,
4074         .slave          = &omap44xx_l3_main_2_hwmod,
4075         .clk            = "l3_div_ck",
4076         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4077 };
4078
4079 /* iva -> l3_main_2 */
4080 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4081         .master         = &omap44xx_iva_hwmod,
4082         .slave          = &omap44xx_l3_main_2_hwmod,
4083         .clk            = "l3_div_ck",
4084         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4085 };
4086
4087 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4088         {
4089                 .pa_start       = 0x44800000,
4090                 .pa_end         = 0x44801fff,
4091                 .flags          = ADDR_TYPE_RT
4092         },
4093         { }
4094 };
4095
4096 /* l3_main_1 -> l3_main_2 */
4097 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4098         .master         = &omap44xx_l3_main_1_hwmod,
4099         .slave          = &omap44xx_l3_main_2_hwmod,
4100         .clk            = "l3_div_ck",
4101         .addr           = omap44xx_l3_main_2_addrs,
4102         .user           = OCP_USER_MPU,
4103 };
4104
4105 /* l4_cfg -> l3_main_2 */
4106 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4107         .master         = &omap44xx_l4_cfg_hwmod,
4108         .slave          = &omap44xx_l3_main_2_hwmod,
4109         .clk            = "l4_div_ck",
4110         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4111 };
4112
4113 /* usb_host_fs -> l3_main_2 */
4114 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4115         .master         = &omap44xx_usb_host_fs_hwmod,
4116         .slave          = &omap44xx_l3_main_2_hwmod,
4117         .clk            = "l3_div_ck",
4118         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4119 };
4120
4121 /* usb_host_hs -> l3_main_2 */
4122 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4123         .master         = &omap44xx_usb_host_hs_hwmod,
4124         .slave          = &omap44xx_l3_main_2_hwmod,
4125         .clk            = "l3_div_ck",
4126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4127 };
4128
4129 /* usb_otg_hs -> l3_main_2 */
4130 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4131         .master         = &omap44xx_usb_otg_hs_hwmod,
4132         .slave          = &omap44xx_l3_main_2_hwmod,
4133         .clk            = "l3_div_ck",
4134         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4135 };
4136
4137 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4138         {
4139                 .pa_start       = 0x45000000,
4140                 .pa_end         = 0x45000fff,
4141                 .flags          = ADDR_TYPE_RT
4142         },
4143         { }
4144 };
4145
4146 /* l3_main_1 -> l3_main_3 */
4147 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4148         .master         = &omap44xx_l3_main_1_hwmod,
4149         .slave          = &omap44xx_l3_main_3_hwmod,
4150         .clk            = "l3_div_ck",
4151         .addr           = omap44xx_l3_main_3_addrs,
4152         .user           = OCP_USER_MPU,
4153 };
4154
4155 /* l3_main_2 -> l3_main_3 */
4156 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4157         .master         = &omap44xx_l3_main_2_hwmod,
4158         .slave          = &omap44xx_l3_main_3_hwmod,
4159         .clk            = "l3_div_ck",
4160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4161 };
4162
4163 /* l4_cfg -> l3_main_3 */
4164 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4165         .master         = &omap44xx_l4_cfg_hwmod,
4166         .slave          = &omap44xx_l3_main_3_hwmod,
4167         .clk            = "l4_div_ck",
4168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4169 };
4170
4171 /* aess -> l4_abe */
4172 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4173         .master         = &omap44xx_aess_hwmod,
4174         .slave          = &omap44xx_l4_abe_hwmod,
4175         .clk            = "ocp_abe_iclk",
4176         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4177 };
4178
4179 /* dsp -> l4_abe */
4180 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4181         .master         = &omap44xx_dsp_hwmod,
4182         .slave          = &omap44xx_l4_abe_hwmod,
4183         .clk            = "ocp_abe_iclk",
4184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4185 };
4186
4187 /* l3_main_1 -> l4_abe */
4188 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4189         .master         = &omap44xx_l3_main_1_hwmod,
4190         .slave          = &omap44xx_l4_abe_hwmod,
4191         .clk            = "l3_div_ck",
4192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4193 };
4194
4195 /* mpu -> l4_abe */
4196 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4197         .master         = &omap44xx_mpu_hwmod,
4198         .slave          = &omap44xx_l4_abe_hwmod,
4199         .clk            = "ocp_abe_iclk",
4200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4201 };
4202
4203 /* l3_main_1 -> l4_cfg */
4204 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4205         .master         = &omap44xx_l3_main_1_hwmod,
4206         .slave          = &omap44xx_l4_cfg_hwmod,
4207         .clk            = "l3_div_ck",
4208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4209 };
4210
4211 /* l3_main_2 -> l4_per */
4212 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4213         .master         = &omap44xx_l3_main_2_hwmod,
4214         .slave          = &omap44xx_l4_per_hwmod,
4215         .clk            = "l3_div_ck",
4216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4217 };
4218
4219 /* l4_cfg -> l4_wkup */
4220 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4221         .master         = &omap44xx_l4_cfg_hwmod,
4222         .slave          = &omap44xx_l4_wkup_hwmod,
4223         .clk            = "l4_div_ck",
4224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4225 };
4226
4227 /* mpu -> mpu_private */
4228 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4229         .master         = &omap44xx_mpu_hwmod,
4230         .slave          = &omap44xx_mpu_private_hwmod,
4231         .clk            = "l3_div_ck",
4232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4233 };
4234
4235 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4236         {
4237                 .pa_start       = 0x4a102000,
4238                 .pa_end         = 0x4a10207f,
4239                 .flags          = ADDR_TYPE_RT
4240         },
4241         { }
4242 };
4243
4244 /* l4_cfg -> ocp_wp_noc */
4245 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4246         .master         = &omap44xx_l4_cfg_hwmod,
4247         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4248         .clk            = "l4_div_ck",
4249         .addr           = omap44xx_ocp_wp_noc_addrs,
4250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4251 };
4252
4253 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4254         {
4255                 .name           = "dmem",
4256                 .pa_start       = 0x40180000,
4257                 .pa_end         = 0x4018ffff
4258         },
4259         {
4260                 .name           = "cmem",
4261                 .pa_start       = 0x401a0000,
4262                 .pa_end         = 0x401a1fff
4263         },
4264         {
4265                 .name           = "smem",
4266                 .pa_start       = 0x401c0000,
4267                 .pa_end         = 0x401c5fff
4268         },
4269         {
4270                 .name           = "pmem",
4271                 .pa_start       = 0x401e0000,
4272                 .pa_end         = 0x401e1fff
4273         },
4274         {
4275                 .name           = "mpu",
4276                 .pa_start       = 0x401f1000,
4277                 .pa_end         = 0x401f13ff,
4278                 .flags          = ADDR_TYPE_RT
4279         },
4280         { }
4281 };
4282
4283 /* l4_abe -> aess */
4284 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4285         .master         = &omap44xx_l4_abe_hwmod,
4286         .slave          = &omap44xx_aess_hwmod,
4287         .clk            = "ocp_abe_iclk",
4288         .addr           = omap44xx_aess_addrs,
4289         .user           = OCP_USER_MPU,
4290 };
4291
4292 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4293         {
4294                 .name           = "dmem_dma",
4295                 .pa_start       = 0x49080000,
4296                 .pa_end         = 0x4908ffff
4297         },
4298         {
4299                 .name           = "cmem_dma",
4300                 .pa_start       = 0x490a0000,
4301                 .pa_end         = 0x490a1fff
4302         },
4303         {
4304                 .name           = "smem_dma",
4305                 .pa_start       = 0x490c0000,
4306                 .pa_end         = 0x490c5fff
4307         },
4308         {
4309                 .name           = "pmem_dma",
4310                 .pa_start       = 0x490e0000,
4311                 .pa_end         = 0x490e1fff
4312         },
4313         {
4314                 .name           = "dma",
4315                 .pa_start       = 0x490f1000,
4316                 .pa_end         = 0x490f13ff,
4317                 .flags          = ADDR_TYPE_RT
4318         },
4319         { }
4320 };
4321
4322 /* l4_abe -> aess (dma) */
4323 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4324         .master         = &omap44xx_l4_abe_hwmod,
4325         .slave          = &omap44xx_aess_hwmod,
4326         .clk            = "ocp_abe_iclk",
4327         .addr           = omap44xx_aess_dma_addrs,
4328         .user           = OCP_USER_SDMA,
4329 };
4330
4331 /* l3_main_2 -> c2c */
4332 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4333         .master         = &omap44xx_l3_main_2_hwmod,
4334         .slave          = &omap44xx_c2c_hwmod,
4335         .clk            = "l3_div_ck",
4336         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4337 };
4338
4339 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4340         {
4341                 .pa_start       = 0x4a304000,
4342                 .pa_end         = 0x4a30401f,
4343                 .flags          = ADDR_TYPE_RT
4344         },
4345         { }
4346 };
4347
4348 /* l4_wkup -> counter_32k */
4349 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4350         .master         = &omap44xx_l4_wkup_hwmod,
4351         .slave          = &omap44xx_counter_32k_hwmod,
4352         .clk            = "l4_wkup_clk_mux_ck",
4353         .addr           = omap44xx_counter_32k_addrs,
4354         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4355 };
4356
4357 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4358         {
4359                 .pa_start       = 0x4a002000,
4360                 .pa_end         = 0x4a0027ff,
4361                 .flags          = ADDR_TYPE_RT
4362         },
4363         { }
4364 };
4365
4366 /* l4_cfg -> ctrl_module_core */
4367 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4368         .master         = &omap44xx_l4_cfg_hwmod,
4369         .slave          = &omap44xx_ctrl_module_core_hwmod,
4370         .clk            = "l4_div_ck",
4371         .addr           = omap44xx_ctrl_module_core_addrs,
4372         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4373 };
4374
4375 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4376         {
4377                 .pa_start       = 0x4a100000,
4378                 .pa_end         = 0x4a1007ff,
4379                 .flags          = ADDR_TYPE_RT
4380         },
4381         { }
4382 };
4383
4384 /* l4_cfg -> ctrl_module_pad_core */
4385 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4386         .master         = &omap44xx_l4_cfg_hwmod,
4387         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4388         .clk            = "l4_div_ck",
4389         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4390         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4391 };
4392
4393 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4394         {
4395                 .pa_start       = 0x4a30c000,
4396                 .pa_end         = 0x4a30c7ff,
4397                 .flags          = ADDR_TYPE_RT
4398         },
4399         { }
4400 };
4401
4402 /* l4_wkup -> ctrl_module_wkup */
4403 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4404         .master         = &omap44xx_l4_wkup_hwmod,
4405         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4406         .clk            = "l4_wkup_clk_mux_ck",
4407         .addr           = omap44xx_ctrl_module_wkup_addrs,
4408         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4409 };
4410
4411 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4412         {
4413                 .pa_start       = 0x4a31e000,
4414                 .pa_end         = 0x4a31e7ff,
4415                 .flags          = ADDR_TYPE_RT
4416         },
4417         { }
4418 };
4419
4420 /* l4_wkup -> ctrl_module_pad_wkup */
4421 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4422         .master         = &omap44xx_l4_wkup_hwmod,
4423         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4424         .clk            = "l4_wkup_clk_mux_ck",
4425         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4426         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4427 };
4428
4429 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4430         {
4431                 .pa_start       = 0x54160000,
4432                 .pa_end         = 0x54167fff,
4433                 .flags          = ADDR_TYPE_RT
4434         },
4435         { }
4436 };
4437
4438 /* l3_instr -> debugss */
4439 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4440         .master         = &omap44xx_l3_instr_hwmod,
4441         .slave          = &omap44xx_debugss_hwmod,
4442         .clk            = "l3_div_ck",
4443         .addr           = omap44xx_debugss_addrs,
4444         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4445 };
4446
4447 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4448         {
4449                 .pa_start       = 0x4a056000,
4450                 .pa_end         = 0x4a056fff,
4451                 .flags          = ADDR_TYPE_RT
4452         },
4453         { }
4454 };
4455
4456 /* l4_cfg -> dma_system */
4457 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4458         .master         = &omap44xx_l4_cfg_hwmod,
4459         .slave          = &omap44xx_dma_system_hwmod,
4460         .clk            = "l4_div_ck",
4461         .addr           = omap44xx_dma_system_addrs,
4462         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4463 };
4464
4465 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4466         {
4467                 .name           = "mpu",
4468                 .pa_start       = 0x4012e000,
4469                 .pa_end         = 0x4012e07f,
4470                 .flags          = ADDR_TYPE_RT
4471         },
4472         { }
4473 };
4474
4475 /* l4_abe -> dmic */
4476 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4477         .master         = &omap44xx_l4_abe_hwmod,
4478         .slave          = &omap44xx_dmic_hwmod,
4479         .clk            = "ocp_abe_iclk",
4480         .addr           = omap44xx_dmic_addrs,
4481         .user           = OCP_USER_MPU,
4482 };
4483
4484 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4485         {
4486                 .name           = "dma",
4487                 .pa_start       = 0x4902e000,
4488                 .pa_end         = 0x4902e07f,
4489                 .flags          = ADDR_TYPE_RT
4490         },
4491         { }
4492 };
4493
4494 /* l4_abe -> dmic (dma) */
4495 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4496         .master         = &omap44xx_l4_abe_hwmod,
4497         .slave          = &omap44xx_dmic_hwmod,
4498         .clk            = "ocp_abe_iclk",
4499         .addr           = omap44xx_dmic_dma_addrs,
4500         .user           = OCP_USER_SDMA,
4501 };
4502
4503 /* dsp -> iva */
4504 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4505         .master         = &omap44xx_dsp_hwmod,
4506         .slave          = &omap44xx_iva_hwmod,
4507         .clk            = "dpll_iva_m5x2_ck",
4508         .user           = OCP_USER_DSP,
4509 };
4510
4511 /* dsp -> sl2if */
4512 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4513         .master         = &omap44xx_dsp_hwmod,
4514         .slave          = &omap44xx_sl2if_hwmod,
4515         .clk            = "dpll_iva_m5x2_ck",
4516         .user           = OCP_USER_DSP,
4517 };
4518
4519 /* l4_cfg -> dsp */
4520 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4521         .master         = &omap44xx_l4_cfg_hwmod,
4522         .slave          = &omap44xx_dsp_hwmod,
4523         .clk            = "l4_div_ck",
4524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4525 };
4526
4527 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4528         {
4529                 .pa_start       = 0x58000000,
4530                 .pa_end         = 0x5800007f,
4531                 .flags          = ADDR_TYPE_RT
4532         },
4533         { }
4534 };
4535
4536 /* l3_main_2 -> dss */
4537 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4538         .master         = &omap44xx_l3_main_2_hwmod,
4539         .slave          = &omap44xx_dss_hwmod,
4540         .clk            = "dss_fck",
4541         .addr           = omap44xx_dss_dma_addrs,
4542         .user           = OCP_USER_SDMA,
4543 };
4544
4545 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4546         {
4547                 .pa_start       = 0x48040000,
4548                 .pa_end         = 0x4804007f,
4549                 .flags          = ADDR_TYPE_RT
4550         },
4551         { }
4552 };
4553
4554 /* l4_per -> dss */
4555 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4556         .master         = &omap44xx_l4_per_hwmod,
4557         .slave          = &omap44xx_dss_hwmod,
4558         .clk            = "l4_div_ck",
4559         .addr           = omap44xx_dss_addrs,
4560         .user           = OCP_USER_MPU,
4561 };
4562
4563 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4564         {
4565                 .pa_start       = 0x58001000,
4566                 .pa_end         = 0x58001fff,
4567                 .flags          = ADDR_TYPE_RT
4568         },
4569         { }
4570 };
4571
4572 /* l3_main_2 -> dss_dispc */
4573 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4574         .master         = &omap44xx_l3_main_2_hwmod,
4575         .slave          = &omap44xx_dss_dispc_hwmod,
4576         .clk            = "dss_fck",
4577         .addr           = omap44xx_dss_dispc_dma_addrs,
4578         .user           = OCP_USER_SDMA,
4579 };
4580
4581 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4582         {
4583                 .pa_start       = 0x48041000,
4584                 .pa_end         = 0x48041fff,
4585                 .flags          = ADDR_TYPE_RT
4586         },
4587         { }
4588 };
4589
4590 /* l4_per -> dss_dispc */
4591 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4592         .master         = &omap44xx_l4_per_hwmod,
4593         .slave          = &omap44xx_dss_dispc_hwmod,
4594         .clk            = "l4_div_ck",
4595         .addr           = omap44xx_dss_dispc_addrs,
4596         .user           = OCP_USER_MPU,
4597 };
4598
4599 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4600         {
4601                 .pa_start       = 0x58004000,
4602                 .pa_end         = 0x580041ff,
4603                 .flags          = ADDR_TYPE_RT
4604         },
4605         { }
4606 };
4607
4608 /* l3_main_2 -> dss_dsi1 */
4609 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4610         .master         = &omap44xx_l3_main_2_hwmod,
4611         .slave          = &omap44xx_dss_dsi1_hwmod,
4612         .clk            = "dss_fck",
4613         .addr           = omap44xx_dss_dsi1_dma_addrs,
4614         .user           = OCP_USER_SDMA,
4615 };
4616
4617 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4618         {
4619                 .pa_start       = 0x48044000,
4620                 .pa_end         = 0x480441ff,
4621                 .flags          = ADDR_TYPE_RT
4622         },
4623         { }
4624 };
4625
4626 /* l4_per -> dss_dsi1 */
4627 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4628         .master         = &omap44xx_l4_per_hwmod,
4629         .slave          = &omap44xx_dss_dsi1_hwmod,
4630         .clk            = "l4_div_ck",
4631         .addr           = omap44xx_dss_dsi1_addrs,
4632         .user           = OCP_USER_MPU,
4633 };
4634
4635 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4636         {
4637                 .pa_start       = 0x58005000,
4638                 .pa_end         = 0x580051ff,
4639                 .flags          = ADDR_TYPE_RT
4640         },
4641         { }
4642 };
4643
4644 /* l3_main_2 -> dss_dsi2 */
4645 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4646         .master         = &omap44xx_l3_main_2_hwmod,
4647         .slave          = &omap44xx_dss_dsi2_hwmod,
4648         .clk            = "dss_fck",
4649         .addr           = omap44xx_dss_dsi2_dma_addrs,
4650         .user           = OCP_USER_SDMA,
4651 };
4652
4653 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4654         {
4655                 .pa_start       = 0x48045000,
4656                 .pa_end         = 0x480451ff,
4657                 .flags          = ADDR_TYPE_RT
4658         },
4659         { }
4660 };
4661
4662 /* l4_per -> dss_dsi2 */
4663 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4664         .master         = &omap44xx_l4_per_hwmod,
4665         .slave          = &omap44xx_dss_dsi2_hwmod,
4666         .clk            = "l4_div_ck",
4667         .addr           = omap44xx_dss_dsi2_addrs,
4668         .user           = OCP_USER_MPU,
4669 };
4670
4671 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4672         {
4673                 .pa_start       = 0x58006000,
4674                 .pa_end         = 0x58006fff,
4675                 .flags          = ADDR_TYPE_RT
4676         },
4677         { }
4678 };
4679
4680 /* l3_main_2 -> dss_hdmi */
4681 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4682         .master         = &omap44xx_l3_main_2_hwmod,
4683         .slave          = &omap44xx_dss_hdmi_hwmod,
4684         .clk            = "dss_fck",
4685         .addr           = omap44xx_dss_hdmi_dma_addrs,
4686         .user           = OCP_USER_SDMA,
4687 };
4688
4689 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4690         {
4691                 .pa_start       = 0x48046000,
4692                 .pa_end         = 0x48046fff,
4693                 .flags          = ADDR_TYPE_RT
4694         },
4695         { }
4696 };
4697
4698 /* l4_per -> dss_hdmi */
4699 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4700         .master         = &omap44xx_l4_per_hwmod,
4701         .slave          = &omap44xx_dss_hdmi_hwmod,
4702         .clk            = "l4_div_ck",
4703         .addr           = omap44xx_dss_hdmi_addrs,
4704         .user           = OCP_USER_MPU,
4705 };
4706
4707 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4708         {
4709                 .pa_start       = 0x58002000,
4710                 .pa_end         = 0x580020ff,
4711                 .flags          = ADDR_TYPE_RT
4712         },
4713         { }
4714 };
4715
4716 /* l3_main_2 -> dss_rfbi */
4717 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4718         .master         = &omap44xx_l3_main_2_hwmod,
4719         .slave          = &omap44xx_dss_rfbi_hwmod,
4720         .clk            = "dss_fck",
4721         .addr           = omap44xx_dss_rfbi_dma_addrs,
4722         .user           = OCP_USER_SDMA,
4723 };
4724
4725 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4726         {
4727                 .pa_start       = 0x48042000,
4728                 .pa_end         = 0x480420ff,
4729                 .flags          = ADDR_TYPE_RT
4730         },
4731         { }
4732 };
4733
4734 /* l4_per -> dss_rfbi */
4735 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4736         .master         = &omap44xx_l4_per_hwmod,
4737         .slave          = &omap44xx_dss_rfbi_hwmod,
4738         .clk            = "l4_div_ck",
4739         .addr           = omap44xx_dss_rfbi_addrs,
4740         .user           = OCP_USER_MPU,
4741 };
4742
4743 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4744         {
4745                 .pa_start       = 0x58003000,
4746                 .pa_end         = 0x580030ff,
4747                 .flags          = ADDR_TYPE_RT
4748         },
4749         { }
4750 };
4751
4752 /* l3_main_2 -> dss_venc */
4753 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4754         .master         = &omap44xx_l3_main_2_hwmod,
4755         .slave          = &omap44xx_dss_venc_hwmod,
4756         .clk            = "dss_fck",
4757         .addr           = omap44xx_dss_venc_dma_addrs,
4758         .user           = OCP_USER_SDMA,
4759 };
4760
4761 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4762         {
4763                 .pa_start       = 0x48043000,
4764                 .pa_end         = 0x480430ff,
4765                 .flags          = ADDR_TYPE_RT
4766         },
4767         { }
4768 };
4769
4770 /* l4_per -> dss_venc */
4771 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4772         .master         = &omap44xx_l4_per_hwmod,
4773         .slave          = &omap44xx_dss_venc_hwmod,
4774         .clk            = "l4_div_ck",
4775         .addr           = omap44xx_dss_venc_addrs,
4776         .user           = OCP_USER_MPU,
4777 };
4778
4779 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4780         {
4781                 .pa_start       = 0x48078000,
4782                 .pa_end         = 0x48078fff,
4783                 .flags          = ADDR_TYPE_RT
4784         },
4785         { }
4786 };
4787
4788 /* l4_per -> elm */
4789 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4790         .master         = &omap44xx_l4_per_hwmod,
4791         .slave          = &omap44xx_elm_hwmod,
4792         .clk            = "l4_div_ck",
4793         .addr           = omap44xx_elm_addrs,
4794         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4795 };
4796
4797 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4798         {
4799                 .pa_start       = 0x4c000000,
4800                 .pa_end         = 0x4c0000ff,
4801                 .flags          = ADDR_TYPE_RT
4802         },
4803         { }
4804 };
4805
4806 /* emif_fw -> emif1 */
4807 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4808         .master         = &omap44xx_emif_fw_hwmod,
4809         .slave          = &omap44xx_emif1_hwmod,
4810         .clk            = "l3_div_ck",
4811         .addr           = omap44xx_emif1_addrs,
4812         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4813 };
4814
4815 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4816         {
4817                 .pa_start       = 0x4d000000,
4818                 .pa_end         = 0x4d0000ff,
4819                 .flags          = ADDR_TYPE_RT
4820         },
4821         { }
4822 };
4823
4824 /* emif_fw -> emif2 */
4825 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4826         .master         = &omap44xx_emif_fw_hwmod,
4827         .slave          = &omap44xx_emif2_hwmod,
4828         .clk            = "l3_div_ck",
4829         .addr           = omap44xx_emif2_addrs,
4830         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4831 };
4832
4833 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4834         {
4835                 .pa_start       = 0x4a10a000,
4836                 .pa_end         = 0x4a10a1ff,
4837                 .flags          = ADDR_TYPE_RT
4838         },
4839         { }
4840 };
4841
4842 /* l4_cfg -> fdif */
4843 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4844         .master         = &omap44xx_l4_cfg_hwmod,
4845         .slave          = &omap44xx_fdif_hwmod,
4846         .clk            = "l4_div_ck",
4847         .addr           = omap44xx_fdif_addrs,
4848         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4849 };
4850
4851 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4852         {
4853                 .pa_start       = 0x4a310000,
4854                 .pa_end         = 0x4a3101ff,
4855                 .flags          = ADDR_TYPE_RT
4856         },
4857         { }
4858 };
4859
4860 /* l4_wkup -> gpio1 */
4861 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4862         .master         = &omap44xx_l4_wkup_hwmod,
4863         .slave          = &omap44xx_gpio1_hwmod,
4864         .clk            = "l4_wkup_clk_mux_ck",
4865         .addr           = omap44xx_gpio1_addrs,
4866         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4867 };
4868
4869 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4870         {
4871                 .pa_start       = 0x48055000,
4872                 .pa_end         = 0x480551ff,
4873                 .flags          = ADDR_TYPE_RT
4874         },
4875         { }
4876 };
4877
4878 /* l4_per -> gpio2 */
4879 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4880         .master         = &omap44xx_l4_per_hwmod,
4881         .slave          = &omap44xx_gpio2_hwmod,
4882         .clk            = "l4_div_ck",
4883         .addr           = omap44xx_gpio2_addrs,
4884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4885 };
4886
4887 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4888         {
4889                 .pa_start       = 0x48057000,
4890                 .pa_end         = 0x480571ff,
4891                 .flags          = ADDR_TYPE_RT
4892         },
4893         { }
4894 };
4895
4896 /* l4_per -> gpio3 */
4897 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4898         .master         = &omap44xx_l4_per_hwmod,
4899         .slave          = &omap44xx_gpio3_hwmod,
4900         .clk            = "l4_div_ck",
4901         .addr           = omap44xx_gpio3_addrs,
4902         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4903 };
4904
4905 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4906         {
4907                 .pa_start       = 0x48059000,
4908                 .pa_end         = 0x480591ff,
4909                 .flags          = ADDR_TYPE_RT
4910         },
4911         { }
4912 };
4913
4914 /* l4_per -> gpio4 */
4915 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4916         .master         = &omap44xx_l4_per_hwmod,
4917         .slave          = &omap44xx_gpio4_hwmod,
4918         .clk            = "l4_div_ck",
4919         .addr           = omap44xx_gpio4_addrs,
4920         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4921 };
4922
4923 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4924         {
4925                 .pa_start       = 0x4805b000,
4926                 .pa_end         = 0x4805b1ff,
4927                 .flags          = ADDR_TYPE_RT
4928         },
4929         { }
4930 };
4931
4932 /* l4_per -> gpio5 */
4933 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4934         .master         = &omap44xx_l4_per_hwmod,
4935         .slave          = &omap44xx_gpio5_hwmod,
4936         .clk            = "l4_div_ck",
4937         .addr           = omap44xx_gpio5_addrs,
4938         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4939 };
4940
4941 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4942         {
4943                 .pa_start       = 0x4805d000,
4944                 .pa_end         = 0x4805d1ff,
4945                 .flags          = ADDR_TYPE_RT
4946         },
4947         { }
4948 };
4949
4950 /* l4_per -> gpio6 */
4951 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4952         .master         = &omap44xx_l4_per_hwmod,
4953         .slave          = &omap44xx_gpio6_hwmod,
4954         .clk            = "l4_div_ck",
4955         .addr           = omap44xx_gpio6_addrs,
4956         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4957 };
4958
4959 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4960         {
4961                 .pa_start       = 0x50000000,
4962                 .pa_end         = 0x500003ff,
4963                 .flags          = ADDR_TYPE_RT
4964         },
4965         { }
4966 };
4967
4968 /* l3_main_2 -> gpmc */
4969 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4970         .master         = &omap44xx_l3_main_2_hwmod,
4971         .slave          = &omap44xx_gpmc_hwmod,
4972         .clk            = "l3_div_ck",
4973         .addr           = omap44xx_gpmc_addrs,
4974         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4975 };
4976
4977 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4978         {
4979                 .pa_start       = 0x56000000,
4980                 .pa_end         = 0x5600ffff,
4981                 .flags          = ADDR_TYPE_RT
4982         },
4983         { }
4984 };
4985
4986 /* l3_main_2 -> gpu */
4987 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4988         .master         = &omap44xx_l3_main_2_hwmod,
4989         .slave          = &omap44xx_gpu_hwmod,
4990         .clk            = "l3_div_ck",
4991         .addr           = omap44xx_gpu_addrs,
4992         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4993 };
4994
4995 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4996         {
4997                 .pa_start       = 0x480b2000,
4998                 .pa_end         = 0x480b201f,
4999                 .flags          = ADDR_TYPE_RT
5000         },
5001         { }
5002 };
5003
5004 /* l4_per -> hdq1w */
5005 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
5006         .master         = &omap44xx_l4_per_hwmod,
5007         .slave          = &omap44xx_hdq1w_hwmod,
5008         .clk            = "l4_div_ck",
5009         .addr           = omap44xx_hdq1w_addrs,
5010         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5011 };
5012
5013 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
5014         {
5015                 .pa_start       = 0x4a058000,
5016                 .pa_end         = 0x4a05bfff,
5017                 .flags          = ADDR_TYPE_RT
5018         },
5019         { }
5020 };
5021
5022 /* l4_cfg -> hsi */
5023 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
5024         .master         = &omap44xx_l4_cfg_hwmod,
5025         .slave          = &omap44xx_hsi_hwmod,
5026         .clk            = "l4_div_ck",
5027         .addr           = omap44xx_hsi_addrs,
5028         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5029 };
5030
5031 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
5032         {
5033                 .pa_start       = 0x48070000,
5034                 .pa_end         = 0x480700ff,
5035                 .flags          = ADDR_TYPE_RT
5036         },
5037         { }
5038 };
5039
5040 /* l4_per -> i2c1 */
5041 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
5042         .master         = &omap44xx_l4_per_hwmod,
5043         .slave          = &omap44xx_i2c1_hwmod,
5044         .clk            = "l4_div_ck",
5045         .addr           = omap44xx_i2c1_addrs,
5046         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5047 };
5048
5049 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
5050         {
5051                 .pa_start       = 0x48072000,
5052                 .pa_end         = 0x480720ff,
5053                 .flags          = ADDR_TYPE_RT
5054         },
5055         { }
5056 };
5057
5058 /* l4_per -> i2c2 */
5059 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
5060         .master         = &omap44xx_l4_per_hwmod,
5061         .slave          = &omap44xx_i2c2_hwmod,
5062         .clk            = "l4_div_ck",
5063         .addr           = omap44xx_i2c2_addrs,
5064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5065 };
5066
5067 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
5068         {
5069                 .pa_start       = 0x48060000,
5070                 .pa_end         = 0x480600ff,
5071                 .flags          = ADDR_TYPE_RT
5072         },
5073         { }
5074 };
5075
5076 /* l4_per -> i2c3 */
5077 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
5078         .master         = &omap44xx_l4_per_hwmod,
5079         .slave          = &omap44xx_i2c3_hwmod,
5080         .clk            = "l4_div_ck",
5081         .addr           = omap44xx_i2c3_addrs,
5082         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5083 };
5084
5085 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5086         {
5087                 .pa_start       = 0x48350000,
5088                 .pa_end         = 0x483500ff,
5089                 .flags          = ADDR_TYPE_RT
5090         },
5091         { }
5092 };
5093
5094 /* l4_per -> i2c4 */
5095 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5096         .master         = &omap44xx_l4_per_hwmod,
5097         .slave          = &omap44xx_i2c4_hwmod,
5098         .clk            = "l4_div_ck",
5099         .addr           = omap44xx_i2c4_addrs,
5100         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5101 };
5102
5103 /* l3_main_2 -> ipu */
5104 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5105         .master         = &omap44xx_l3_main_2_hwmod,
5106         .slave          = &omap44xx_ipu_hwmod,
5107         .clk            = "l3_div_ck",
5108         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5109 };
5110
5111 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5112         {
5113                 .pa_start       = 0x52000000,
5114                 .pa_end         = 0x520000ff,
5115                 .flags          = ADDR_TYPE_RT
5116         },
5117         { }
5118 };
5119
5120 /* l3_main_2 -> iss */
5121 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5122         .master         = &omap44xx_l3_main_2_hwmod,
5123         .slave          = &omap44xx_iss_hwmod,
5124         .clk            = "l3_div_ck",
5125         .addr           = omap44xx_iss_addrs,
5126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5127 };
5128
5129 /* iva -> sl2if */
5130 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5131         .master         = &omap44xx_iva_hwmod,
5132         .slave          = &omap44xx_sl2if_hwmod,
5133         .clk            = "dpll_iva_m5x2_ck",
5134         .user           = OCP_USER_IVA,
5135 };
5136
5137 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5138         {
5139                 .pa_start       = 0x5a000000,
5140                 .pa_end         = 0x5a07ffff,
5141                 .flags          = ADDR_TYPE_RT
5142         },
5143         { }
5144 };
5145
5146 /* l3_main_2 -> iva */
5147 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5148         .master         = &omap44xx_l3_main_2_hwmod,
5149         .slave          = &omap44xx_iva_hwmod,
5150         .clk            = "l3_div_ck",
5151         .addr           = omap44xx_iva_addrs,
5152         .user           = OCP_USER_MPU,
5153 };
5154
5155 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5156         {
5157                 .pa_start       = 0x4a31c000,
5158                 .pa_end         = 0x4a31c07f,
5159                 .flags          = ADDR_TYPE_RT
5160         },
5161         { }
5162 };
5163
5164 /* l4_wkup -> kbd */
5165 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5166         .master         = &omap44xx_l4_wkup_hwmod,
5167         .slave          = &omap44xx_kbd_hwmod,
5168         .clk            = "l4_wkup_clk_mux_ck",
5169         .addr           = omap44xx_kbd_addrs,
5170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5171 };
5172
5173 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5174         {
5175                 .pa_start       = 0x4a0f4000,
5176                 .pa_end         = 0x4a0f41ff,
5177                 .flags          = ADDR_TYPE_RT
5178         },
5179         { }
5180 };
5181
5182 /* l4_cfg -> mailbox */
5183 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5184         .master         = &omap44xx_l4_cfg_hwmod,
5185         .slave          = &omap44xx_mailbox_hwmod,
5186         .clk            = "l4_div_ck",
5187         .addr           = omap44xx_mailbox_addrs,
5188         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5189 };
5190
5191 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5192         {
5193                 .pa_start       = 0x40128000,
5194                 .pa_end         = 0x401283ff,
5195                 .flags          = ADDR_TYPE_RT
5196         },
5197         { }
5198 };
5199
5200 /* l4_abe -> mcasp */
5201 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5202         .master         = &omap44xx_l4_abe_hwmod,
5203         .slave          = &omap44xx_mcasp_hwmod,
5204         .clk            = "ocp_abe_iclk",
5205         .addr           = omap44xx_mcasp_addrs,
5206         .user           = OCP_USER_MPU,
5207 };
5208
5209 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5210         {
5211                 .pa_start       = 0x49028000,
5212                 .pa_end         = 0x490283ff,
5213                 .flags          = ADDR_TYPE_RT
5214         },
5215         { }
5216 };
5217
5218 /* l4_abe -> mcasp (dma) */
5219 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5220         .master         = &omap44xx_l4_abe_hwmod,
5221         .slave          = &omap44xx_mcasp_hwmod,
5222         .clk            = "ocp_abe_iclk",
5223         .addr           = omap44xx_mcasp_dma_addrs,
5224         .user           = OCP_USER_SDMA,
5225 };
5226
5227 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5228         {
5229                 .name           = "mpu",
5230                 .pa_start       = 0x40122000,
5231                 .pa_end         = 0x401220ff,
5232                 .flags          = ADDR_TYPE_RT
5233         },
5234         { }
5235 };
5236
5237 /* l4_abe -> mcbsp1 */
5238 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5239         .master         = &omap44xx_l4_abe_hwmod,
5240         .slave          = &omap44xx_mcbsp1_hwmod,
5241         .clk            = "ocp_abe_iclk",
5242         .addr           = omap44xx_mcbsp1_addrs,
5243         .user           = OCP_USER_MPU,
5244 };
5245
5246 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5247         {
5248                 .name           = "dma",
5249                 .pa_start       = 0x49022000,
5250                 .pa_end         = 0x490220ff,
5251                 .flags          = ADDR_TYPE_RT
5252         },
5253         { }
5254 };
5255
5256 /* l4_abe -> mcbsp1 (dma) */
5257 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5258         .master         = &omap44xx_l4_abe_hwmod,
5259         .slave          = &omap44xx_mcbsp1_hwmod,
5260         .clk            = "ocp_abe_iclk",
5261         .addr           = omap44xx_mcbsp1_dma_addrs,
5262         .user           = OCP_USER_SDMA,
5263 };
5264
5265 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5266         {
5267                 .name           = "mpu",
5268                 .pa_start       = 0x40124000,
5269                 .pa_end         = 0x401240ff,
5270                 .flags          = ADDR_TYPE_RT
5271         },
5272         { }
5273 };
5274
5275 /* l4_abe -> mcbsp2 */
5276 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5277         .master         = &omap44xx_l4_abe_hwmod,
5278         .slave          = &omap44xx_mcbsp2_hwmod,
5279         .clk            = "ocp_abe_iclk",
5280         .addr           = omap44xx_mcbsp2_addrs,
5281         .user           = OCP_USER_MPU,
5282 };
5283
5284 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5285         {
5286                 .name           = "dma",
5287                 .pa_start       = 0x49024000,
5288                 .pa_end         = 0x490240ff,
5289                 .flags          = ADDR_TYPE_RT
5290         },
5291         { }
5292 };
5293
5294 /* l4_abe -> mcbsp2 (dma) */
5295 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5296         .master         = &omap44xx_l4_abe_hwmod,
5297         .slave          = &omap44xx_mcbsp2_hwmod,
5298         .clk            = "ocp_abe_iclk",
5299         .addr           = omap44xx_mcbsp2_dma_addrs,
5300         .user           = OCP_USER_SDMA,
5301 };
5302
5303 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5304         {
5305                 .name           = "mpu",
5306                 .pa_start       = 0x40126000,
5307                 .pa_end         = 0x401260ff,
5308                 .flags          = ADDR_TYPE_RT
5309         },
5310         { }
5311 };
5312
5313 /* l4_abe -> mcbsp3 */
5314 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5315         .master         = &omap44xx_l4_abe_hwmod,
5316         .slave          = &omap44xx_mcbsp3_hwmod,
5317         .clk            = "ocp_abe_iclk",
5318         .addr           = omap44xx_mcbsp3_addrs,
5319         .user           = OCP_USER_MPU,
5320 };
5321
5322 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5323         {
5324                 .name           = "dma",
5325                 .pa_start       = 0x49026000,
5326                 .pa_end         = 0x490260ff,
5327                 .flags          = ADDR_TYPE_RT
5328         },
5329         { }
5330 };
5331
5332 /* l4_abe -> mcbsp3 (dma) */
5333 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5334         .master         = &omap44xx_l4_abe_hwmod,
5335         .slave          = &omap44xx_mcbsp3_hwmod,
5336         .clk            = "ocp_abe_iclk",
5337         .addr           = omap44xx_mcbsp3_dma_addrs,
5338         .user           = OCP_USER_SDMA,
5339 };
5340
5341 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5342         {
5343                 .pa_start       = 0x48096000,
5344                 .pa_end         = 0x480960ff,
5345                 .flags          = ADDR_TYPE_RT
5346         },
5347         { }
5348 };
5349
5350 /* l4_per -> mcbsp4 */
5351 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5352         .master         = &omap44xx_l4_per_hwmod,
5353         .slave          = &omap44xx_mcbsp4_hwmod,
5354         .clk            = "l4_div_ck",
5355         .addr           = omap44xx_mcbsp4_addrs,
5356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5357 };
5358
5359 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5360         {
5361                 .name           = "mpu",
5362                 .pa_start       = 0x40132000,
5363                 .pa_end         = 0x4013207f,
5364                 .flags          = ADDR_TYPE_RT
5365         },
5366         { }
5367 };
5368
5369 /* l4_abe -> mcpdm */
5370 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5371         .master         = &omap44xx_l4_abe_hwmod,
5372         .slave          = &omap44xx_mcpdm_hwmod,
5373         .clk            = "ocp_abe_iclk",
5374         .addr           = omap44xx_mcpdm_addrs,
5375         .user           = OCP_USER_MPU,
5376 };
5377
5378 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5379         {
5380                 .name           = "dma",
5381                 .pa_start       = 0x49032000,
5382                 .pa_end         = 0x4903207f,
5383                 .flags          = ADDR_TYPE_RT
5384         },
5385         { }
5386 };
5387
5388 /* l4_abe -> mcpdm (dma) */
5389 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5390         .master         = &omap44xx_l4_abe_hwmod,
5391         .slave          = &omap44xx_mcpdm_hwmod,
5392         .clk            = "ocp_abe_iclk",
5393         .addr           = omap44xx_mcpdm_dma_addrs,
5394         .user           = OCP_USER_SDMA,
5395 };
5396
5397 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5398         {
5399                 .pa_start       = 0x48098000,
5400                 .pa_end         = 0x480981ff,
5401                 .flags          = ADDR_TYPE_RT
5402         },
5403         { }
5404 };
5405
5406 /* l4_per -> mcspi1 */
5407 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5408         .master         = &omap44xx_l4_per_hwmod,
5409         .slave          = &omap44xx_mcspi1_hwmod,
5410         .clk            = "l4_div_ck",
5411         .addr           = omap44xx_mcspi1_addrs,
5412         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5413 };
5414
5415 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5416         {
5417                 .pa_start       = 0x4809a000,
5418                 .pa_end         = 0x4809a1ff,
5419                 .flags          = ADDR_TYPE_RT
5420         },
5421         { }
5422 };
5423
5424 /* l4_per -> mcspi2 */
5425 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5426         .master         = &omap44xx_l4_per_hwmod,
5427         .slave          = &omap44xx_mcspi2_hwmod,
5428         .clk            = "l4_div_ck",
5429         .addr           = omap44xx_mcspi2_addrs,
5430         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5431 };
5432
5433 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5434         {
5435                 .pa_start       = 0x480b8000,
5436                 .pa_end         = 0x480b81ff,
5437                 .flags          = ADDR_TYPE_RT
5438         },
5439         { }
5440 };
5441
5442 /* l4_per -> mcspi3 */
5443 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5444         .master         = &omap44xx_l4_per_hwmod,
5445         .slave          = &omap44xx_mcspi3_hwmod,
5446         .clk            = "l4_div_ck",
5447         .addr           = omap44xx_mcspi3_addrs,
5448         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5449 };
5450
5451 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5452         {
5453                 .pa_start       = 0x480ba000,
5454                 .pa_end         = 0x480ba1ff,
5455                 .flags          = ADDR_TYPE_RT
5456         },
5457         { }
5458 };
5459
5460 /* l4_per -> mcspi4 */
5461 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5462         .master         = &omap44xx_l4_per_hwmod,
5463         .slave          = &omap44xx_mcspi4_hwmod,
5464         .clk            = "l4_div_ck",
5465         .addr           = omap44xx_mcspi4_addrs,
5466         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5467 };
5468
5469 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5470         {
5471                 .pa_start       = 0x4809c000,
5472                 .pa_end         = 0x4809c3ff,
5473                 .flags          = ADDR_TYPE_RT
5474         },
5475         { }
5476 };
5477
5478 /* l4_per -> mmc1 */
5479 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5480         .master         = &omap44xx_l4_per_hwmod,
5481         .slave          = &omap44xx_mmc1_hwmod,
5482         .clk            = "l4_div_ck",
5483         .addr           = omap44xx_mmc1_addrs,
5484         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5485 };
5486
5487 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5488         {
5489                 .pa_start       = 0x480b4000,
5490                 .pa_end         = 0x480b43ff,
5491                 .flags          = ADDR_TYPE_RT
5492         },
5493         { }
5494 };
5495
5496 /* l4_per -> mmc2 */
5497 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5498         .master         = &omap44xx_l4_per_hwmod,
5499         .slave          = &omap44xx_mmc2_hwmod,
5500         .clk            = "l4_div_ck",
5501         .addr           = omap44xx_mmc2_addrs,
5502         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5503 };
5504
5505 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5506         {
5507                 .pa_start       = 0x480ad000,
5508                 .pa_end         = 0x480ad3ff,
5509                 .flags          = ADDR_TYPE_RT
5510         },
5511         { }
5512 };
5513
5514 /* l4_per -> mmc3 */
5515 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5516         .master         = &omap44xx_l4_per_hwmod,
5517         .slave          = &omap44xx_mmc3_hwmod,
5518         .clk            = "l4_div_ck",
5519         .addr           = omap44xx_mmc3_addrs,
5520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5521 };
5522
5523 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5524         {
5525                 .pa_start       = 0x480d1000,
5526                 .pa_end         = 0x480d13ff,
5527                 .flags          = ADDR_TYPE_RT
5528         },
5529         { }
5530 };
5531
5532 /* l4_per -> mmc4 */
5533 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5534         .master         = &omap44xx_l4_per_hwmod,
5535         .slave          = &omap44xx_mmc4_hwmod,
5536         .clk            = "l4_div_ck",
5537         .addr           = omap44xx_mmc4_addrs,
5538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5539 };
5540
5541 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5542         {
5543                 .pa_start       = 0x480d5000,
5544                 .pa_end         = 0x480d53ff,
5545                 .flags          = ADDR_TYPE_RT
5546         },
5547         { }
5548 };
5549
5550 /* l4_per -> mmc5 */
5551 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5552         .master         = &omap44xx_l4_per_hwmod,
5553         .slave          = &omap44xx_mmc5_hwmod,
5554         .clk            = "l4_div_ck",
5555         .addr           = omap44xx_mmc5_addrs,
5556         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5557 };
5558
5559 /* l3_main_2 -> ocmc_ram */
5560 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5561         .master         = &omap44xx_l3_main_2_hwmod,
5562         .slave          = &omap44xx_ocmc_ram_hwmod,
5563         .clk            = "l3_div_ck",
5564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5565 };
5566
5567 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5568         {
5569                 .pa_start       = 0x4a0ad000,
5570                 .pa_end         = 0x4a0ad01f,
5571                 .flags          = ADDR_TYPE_RT
5572         },
5573         { }
5574 };
5575
5576 /* l4_cfg -> ocp2scp_usb_phy */
5577 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5578         .master         = &omap44xx_l4_cfg_hwmod,
5579         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5580         .clk            = "l4_div_ck",
5581         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5582         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5583 };
5584
5585 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5586         {
5587                 .pa_start       = 0x48243000,
5588                 .pa_end         = 0x48243fff,
5589                 .flags          = ADDR_TYPE_RT
5590         },
5591         { }
5592 };
5593
5594 /* mpu_private -> prcm_mpu */
5595 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5596         .master         = &omap44xx_mpu_private_hwmod,
5597         .slave          = &omap44xx_prcm_mpu_hwmod,
5598         .clk            = "l3_div_ck",
5599         .addr           = omap44xx_prcm_mpu_addrs,
5600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5601 };
5602
5603 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5604         {
5605                 .pa_start       = 0x4a004000,
5606                 .pa_end         = 0x4a004fff,
5607                 .flags          = ADDR_TYPE_RT
5608         },
5609         { }
5610 };
5611
5612 /* l4_wkup -> cm_core_aon */
5613 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5614         .master         = &omap44xx_l4_wkup_hwmod,
5615         .slave          = &omap44xx_cm_core_aon_hwmod,
5616         .clk            = "l4_wkup_clk_mux_ck",
5617         .addr           = omap44xx_cm_core_aon_addrs,
5618         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5619 };
5620
5621 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5622         {
5623                 .pa_start       = 0x4a008000,
5624                 .pa_end         = 0x4a009fff,
5625                 .flags          = ADDR_TYPE_RT
5626         },
5627         { }
5628 };
5629
5630 /* l4_cfg -> cm_core */
5631 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5632         .master         = &omap44xx_l4_cfg_hwmod,
5633         .slave          = &omap44xx_cm_core_hwmod,
5634         .clk            = "l4_div_ck",
5635         .addr           = omap44xx_cm_core_addrs,
5636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5637 };
5638
5639 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5640         {
5641                 .pa_start       = 0x4a306000,
5642                 .pa_end         = 0x4a307fff,
5643                 .flags          = ADDR_TYPE_RT
5644         },
5645         { }
5646 };
5647
5648 /* l4_wkup -> prm */
5649 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5650         .master         = &omap44xx_l4_wkup_hwmod,
5651         .slave          = &omap44xx_prm_hwmod,
5652         .clk            = "l4_wkup_clk_mux_ck",
5653         .addr           = omap44xx_prm_addrs,
5654         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5655 };
5656
5657 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5658         {
5659                 .pa_start       = 0x4a30a000,
5660                 .pa_end         = 0x4a30a7ff,
5661                 .flags          = ADDR_TYPE_RT
5662         },
5663         { }
5664 };
5665
5666 /* l4_wkup -> scrm */
5667 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5668         .master         = &omap44xx_l4_wkup_hwmod,
5669         .slave          = &omap44xx_scrm_hwmod,
5670         .clk            = "l4_wkup_clk_mux_ck",
5671         .addr           = omap44xx_scrm_addrs,
5672         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5673 };
5674
5675 /* l3_main_2 -> sl2if */
5676 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5677         .master         = &omap44xx_l3_main_2_hwmod,
5678         .slave          = &omap44xx_sl2if_hwmod,
5679         .clk            = "l3_div_ck",
5680         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5681 };
5682
5683 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5684         {
5685                 .pa_start       = 0x4012c000,
5686                 .pa_end         = 0x4012c3ff,
5687                 .flags          = ADDR_TYPE_RT
5688         },
5689         { }
5690 };
5691
5692 /* l4_abe -> slimbus1 */
5693 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5694         .master         = &omap44xx_l4_abe_hwmod,
5695         .slave          = &omap44xx_slimbus1_hwmod,
5696         .clk            = "ocp_abe_iclk",
5697         .addr           = omap44xx_slimbus1_addrs,
5698         .user           = OCP_USER_MPU,
5699 };
5700
5701 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5702         {
5703                 .pa_start       = 0x4902c000,
5704                 .pa_end         = 0x4902c3ff,
5705                 .flags          = ADDR_TYPE_RT
5706         },
5707         { }
5708 };
5709
5710 /* l4_abe -> slimbus1 (dma) */
5711 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5712         .master         = &omap44xx_l4_abe_hwmod,
5713         .slave          = &omap44xx_slimbus1_hwmod,
5714         .clk            = "ocp_abe_iclk",
5715         .addr           = omap44xx_slimbus1_dma_addrs,
5716         .user           = OCP_USER_SDMA,
5717 };
5718
5719 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5720         {
5721                 .pa_start       = 0x48076000,
5722                 .pa_end         = 0x480763ff,
5723                 .flags          = ADDR_TYPE_RT
5724         },
5725         { }
5726 };
5727
5728 /* l4_per -> slimbus2 */
5729 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5730         .master         = &omap44xx_l4_per_hwmod,
5731         .slave          = &omap44xx_slimbus2_hwmod,
5732         .clk            = "l4_div_ck",
5733         .addr           = omap44xx_slimbus2_addrs,
5734         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5735 };
5736
5737 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5738         {
5739                 .pa_start       = 0x4a0dd000,
5740                 .pa_end         = 0x4a0dd03f,
5741                 .flags          = ADDR_TYPE_RT
5742         },
5743         { }
5744 };
5745
5746 /* l4_cfg -> smartreflex_core */
5747 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5748         .master         = &omap44xx_l4_cfg_hwmod,
5749         .slave          = &omap44xx_smartreflex_core_hwmod,
5750         .clk            = "l4_div_ck",
5751         .addr           = omap44xx_smartreflex_core_addrs,
5752         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5753 };
5754
5755 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5756         {
5757                 .pa_start       = 0x4a0db000,
5758                 .pa_end         = 0x4a0db03f,
5759                 .flags          = ADDR_TYPE_RT
5760         },
5761         { }
5762 };
5763
5764 /* l4_cfg -> smartreflex_iva */
5765 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5766         .master         = &omap44xx_l4_cfg_hwmod,
5767         .slave          = &omap44xx_smartreflex_iva_hwmod,
5768         .clk            = "l4_div_ck",
5769         .addr           = omap44xx_smartreflex_iva_addrs,
5770         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5771 };
5772
5773 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5774         {
5775                 .pa_start       = 0x4a0d9000,
5776                 .pa_end         = 0x4a0d903f,
5777                 .flags          = ADDR_TYPE_RT
5778         },
5779         { }
5780 };
5781
5782 /* l4_cfg -> smartreflex_mpu */
5783 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5784         .master         = &omap44xx_l4_cfg_hwmod,
5785         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5786         .clk            = "l4_div_ck",
5787         .addr           = omap44xx_smartreflex_mpu_addrs,
5788         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5789 };
5790
5791 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5792         {
5793                 .pa_start       = 0x4a0f6000,
5794                 .pa_end         = 0x4a0f6fff,
5795                 .flags          = ADDR_TYPE_RT
5796         },
5797         { }
5798 };
5799
5800 /* l4_cfg -> spinlock */
5801 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5802         .master         = &omap44xx_l4_cfg_hwmod,
5803         .slave          = &omap44xx_spinlock_hwmod,
5804         .clk            = "l4_div_ck",
5805         .addr           = omap44xx_spinlock_addrs,
5806         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5807 };
5808
5809 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5810         {
5811                 .pa_start       = 0x4a318000,
5812                 .pa_end         = 0x4a31807f,
5813                 .flags          = ADDR_TYPE_RT
5814         },
5815         { }
5816 };
5817
5818 /* l4_wkup -> timer1 */
5819 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5820         .master         = &omap44xx_l4_wkup_hwmod,
5821         .slave          = &omap44xx_timer1_hwmod,
5822         .clk            = "l4_wkup_clk_mux_ck",
5823         .addr           = omap44xx_timer1_addrs,
5824         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5825 };
5826
5827 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5828         {
5829                 .pa_start       = 0x48032000,
5830                 .pa_end         = 0x4803207f,
5831                 .flags          = ADDR_TYPE_RT
5832         },
5833         { }
5834 };
5835
5836 /* l4_per -> timer2 */
5837 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5838         .master         = &omap44xx_l4_per_hwmod,
5839         .slave          = &omap44xx_timer2_hwmod,
5840         .clk            = "l4_div_ck",
5841         .addr           = omap44xx_timer2_addrs,
5842         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5843 };
5844
5845 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5846         {
5847                 .pa_start       = 0x48034000,
5848                 .pa_end         = 0x4803407f,
5849                 .flags          = ADDR_TYPE_RT
5850         },
5851         { }
5852 };
5853
5854 /* l4_per -> timer3 */
5855 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5856         .master         = &omap44xx_l4_per_hwmod,
5857         .slave          = &omap44xx_timer3_hwmod,
5858         .clk            = "l4_div_ck",
5859         .addr           = omap44xx_timer3_addrs,
5860         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5861 };
5862
5863 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5864         {
5865                 .pa_start       = 0x48036000,
5866                 .pa_end         = 0x4803607f,
5867                 .flags          = ADDR_TYPE_RT
5868         },
5869         { }
5870 };
5871
5872 /* l4_per -> timer4 */
5873 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5874         .master         = &omap44xx_l4_per_hwmod,
5875         .slave          = &omap44xx_timer4_hwmod,
5876         .clk            = "l4_div_ck",
5877         .addr           = omap44xx_timer4_addrs,
5878         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5879 };
5880
5881 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5882         {
5883                 .pa_start       = 0x40138000,
5884                 .pa_end         = 0x4013807f,
5885                 .flags          = ADDR_TYPE_RT
5886         },
5887         { }
5888 };
5889
5890 /* l4_abe -> timer5 */
5891 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5892         .master         = &omap44xx_l4_abe_hwmod,
5893         .slave          = &omap44xx_timer5_hwmod,
5894         .clk            = "ocp_abe_iclk",
5895         .addr           = omap44xx_timer5_addrs,
5896         .user           = OCP_USER_MPU,
5897 };
5898
5899 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5900         {
5901                 .pa_start       = 0x49038000,
5902                 .pa_end         = 0x4903807f,
5903                 .flags          = ADDR_TYPE_RT
5904         },
5905         { }
5906 };
5907
5908 /* l4_abe -> timer5 (dma) */
5909 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5910         .master         = &omap44xx_l4_abe_hwmod,
5911         .slave          = &omap44xx_timer5_hwmod,
5912         .clk            = "ocp_abe_iclk",
5913         .addr           = omap44xx_timer5_dma_addrs,
5914         .user           = OCP_USER_SDMA,
5915 };
5916
5917 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5918         {
5919                 .pa_start       = 0x4013a000,
5920                 .pa_end         = 0x4013a07f,
5921                 .flags          = ADDR_TYPE_RT
5922         },
5923         { }
5924 };
5925
5926 /* l4_abe -> timer6 */
5927 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5928         .master         = &omap44xx_l4_abe_hwmod,
5929         .slave          = &omap44xx_timer6_hwmod,
5930         .clk            = "ocp_abe_iclk",
5931         .addr           = omap44xx_timer6_addrs,
5932         .user           = OCP_USER_MPU,
5933 };
5934
5935 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5936         {
5937                 .pa_start       = 0x4903a000,
5938                 .pa_end         = 0x4903a07f,
5939                 .flags          = ADDR_TYPE_RT
5940         },
5941         { }
5942 };
5943
5944 /* l4_abe -> timer6 (dma) */
5945 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5946         .master         = &omap44xx_l4_abe_hwmod,
5947         .slave          = &omap44xx_timer6_hwmod,
5948         .clk            = "ocp_abe_iclk",
5949         .addr           = omap44xx_timer6_dma_addrs,
5950         .user           = OCP_USER_SDMA,
5951 };
5952
5953 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5954         {
5955                 .pa_start       = 0x4013c000,
5956                 .pa_end         = 0x4013c07f,
5957                 .flags          = ADDR_TYPE_RT
5958         },
5959         { }
5960 };
5961
5962 /* l4_abe -> timer7 */
5963 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5964         .master         = &omap44xx_l4_abe_hwmod,
5965         .slave          = &omap44xx_timer7_hwmod,
5966         .clk            = "ocp_abe_iclk",
5967         .addr           = omap44xx_timer7_addrs,
5968         .user           = OCP_USER_MPU,
5969 };
5970
5971 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5972         {
5973                 .pa_start       = 0x4903c000,
5974                 .pa_end         = 0x4903c07f,
5975                 .flags          = ADDR_TYPE_RT
5976         },
5977         { }
5978 };
5979
5980 /* l4_abe -> timer7 (dma) */
5981 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5982         .master         = &omap44xx_l4_abe_hwmod,
5983         .slave          = &omap44xx_timer7_hwmod,
5984         .clk            = "ocp_abe_iclk",
5985         .addr           = omap44xx_timer7_dma_addrs,
5986         .user           = OCP_USER_SDMA,
5987 };
5988
5989 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5990         {
5991                 .pa_start       = 0x4013e000,
5992                 .pa_end         = 0x4013e07f,
5993                 .flags          = ADDR_TYPE_RT
5994         },
5995         { }
5996 };
5997
5998 /* l4_abe -> timer8 */
5999 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
6000         .master         = &omap44xx_l4_abe_hwmod,
6001         .slave          = &omap44xx_timer8_hwmod,
6002         .clk            = "ocp_abe_iclk",
6003         .addr           = omap44xx_timer8_addrs,
6004         .user           = OCP_USER_MPU,
6005 };
6006
6007 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
6008         {
6009                 .pa_start       = 0x4903e000,
6010                 .pa_end         = 0x4903e07f,
6011                 .flags          = ADDR_TYPE_RT
6012         },
6013         { }
6014 };
6015
6016 /* l4_abe -> timer8 (dma) */
6017 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
6018         .master         = &omap44xx_l4_abe_hwmod,
6019         .slave          = &omap44xx_timer8_hwmod,
6020         .clk            = "ocp_abe_iclk",
6021         .addr           = omap44xx_timer8_dma_addrs,
6022         .user           = OCP_USER_SDMA,
6023 };
6024
6025 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
6026         {
6027                 .pa_start       = 0x4803e000,
6028                 .pa_end         = 0x4803e07f,
6029                 .flags          = ADDR_TYPE_RT
6030         },
6031         { }
6032 };
6033
6034 /* l4_per -> timer9 */
6035 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
6036         .master         = &omap44xx_l4_per_hwmod,
6037         .slave          = &omap44xx_timer9_hwmod,
6038         .clk            = "l4_div_ck",
6039         .addr           = omap44xx_timer9_addrs,
6040         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6041 };
6042
6043 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
6044         {
6045                 .pa_start       = 0x48086000,
6046                 .pa_end         = 0x4808607f,
6047                 .flags          = ADDR_TYPE_RT
6048         },
6049         { }
6050 };
6051
6052 /* l4_per -> timer10 */
6053 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
6054         .master         = &omap44xx_l4_per_hwmod,
6055         .slave          = &omap44xx_timer10_hwmod,
6056         .clk            = "l4_div_ck",
6057         .addr           = omap44xx_timer10_addrs,
6058         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6059 };
6060
6061 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
6062         {
6063                 .pa_start       = 0x48088000,
6064                 .pa_end         = 0x4808807f,
6065                 .flags          = ADDR_TYPE_RT
6066         },
6067         { }
6068 };
6069
6070 /* l4_per -> timer11 */
6071 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
6072         .master         = &omap44xx_l4_per_hwmod,
6073         .slave          = &omap44xx_timer11_hwmod,
6074         .clk            = "l4_div_ck",
6075         .addr           = omap44xx_timer11_addrs,
6076         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6077 };
6078
6079 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
6080         {
6081                 .pa_start       = 0x4806a000,
6082                 .pa_end         = 0x4806a0ff,
6083                 .flags          = ADDR_TYPE_RT
6084         },
6085         { }
6086 };
6087
6088 /* l4_per -> uart1 */
6089 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6090         .master         = &omap44xx_l4_per_hwmod,
6091         .slave          = &omap44xx_uart1_hwmod,
6092         .clk            = "l4_div_ck",
6093         .addr           = omap44xx_uart1_addrs,
6094         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6095 };
6096
6097 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6098         {
6099                 .pa_start       = 0x4806c000,
6100                 .pa_end         = 0x4806c0ff,
6101                 .flags          = ADDR_TYPE_RT
6102         },
6103         { }
6104 };
6105
6106 /* l4_per -> uart2 */
6107 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6108         .master         = &omap44xx_l4_per_hwmod,
6109         .slave          = &omap44xx_uart2_hwmod,
6110         .clk            = "l4_div_ck",
6111         .addr           = omap44xx_uart2_addrs,
6112         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6113 };
6114
6115 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6116         {
6117                 .pa_start       = 0x48020000,
6118                 .pa_end         = 0x480200ff,
6119                 .flags          = ADDR_TYPE_RT
6120         },
6121         { }
6122 };
6123
6124 /* l4_per -> uart3 */
6125 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6126         .master         = &omap44xx_l4_per_hwmod,
6127         .slave          = &omap44xx_uart3_hwmod,
6128         .clk            = "l4_div_ck",
6129         .addr           = omap44xx_uart3_addrs,
6130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6131 };
6132
6133 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6134         {
6135                 .pa_start       = 0x4806e000,
6136                 .pa_end         = 0x4806e0ff,
6137                 .flags          = ADDR_TYPE_RT
6138         },
6139         { }
6140 };
6141
6142 /* l4_per -> uart4 */
6143 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6144         .master         = &omap44xx_l4_per_hwmod,
6145         .slave          = &omap44xx_uart4_hwmod,
6146         .clk            = "l4_div_ck",
6147         .addr           = omap44xx_uart4_addrs,
6148         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6149 };
6150
6151 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6152         {
6153                 .pa_start       = 0x4a0a9000,
6154                 .pa_end         = 0x4a0a93ff,
6155                 .flags          = ADDR_TYPE_RT
6156         },
6157         { }
6158 };
6159
6160 /* l4_cfg -> usb_host_fs */
6161 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6162         .master         = &omap44xx_l4_cfg_hwmod,
6163         .slave          = &omap44xx_usb_host_fs_hwmod,
6164         .clk            = "l4_div_ck",
6165         .addr           = omap44xx_usb_host_fs_addrs,
6166         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6167 };
6168
6169 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6170         {
6171                 .name           = "uhh",
6172                 .pa_start       = 0x4a064000,
6173                 .pa_end         = 0x4a0647ff,
6174                 .flags          = ADDR_TYPE_RT
6175         },
6176         {
6177                 .name           = "ohci",
6178                 .pa_start       = 0x4a064800,
6179                 .pa_end         = 0x4a064bff,
6180         },
6181         {
6182                 .name           = "ehci",
6183                 .pa_start       = 0x4a064c00,
6184                 .pa_end         = 0x4a064fff,
6185         },
6186         {}
6187 };
6188
6189 /* l4_cfg -> usb_host_hs */
6190 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6191         .master         = &omap44xx_l4_cfg_hwmod,
6192         .slave          = &omap44xx_usb_host_hs_hwmod,
6193         .clk            = "l4_div_ck",
6194         .addr           = omap44xx_usb_host_hs_addrs,
6195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6196 };
6197
6198 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6199         {
6200                 .pa_start       = 0x4a0ab000,
6201                 .pa_end         = 0x4a0ab7ff,
6202                 .flags          = ADDR_TYPE_RT
6203         },
6204         { }
6205 };
6206
6207 /* l4_cfg -> usb_otg_hs */
6208 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6209         .master         = &omap44xx_l4_cfg_hwmod,
6210         .slave          = &omap44xx_usb_otg_hs_hwmod,
6211         .clk            = "l4_div_ck",
6212         .addr           = omap44xx_usb_otg_hs_addrs,
6213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6214 };
6215
6216 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6217         {
6218                 .name           = "tll",
6219                 .pa_start       = 0x4a062000,
6220                 .pa_end         = 0x4a063fff,
6221                 .flags          = ADDR_TYPE_RT
6222         },
6223         {}
6224 };
6225
6226 /* l4_cfg -> usb_tll_hs */
6227 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6228         .master         = &omap44xx_l4_cfg_hwmod,
6229         .slave          = &omap44xx_usb_tll_hs_hwmod,
6230         .clk            = "l4_div_ck",
6231         .addr           = omap44xx_usb_tll_hs_addrs,
6232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6233 };
6234
6235 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6236         {
6237                 .pa_start       = 0x4a314000,
6238                 .pa_end         = 0x4a31407f,
6239                 .flags          = ADDR_TYPE_RT
6240         },
6241         { }
6242 };
6243
6244 /* l4_wkup -> wd_timer2 */
6245 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6246         .master         = &omap44xx_l4_wkup_hwmod,
6247         .slave          = &omap44xx_wd_timer2_hwmod,
6248         .clk            = "l4_wkup_clk_mux_ck",
6249         .addr           = omap44xx_wd_timer2_addrs,
6250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6251 };
6252
6253 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6254         {
6255                 .pa_start       = 0x40130000,
6256                 .pa_end         = 0x4013007f,
6257                 .flags          = ADDR_TYPE_RT
6258         },
6259         { }
6260 };
6261
6262 /* l4_abe -> wd_timer3 */
6263 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6264         .master         = &omap44xx_l4_abe_hwmod,
6265         .slave          = &omap44xx_wd_timer3_hwmod,
6266         .clk            = "ocp_abe_iclk",
6267         .addr           = omap44xx_wd_timer3_addrs,
6268         .user           = OCP_USER_MPU,
6269 };
6270
6271 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6272         {
6273                 .pa_start       = 0x49030000,
6274                 .pa_end         = 0x4903007f,
6275                 .flags          = ADDR_TYPE_RT
6276         },
6277         { }
6278 };
6279
6280 /* l4_abe -> wd_timer3 (dma) */
6281 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6282         .master         = &omap44xx_l4_abe_hwmod,
6283         .slave          = &omap44xx_wd_timer3_hwmod,
6284         .clk            = "ocp_abe_iclk",
6285         .addr           = omap44xx_wd_timer3_dma_addrs,
6286         .user           = OCP_USER_SDMA,
6287 };
6288
6289 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6290         &omap44xx_c2c__c2c_target_fw,
6291         &omap44xx_l4_cfg__c2c_target_fw,
6292         &omap44xx_l3_main_1__dmm,
6293         &omap44xx_mpu__dmm,
6294         &omap44xx_c2c__emif_fw,
6295         &omap44xx_dmm__emif_fw,
6296         &omap44xx_l4_cfg__emif_fw,
6297         &omap44xx_iva__l3_instr,
6298         &omap44xx_l3_main_3__l3_instr,
6299         &omap44xx_ocp_wp_noc__l3_instr,
6300         &omap44xx_dsp__l3_main_1,
6301         &omap44xx_dss__l3_main_1,
6302         &omap44xx_l3_main_2__l3_main_1,
6303         &omap44xx_l4_cfg__l3_main_1,
6304         &omap44xx_mmc1__l3_main_1,
6305         &omap44xx_mmc2__l3_main_1,
6306         &omap44xx_mpu__l3_main_1,
6307         &omap44xx_c2c_target_fw__l3_main_2,
6308         &omap44xx_debugss__l3_main_2,
6309         &omap44xx_dma_system__l3_main_2,
6310         &omap44xx_fdif__l3_main_2,
6311         &omap44xx_gpu__l3_main_2,
6312         &omap44xx_hsi__l3_main_2,
6313         &omap44xx_ipu__l3_main_2,
6314         &omap44xx_iss__l3_main_2,
6315         &omap44xx_iva__l3_main_2,
6316         &omap44xx_l3_main_1__l3_main_2,
6317         &omap44xx_l4_cfg__l3_main_2,
6318         /* &omap44xx_usb_host_fs__l3_main_2, */
6319         &omap44xx_usb_host_hs__l3_main_2,
6320         &omap44xx_usb_otg_hs__l3_main_2,
6321         &omap44xx_l3_main_1__l3_main_3,
6322         &omap44xx_l3_main_2__l3_main_3,
6323         &omap44xx_l4_cfg__l3_main_3,
6324         &omap44xx_aess__l4_abe,
6325         &omap44xx_dsp__l4_abe,
6326         &omap44xx_l3_main_1__l4_abe,
6327         &omap44xx_mpu__l4_abe,
6328         &omap44xx_l3_main_1__l4_cfg,
6329         &omap44xx_l3_main_2__l4_per,
6330         &omap44xx_l4_cfg__l4_wkup,
6331         &omap44xx_mpu__mpu_private,
6332         &omap44xx_l4_cfg__ocp_wp_noc,
6333         &omap44xx_l4_abe__aess,
6334         &omap44xx_l4_abe__aess_dma,
6335         &omap44xx_l3_main_2__c2c,
6336         &omap44xx_l4_wkup__counter_32k,
6337         &omap44xx_l4_cfg__ctrl_module_core,
6338         &omap44xx_l4_cfg__ctrl_module_pad_core,
6339         &omap44xx_l4_wkup__ctrl_module_wkup,
6340         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6341         &omap44xx_l3_instr__debugss,
6342         &omap44xx_l4_cfg__dma_system,
6343         &omap44xx_l4_abe__dmic,
6344         &omap44xx_l4_abe__dmic_dma,
6345         &omap44xx_dsp__iva,
6346         /* &omap44xx_dsp__sl2if, */
6347         &omap44xx_l4_cfg__dsp,
6348         &omap44xx_l3_main_2__dss,
6349         &omap44xx_l4_per__dss,
6350         &omap44xx_l3_main_2__dss_dispc,
6351         &omap44xx_l4_per__dss_dispc,
6352         &omap44xx_l3_main_2__dss_dsi1,
6353         &omap44xx_l4_per__dss_dsi1,
6354         &omap44xx_l3_main_2__dss_dsi2,
6355         &omap44xx_l4_per__dss_dsi2,
6356         &omap44xx_l3_main_2__dss_hdmi,
6357         &omap44xx_l4_per__dss_hdmi,
6358         &omap44xx_l3_main_2__dss_rfbi,
6359         &omap44xx_l4_per__dss_rfbi,
6360         &omap44xx_l3_main_2__dss_venc,
6361         &omap44xx_l4_per__dss_venc,
6362         &omap44xx_l4_per__elm,
6363         &omap44xx_emif_fw__emif1,
6364         &omap44xx_emif_fw__emif2,
6365         &omap44xx_l4_cfg__fdif,
6366         &omap44xx_l4_wkup__gpio1,
6367         &omap44xx_l4_per__gpio2,
6368         &omap44xx_l4_per__gpio3,
6369         &omap44xx_l4_per__gpio4,
6370         &omap44xx_l4_per__gpio5,
6371         &omap44xx_l4_per__gpio6,
6372         &omap44xx_l3_main_2__gpmc,
6373         &omap44xx_l3_main_2__gpu,
6374         &omap44xx_l4_per__hdq1w,
6375         &omap44xx_l4_cfg__hsi,
6376         &omap44xx_l4_per__i2c1,
6377         &omap44xx_l4_per__i2c2,
6378         &omap44xx_l4_per__i2c3,
6379         &omap44xx_l4_per__i2c4,
6380         &omap44xx_l3_main_2__ipu,
6381         &omap44xx_l3_main_2__iss,
6382         /* &omap44xx_iva__sl2if, */
6383         &omap44xx_l3_main_2__iva,
6384         &omap44xx_l4_wkup__kbd,
6385         &omap44xx_l4_cfg__mailbox,
6386         &omap44xx_l4_abe__mcasp,
6387         &omap44xx_l4_abe__mcasp_dma,
6388         &omap44xx_l4_abe__mcbsp1,
6389         &omap44xx_l4_abe__mcbsp1_dma,
6390         &omap44xx_l4_abe__mcbsp2,
6391         &omap44xx_l4_abe__mcbsp2_dma,
6392         &omap44xx_l4_abe__mcbsp3,
6393         &omap44xx_l4_abe__mcbsp3_dma,
6394         &omap44xx_l4_per__mcbsp4,
6395         &omap44xx_l4_abe__mcpdm,
6396         &omap44xx_l4_abe__mcpdm_dma,
6397         &omap44xx_l4_per__mcspi1,
6398         &omap44xx_l4_per__mcspi2,
6399         &omap44xx_l4_per__mcspi3,
6400         &omap44xx_l4_per__mcspi4,
6401         &omap44xx_l4_per__mmc1,
6402         &omap44xx_l4_per__mmc2,
6403         &omap44xx_l4_per__mmc3,
6404         &omap44xx_l4_per__mmc4,
6405         &omap44xx_l4_per__mmc5,
6406         &omap44xx_l3_main_2__mmu_ipu,
6407         &omap44xx_l4_cfg__mmu_dsp,
6408         &omap44xx_l3_main_2__ocmc_ram,
6409         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6410         &omap44xx_mpu_private__prcm_mpu,
6411         &omap44xx_l4_wkup__cm_core_aon,
6412         &omap44xx_l4_cfg__cm_core,
6413         &omap44xx_l4_wkup__prm,
6414         &omap44xx_l4_wkup__scrm,
6415         /* &omap44xx_l3_main_2__sl2if, */
6416         &omap44xx_l4_abe__slimbus1,
6417         &omap44xx_l4_abe__slimbus1_dma,
6418         &omap44xx_l4_per__slimbus2,
6419         &omap44xx_l4_cfg__smartreflex_core,
6420         &omap44xx_l4_cfg__smartreflex_iva,
6421         &omap44xx_l4_cfg__smartreflex_mpu,
6422         &omap44xx_l4_cfg__spinlock,
6423         &omap44xx_l4_wkup__timer1,
6424         &omap44xx_l4_per__timer2,
6425         &omap44xx_l4_per__timer3,
6426         &omap44xx_l4_per__timer4,
6427         &omap44xx_l4_abe__timer5,
6428         &omap44xx_l4_abe__timer5_dma,
6429         &omap44xx_l4_abe__timer6,
6430         &omap44xx_l4_abe__timer6_dma,
6431         &omap44xx_l4_abe__timer7,
6432         &omap44xx_l4_abe__timer7_dma,
6433         &omap44xx_l4_abe__timer8,
6434         &omap44xx_l4_abe__timer8_dma,
6435         &omap44xx_l4_per__timer9,
6436         &omap44xx_l4_per__timer10,
6437         &omap44xx_l4_per__timer11,
6438         &omap44xx_l4_per__uart1,
6439         &omap44xx_l4_per__uart2,
6440         &omap44xx_l4_per__uart3,
6441         &omap44xx_l4_per__uart4,
6442         /* &omap44xx_l4_cfg__usb_host_fs, */
6443         &omap44xx_l4_cfg__usb_host_hs,
6444         &omap44xx_l4_cfg__usb_otg_hs,
6445         &omap44xx_l4_cfg__usb_tll_hs,
6446         &omap44xx_l4_wkup__wd_timer2,
6447         &omap44xx_l4_abe__wd_timer3,
6448         &omap44xx_l4_abe__wd_timer3_dma,
6449         NULL,
6450 };
6451
6452 int __init omap44xx_hwmod_init(void)
6453 {
6454         omap_hwmod_init();
6455         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6456 }
6457